Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5015654

1

T1

2383

T2

555

T3

54045

full_word

2483018

1

T1

721

T2

500

T3

13733

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7498352	1			T1	3104		T2	1055		T3	67778
auto[TlIntgErrCmd]	111	1			T264	8		T265	5		T266	8
auto[TlIntgErrData]	106	1			T264	2		T265	12		T266	7
auto[TlIntgErrBoth]	103	1			T265	3		T266	5		T332	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5814519

1

T1

2851

T2

928

T3

62782

auto[1]

1684153

1

T1

253

T2

127

T3

4996

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3855658	1			T1	2236		T2	488		T3	51118
auto[TlIntgErrNone]	partial	auto[1]	1159700	1			T1	147		T2	67		T3	2927
auto[TlIntgErrNone]	full_word	auto[0]	1958711	1			T1	615		T2	440		T3	11664
auto[TlIntgErrNone]	full_word	auto[1]	524283	1			T1	106		T2	60		T3	2069
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T264	4		T265	1		T266	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T264	3		T265	3		T266	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T340	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T264	1		T265	1		T338	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T264	2		T265	8		T266	4
auto[TlIntgErrData]	partial	auto[1]	40	1			T265	4		T266	2		T338	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T338	1		T341	1		T339	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T266	1		T334	1		T333	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T266	3		T332	2		T338	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T265	3		T266	2		T332	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T338	1		T340	1		T336	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T334	1		T336	2		T339	2