SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
51.81 | 51.81 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
51.81 | 51.81 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
51.81 | 51.81 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_prim_double_lfsr |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
51.81 | 51.81 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
51.81 | 51.81 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_prim_double_lfsr |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 4 | 80.00 |
Total Bits | 166 | 86 | 51.81 |
Total Bits 0->1 | 83 | 43 | 51.81 |
Total Bits 1->0 | 83 | 43 | 51.81 |
Ports | 5 | 4 | 80.00 |
Port Bits | 166 | 86 | 51.81 |
Port Bits 0->1 | 83 | 43 | 51.81 |
Port Bits 1->0 | 83 | 43 | 51.81 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
seed_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
seed_i[39:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
lfsr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
entropy_i[39:0] | No | No | No | INPUT | ||
state_o[39:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 4 | 80.00 |
Total Bits | 166 | 86 | 51.81 |
Total Bits 0->1 | 83 | 43 | 51.81 |
Total Bits 1->0 | 83 | 43 | 51.81 |
Ports | 5 | 4 | 80.00 |
Port Bits | 166 | 86 | 51.81 |
Port Bits 0->1 | 83 | 43 | 51.81 |
Port Bits 1->0 | 83 | 43 | 51.81 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
seed_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
seed_i[39:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
lfsr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
entropy_i[39:0] | No | No | No | INPUT | ||
state_o[39:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 4 | 80.00 |
Total Bits | 166 | 86 | 51.81 |
Total Bits 0->1 | 83 | 43 | 51.81 |
Total Bits 1->0 | 83 | 43 | 51.81 |
Ports | 5 | 4 | 80.00 |
Port Bits | 166 | 86 | 51.81 |
Port Bits 0->1 | 83 | 43 | 51.81 |
Port Bits 1->0 | 83 | 43 | 51.81 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
seed_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
seed_i[39:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
lfsr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
entropy_i[39:0] | No | No | No | INPUT | ||
state_o[39:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |