Module Definition
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Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.81 51.81


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.81 51.81


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_double_lfsr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.81 51.81


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.81 51.81


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_double_lfsr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_lfsr
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 166 86 51.81
Total Bits 0->1 83 43 51.81
Total Bits 1->0 83 43 51.81

Ports 5 4 80.00
Port Bits 166 86 51.81
Port Bits 0->1 83 43 51.81
Port Bits 1->0 83 43 51.81

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[39:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[39:0] No No No INPUT
state_o[39:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 166 86 51.81
Total Bits 0->1 83 43 51.81
Total Bits 1->0 83 43 51.81

Ports 5 4 80.00
Port Bits 166 86 51.81
Port Bits 0->1 83 43 51.81
Port Bits 1->0 83 43 51.81

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[39:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[39:0] No No No INPUT
state_o[39:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 166 86 51.81
Total Bits 0->1 83 43 51.81
Total Bits 1->0 83 43 51.81

Ports 5 4 80.00
Port Bits 166 86 51.81
Port Bits 0->1 83 43 51.81
Port Bits 1->0 83 43 51.81

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[39:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[39:0] No No No INPUT
state_o[39:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT