SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_prim_reg_we_check |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_prim_reg_we_check |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 48 | 48 | 100.00 |
Total Bits 0->1 | 24 | 24 | 100.00 |
Total Bits 1->0 | 24 | 24 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 48 | 48 | 100.00 |
Port Bits 0->1 | 24 | 24 | 100.00 |
Port Bits 1->0 | 24 | 24 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
oh_i[3:0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | INPUT |
oh_i[17:4] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[22:18] | Yes | Yes | *T12,*T13,*T14 | Yes | T12,T13,T14 | INPUT |
oh_i[24:23] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[35:25] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | INPUT |
oh_i[55:36] | Unreachable | Unreachable | Unreachable | INPUT | ||
addr_i[5:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
err_o | Yes | Yes | T12,T13,T14 | Yes | T12,T13,T14 | OUTPUT |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 22 | 22 | 100.00 |
Total Bits 0->1 | 11 | 11 | 100.00 |
Total Bits 1->0 | 11 | 11 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 22 | 22 | 100.00 |
Port Bits 0->1 | 11 | 11 | 100.00 |
Port Bits 1->0 | 11 | 11 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
oh_i[6:0] | Yes | Yes | T3,*T5,T6 | Yes | T3,T5,T6 | INPUT |
oh_i[7] | Unreachable | Unreachable | Unreachable | INPUT | ||
addr_i[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T3,T5,T6 | Yes | T3,T5,T6 | INPUT |
err_o | Yes | Yes | T12,T13,T14 | Yes | T12,T13,T14 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 48 | 48 | 100.00 |
Total Bits 0->1 | 24 | 24 | 100.00 |
Total Bits 1->0 | 24 | 24 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 48 | 48 | 100.00 |
Port Bits 0->1 | 24 | 24 | 100.00 |
Port Bits 1->0 | 24 | 24 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
oh_i[3:0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | INPUT |
oh_i[17:4] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[22:18] | Yes | Yes | *T12,*T13,*T14 | Yes | T12,T13,T14 | INPUT |
oh_i[24:23] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[35:25] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | INPUT |
oh_i[55:36] | Unreachable | Unreachable | Unreachable | INPUT | ||
addr_i[5:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
err_o | Yes | Yes | T12,T13,T14 | Yes | T12,T13,T14 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 22 | 22 | 100.00 |
Total Bits 0->1 | 11 | 11 | 100.00 |
Total Bits 1->0 | 11 | 11 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 22 | 22 | 100.00 |
Port Bits 0->1 | 11 | 11 | 100.00 |
Port Bits 1->0 | 11 | 11 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
oh_i[6:0] | Yes | Yes | T3,*T5,T6 | Yes | T3,T5,T6 | INPUT |
oh_i[7] | Unreachable | Unreachable | Unreachable | INPUT | ||
addr_i[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T3,T5,T6 | Yes | T3,T5,T6 | INPUT |
err_o | Yes | Yes | T12,T13,T14 | Yes | T12,T13,T14 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |