Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_onehot_check ( parameter AddrWidth=6,OneHotWidth=56,AddrCheck=0,EnableCheck=1,StrictCheck=0,EnableAlertTriggerSVA=1,NumLevels=6,gen_tree[0].gen_level[0].Pa=0,gen_tree[1].gen_level[0].Pa=1,gen_tree[1].gen_level[1].Pa=2,gen_tree[2].gen_level[0].Pa=3,gen_tree[2].gen_level[1].Pa=4,gen_tree[2].gen_level[2].Pa=5,gen_tree[2].gen_level[3].Pa=6,gen_tree[3].gen_level[0].Pa=7,gen_tree[3].gen_level[1].Pa=8,gen_tree[3].gen_level[2].Pa=9,gen_tree[3].gen_level[3].Pa=10,gen_tree[3].gen_level[4].Pa=11,gen_tree[3].gen_level[5].Pa=12,gen_tree[3].gen_level[6].Pa=13,gen_tree[3].gen_level[7].Pa=14,gen_tree[4].gen_level[0].Pa=15,gen_tree[4].gen_level[1].Pa=16,gen_tree[4].gen_level[2].Pa=17,gen_tree[4].gen_level[3].Pa=18,gen_tree[4].gen_level[4].Pa=19,gen_tree[4].gen_level[5].Pa=20,gen_tree[4].gen_level[6].Pa=21,gen_tree[4].gen_level[7].Pa=22,gen_tree[4].gen_level[8].Pa=23,gen_tree[4].gen_level[9].Pa=24,gen_tree[4].gen_level[10].Pa=25,gen_tree[4].gen_level[11].Pa=26,gen_tree[4].gen_level[12].Pa=27,gen_tree[4].gen_level[13].Pa=28,gen_tree[4].gen_level[14].Pa=29,gen_tree[4].gen_level[15].Pa=30,gen_tree[5].gen_level[0].Pa=31,gen_tree[5].gen_level[1].Pa=32,gen_tree[5].gen_level[2].Pa=33,gen_tree[5].gen_level[3].Pa=34,gen_tree[5].gen_level[4].Pa=35,gen_tree[5].gen_level[5].Pa=36,gen_tree[5].gen_level[6].Pa=37,gen_tree[5].gen_level[7].Pa=38,gen_tree[5].gen_level[8].Pa=39,gen_tree[5].gen_level[9].Pa=40,gen_tree[5].gen_level[10].Pa=41,gen_tree[5].gen_level[11].Pa=42,gen_tree[5].gen_level[12].Pa=43,gen_tree[5].gen_level[13].Pa=44,gen_tree[5].gen_level[14].Pa=45,gen_tree[5].gen_level[15].Pa=46,gen_tree[5].gen_level[16].Pa=47,gen_tree[5].gen_level[17].Pa=48,gen_tree[5].gen_level[18].Pa=49,gen_tree[5].gen_level[19].Pa=50,gen_tree[5].gen_level[20].Pa=51,gen_tree[5].gen_level[21].Pa=52,gen_tree[5].gen_level[22].Pa=53,gen_tree[5].gen_level[23].Pa=54,gen_tree[5].gen_level[24].Pa=55,gen_tree[5].gen_level[25].Pa=56,gen_tree[5].gen_level[26].Pa=57,gen_tree[5].gen_level[27].Pa=58,gen_tree[5].gen_level[28].Pa=59,gen_tree[5].gen_level[29].Pa=60,gen_tree[5].gen_level[30].Pa=61,gen_tree[5].gen_level[31].Pa=62,gen_tree[6].gen_level[0].Pa=63,gen_tree[6].gen_level[1].Pa=64,gen_tree[6].gen_level[2].Pa=65,gen_tree[6].gen_level[3].Pa=66,gen_tree[6].gen_level[4].Pa=67,gen_tree[6].gen_level[5].Pa=68,gen_tree[6].gen_level[6].Pa=69,gen_tree[6].gen_level[7].Pa=70,gen_tree[6].gen_level[8].Pa=71,gen_tree[6].gen_level[9].Pa=72,gen_tree[6].gen_level[10].Pa=73,gen_tree[6].gen_level[11].Pa=74,gen_tree[6].gen_level[12].Pa=75,gen_tree[6].gen_level[13].Pa=76,gen_tree[6].gen_level[14].Pa=77,gen_tree[6].gen_level[15].Pa=78,gen_tree[6].gen_level[16].Pa=79,gen_tree[6].gen_level[17].Pa=80,gen_tree[6].gen_level[18].Pa=81,gen_tree[6].gen_level[19].Pa=82,gen_tree[6].gen_level[20].Pa=83,gen_tree[6].gen_level[21].Pa=84,gen_tree[6].gen_level[22].Pa=85,gen_tree[6].gen_level[23].Pa=86,gen_tree[6].gen_level[24].Pa=87,gen_tree[6].gen_level[25].Pa=88,gen_tree[6].gen_level[26].Pa=89,gen_tree[6].gen_level[27].Pa=90,gen_tree[6].gen_level[28].Pa=91,gen_tree[6].gen_level[29].Pa=92,gen_tree[6].gen_level[30].Pa=93,gen_tree[6].gen_level[31].Pa=94,gen_tree[6].gen_level[32].Pa=95,gen_tree[6].gen_level[33].Pa=96,gen_tree[6].gen_level[34].Pa=97,gen_tree[6].gen_level[35].Pa=98,gen_tree[6].gen_level[36].Pa=99,gen_tree[6].gen_level[37].Pa=100,gen_tree[6].gen_level[38].Pa=101,gen_tree[6].gen_level[39].Pa=102,gen_tree[6].gen_level[40].Pa=103,gen_tree[6].gen_level[41].Pa=104,gen_tree[6].gen_level[42].Pa=105,gen_tree[6].gen_level[43].Pa=106,gen_tree[6].gen_level[44].Pa=107,gen_tree[6].gen_level[45].Pa=108,gen_tree[6].gen_level[46].Pa=109,gen_tree[6].gen_level[47].Pa=110,gen_tree[6].gen_level[48].Pa=111,gen_tree[6].gen_level[49].Pa=112,gen_tree[6].gen_level[50].Pa=113,gen_tree[6].gen_level[51].Pa=114,gen_tree[6].gen_level[52].Pa=115,gen_tree[6].gen_level[53].Pa=116,gen_tree[6].gen_level[54].Pa=117,gen_tree[6].gen_level[55].Pa=118,gen_tree[6].gen_level[56].Pa=119,gen_tree[6].gen_level[57].Pa=120,gen_tree[6].gen_level[58].Pa=121,gen_tree[6].gen_level[59].Pa=122,gen_tree[6].gen_level[60].Pa=123,gen_tree[6].gen_level[61].Pa=124,gen_tree[6].gen_level[62].Pa=125,gen_tree[6].gen_level[63].Pa=126 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	48	48	100.00
Total Bits 0->1	24	24	100.00
Total Bits 1->0	24	24	100.00

Ports	5	5	100.00
Port Bits	48	48	100.00
Port Bits 0->1	24	24	100.00
Port Bits 1->0	24	24	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
oh_i[3:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[17:4]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[22:18]	Yes	Yes	*T12,*T13,*T14	Yes	T12,T13,T14	INPUT
oh_i[24:23]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[35:25]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[55:36]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_onehot_check ( parameter AddrWidth=3,OneHotWidth=8,AddrCheck=0,EnableCheck=1,StrictCheck=0,EnableAlertTriggerSVA=1,NumLevels=3,gen_tree[0].gen_level[0].Pa=0,gen_tree[1].gen_level[0].Pa=1,gen_tree[1].gen_level[1].Pa=2,gen_tree[2].gen_level[0].Pa=3,gen_tree[2].gen_level[1].Pa=4,gen_tree[2].gen_level[2].Pa=5,gen_tree[2].gen_level[3].Pa=6,gen_tree[3].gen_level[0].Pa=7,gen_tree[3].gen_level[1].Pa=8,gen_tree[3].gen_level[2].Pa=9,gen_tree[3].gen_level[3].Pa=10,gen_tree[3].gen_level[4].Pa=11,gen_tree[3].gen_level[5].Pa=12,gen_tree[3].gen_level[6].Pa=13,gen_tree[3].gen_level[7].Pa=14 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	5	5	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
oh_i[6:0]	Yes	Yes	T3,*T5,T6	Yes	T3,T5,T6	INPUT
oh_i[7]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
err_o	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	48	48	100.00
Total Bits 0->1	24	24	100.00
Total Bits 1->0	24	24	100.00

Ports	5	5	100.00
Port Bits	48	48	100.00
Port Bits 0->1	24	24	100.00
Port Bits 1->0	24	24	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
oh_i[3:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[17:4]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[22:18]	Yes	Yes	*T12,*T13,*T14	Yes	T12,T13,T14	INPUT
oh_i[24:23]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[35:25]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[55:36]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	5	5	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
oh_i[6:0]	Yes	Yes	T3,*T5,T6	Yes	T3,T5,T6	INPUT
oh_i[7]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
err_o	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT

*Tests covering at least one bit in the range