Unified Coverage Report :: Module :: otp_ctrl_prim_reg_top

Module : otp_ctrl_prim_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	97.98			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	91.84	99.74	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.45	97.27	100.00		100.00	100.00	100.00	gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00	100.00		100.00			100.00
u_csr0_field0	100.00	100.00	100.00			100.00
u_csr0_field1	100.00	100.00	100.00			100.00
u_csr0_field2	100.00	100.00	100.00			100.00
u_csr0_field3	100.00	100.00	100.00			100.00
u_csr0_field4	100.00	100.00	100.00			100.00
u_csr1_field0	100.00	100.00	100.00			100.00
u_csr1_field1	100.00	100.00	100.00			100.00
u_csr1_field2	100.00	100.00	100.00			100.00
u_csr1_field3	100.00	100.00	100.00			100.00
u_csr1_field4	100.00	100.00	100.00			100.00
u_csr2	100.00	100.00	100.00			100.00
u_csr3_field0	100.00	100.00	100.00			100.00
u_csr3_field1	100.00	100.00	100.00			100.00
u_csr3_field2	100.00	100.00	100.00			100.00
u_csr3_field3	87.50	62.50	100.00			100.00
u_csr3_field4	87.50	62.50	100.00			100.00
u_csr3_field5	87.50	62.50	100.00			100.00
u_csr3_field6	87.50	62.50	100.00			100.00
u_csr3_field7	87.50	62.50	100.00			100.00
u_csr3_field8	87.50	62.50	100.00			100.00
u_csr4_field0	100.00	100.00	100.00			100.00
u_csr4_field1	100.00	100.00	100.00			100.00
u_csr4_field2	100.00	100.00	100.00			100.00
u_csr4_field3	100.00	100.00	100.00			100.00
u_csr5_field0	100.00	100.00	100.00			100.00
u_csr5_field1	100.00	100.00	100.00			100.00
u_csr5_field2	87.50	62.50	100.00			100.00
u_csr5_field3	87.50	62.50	100.00			100.00
u_csr5_field4	87.50	62.50	100.00			100.00
u_csr5_field5	87.50	62.50	100.00			100.00
u_csr5_field6	100.00	100.00	100.00			100.00
u_csr6_field0	100.00	100.00	100.00			100.00
u_csr6_field1	100.00	100.00	100.00			100.00
u_csr6_field2	100.00	100.00	100.00			100.00
u_csr6_field3	100.00	100.00	100.00			100.00
u_csr7_field0	87.50	62.50	100.00			100.00
u_csr7_field1	87.50	62.50	100.00			100.00
u_csr7_field2	87.50	62.50	100.00			100.00
u_csr7_field3	87.50	62.50	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

Line Coverage for Module : otp_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
TOTAL		104	104	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	1268	9	9	100.00
CONT_ASSIGN	1279	1	1	100.00
ALWAYS	1283	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
ALWAYS	1355	9	9	100.00
ALWAYS	1368	41	41	100.00
CONT_ASSIGN	1444	0	0
CONT_ASSIGN	1452	1	1	100.00
CONT_ASSIGN	1453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1268	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1279	1	1
1283	1	1
1295	1	1
1297	1	1
1299	1	1
1301	1	1
1303	1	1
1305	1	1
1306	1	1
1308	1	1
1310	1	1
1312	1	1
1314	1	1
1316	1	1
1317	1	1
1319	1	1
1320	1	1
1322	1	1
1324	1	1
1326	1	1
1327	1	1
1329	1	1
1331	1	1
1333	1	1
1335	1	1
1336	1	1
1338	1	1
1340	1	1
1342	1	1
1343	1	1
1345	1	1
1347	1	1
1349	1	1
1351	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1359	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1368	1	1
1369	1	1
1371	1	1
1372	1	1
1373	1	1
1374	1	1
1375	1	1
1379	1	1
1380	1	1
1381	1	1
1382	1	1
1383	1	1
1387	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1403	1	1
1404	1	1
1405	1	1
1406	1	1
1410	1	1
1411	1	1
1412	1	1
1413	1	1
1414	1	1
1415	1	1
1416	1	1
1420	1	1
1421	1	1
1422	1	1
1423	1	1
1427	1	1
1428	1	1
1429	1	1
1430	1	1
1444		unreachable
1452	1	1
1453	1	1

---

Cond Coverage for Module : otp_ctrl_prim_reg_top

	Total	Covered	Percent
Conditions	99	97	97.98
Logical	99	97	97.98
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T264,T265,T266

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T12,T13,T14
0	1	0	Covered	T264,T265,T266
1	0	0	Covered	T12,T13,T14

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T264,T265,T266
0	1	0	Covered	T5,T7,T8
1	0	0	Not Covered

 LINE       1269
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T2,T3,T4

 LINE       1270
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1271
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1279
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       1279
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       1283
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T5,T7,T8

 LINE       1283
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
0	0	0	0	0	0	0	0	Covered	T3,T5,T6
0	0	0	0	0	0	0	1	Covered	T3,T5,T6
0	0	0	0	0	0	1	0	Covered	T3,T5,T6
0	0	0	0	0	1	0	0	Covered	T3,T5,T6
0	0	0	0	1	0	0	0	Covered	T3,T5,T6
0	0	0	1	0	0	0	0	Covered	T3,T5,T6
0	0	1	0	0	0	0	0	Covered	T3,T5,T6
0	1	0	0	0	0	0	0	Covered	T3,T5,T6
1	0	0	0	0	0	0	0	Covered	T1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1295
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1306
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1317
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1320
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1327
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1336
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1343
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T6,T101

---

Branch Coverage for Module : otp_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	1279	2	2	100.00
IF	68	3	3	100.00
CASE	1369	9	9	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1279	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1369	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T3,T5,T6
addr_hit[2]	Covered	T3,T5,T6
addr_hit[3]	Covered	T3,T5,T6
addr_hit[4]	Covered	T3,T5,T6
addr_hit[5]	Covered	T3,T5,T6
addr_hit[6]	Covered	T3,T5,T6
addr_hit[7]	Covered	T3,T5,T6
default	Covered	T101,T226,T268

---

Assert Coverage for Module : otp_ctrl_prim_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	93256249	40256	0	0
reAfterRv	93256249	40256	0	0
rePulse	93256249	25211	0	0
wePulse	93256249	15045	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	40256	0	0
T3	516281	68	0	0
T4	145887	0	0	0
T5	143472	112	0	0
T6	0	114	0	0
T7	0	251	0	0
T8	0	173	0	0
T9	0	222	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	40	0	0
T101	0	104	0	0
T107	0	72	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	66	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	40256	0	0
T3	516281	68	0	0
T4	145887	0	0	0
T5	143472	112	0	0
T6	0	114	0	0
T7	0	251	0	0
T8	0	173	0	0
T9	0	222	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	40	0	0
T101	0	104	0	0
T107	0	72	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	66	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	25211	0	0
T3	516281	34	0	0
T4	145887	0	0	0
T5	143472	49	0	0
T6	0	57	0	0
T7	0	121	0	0
T8	0	78	0	0
T9	0	86	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	39	0	0
T101	0	52	0	0
T107	0	36	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	33	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	15045	0	0
T3	516281	34	0	0
T4	145887	0	0	0
T5	143472	63	0	0
T6	0	57	0	0
T7	0	130	0	0
T8	0	95	0	0
T9	0	136	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	1	0	0
T101	0	52	0	0
T107	0	36	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	33	0	0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

	Line No.	Total	Covered	Percent
TOTAL		104	104	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	1268	9	9	100.00
CONT_ASSIGN	1279	1	1	100.00
ALWAYS	1283	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
ALWAYS	1355	9	9	100.00
ALWAYS	1368	41	41	100.00
CONT_ASSIGN	1444	0	0
CONT_ASSIGN	1452	1	1	100.00
CONT_ASSIGN	1453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1268	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1279	1	1
1283	1	1
1295	1	1
1297	1	1
1299	1	1
1301	1	1
1303	1	1
1305	1	1
1306	1	1
1308	1	1
1310	1	1
1312	1	1
1314	1	1
1316	1	1
1317	1	1
1319	1	1
1320	1	1
1322	1	1
1324	1	1
1326	1	1
1327	1	1
1329	1	1
1331	1	1
1333	1	1
1335	1	1
1336	1	1
1338	1	1
1340	1	1
1342	1	1
1343	1	1
1345	1	1
1347	1	1
1349	1	1
1351	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1359	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1368	1	1
1369	1	1
1371	1	1
1372	1	1
1373	1	1
1374	1	1
1375	1	1
1379	1	1
1380	1	1
1381	1	1
1382	1	1
1383	1	1
1387	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1403	1	1
1404	1	1
1405	1	1
1406	1	1
1410	1	1
1411	1	1
1412	1	1
1413	1	1
1414	1	1
1415	1	1
1416	1	1
1420	1	1
1421	1	1
1422	1	1
1423	1	1
1427	1	1
1428	1	1
1429	1	1
1430	1	1
1444		unreachable
1452	1	1
1453	1	1

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

	Total	Covered	Percent
Conditions	97	97	100.00
Logical	97	97	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T5,T6

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T264,T265,T266

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T12,T13,T14
0	1	0	Covered	T264,T265,T266
1	0	0	Covered	T12,T13,T14

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T264,T265,T266
0	1	0	Covered	T5,T7,T8
1	0	0	Excluded		VC_COV_UNR

 LINE       1269
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T2,T3,T4

 LINE       1270
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1271
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T6

 LINE       1279
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       1279
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       1283
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T5,T7,T8

 LINE       1283
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
0	0	0	0	0	0	0	0	Covered	T3,T5,T6
0	0	0	0	0	0	0	1	Covered	T3,T5,T6
0	0	0	0	0	0	1	0	Covered	T3,T5,T6
0	0	0	0	0	1	0	0	Covered	T3,T5,T6
0	0	0	0	1	0	0	0	Covered	T3,T5,T6
0	0	0	1	0	0	0	0	Covered	T3,T5,T6
0	0	1	0	0	0	0	0	Covered	T3,T5,T6
0	1	0	0	0	0	0	0	Covered	T3,T5,T6
1	0	0	0	0	0	0	0	Covered	T1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       1283
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1283
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1295
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1306
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1317
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1320
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1327
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1336
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T5,T6

 LINE       1343
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T6
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T3,T6,T101

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	1279	2	2	100.00
IF	68	3	3	100.00
CASE	1369	9	9	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1279	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1369	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T3,T5,T6
addr_hit[2]	Covered	T3,T5,T6
addr_hit[3]	Covered	T3,T5,T6
addr_hit[4]	Covered	T3,T5,T6
addr_hit[5]	Covered	T3,T5,T6
addr_hit[6]	Covered	T3,T5,T6
addr_hit[7]	Covered	T3,T5,T6
default	Covered	T101,T226,T268

---

Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	93256249	40256	0	0
reAfterRv	93256249	40256	0	0
rePulse	93256249	25211	0	0
wePulse	93256249	15045	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	40256	0	0
T3	516281	68	0	0
T4	145887	0	0	0
T5	143472	112	0	0
T6	0	114	0	0
T7	0	251	0	0
T8	0	173	0	0
T9	0	222	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	40	0	0
T101	0	104	0	0
T107	0	72	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	66	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	40256	0	0
T3	516281	68	0	0
T4	145887	0	0	0
T5	143472	112	0	0
T6	0	114	0	0
T7	0	251	0	0
T8	0	173	0	0
T9	0	222	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	40	0	0
T101	0	104	0	0
T107	0	72	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	66	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	25211	0	0
T3	516281	34	0	0
T4	145887	0	0	0
T5	143472	49	0	0
T6	0	57	0	0
T7	0	121	0	0
T8	0	78	0	0
T9	0	86	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	39	0	0
T101	0	52	0	0
T107	0	36	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	33	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	15045	0	0
T3	516281	34	0	0
T4	145887	0	0	0
T5	143472	63	0	0
T6	0	57	0	0
T7	0	130	0	0
T8	0	95	0	0
T9	0	136	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	1	0	0
T101	0	52	0	0
T107	0	36	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T268	0	33	0	0