Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	80.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]	57.14	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	85.71	1	100	1	64	64

Group Instance : unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.14	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	3	4	57.14

Variables for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	3	4	57.14	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	3	4	57.14

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	97263	1		T1	530	T8	124	T5	151
check_fail	1	1		T81	1	-	-	-	-
access_err	28223	1		T2	111	T4	2	T5	182
no_err	87147	1		T1	69	T2	122	T4	54

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	97116	1		T1	530	T3	1	T8	124
check_fail	1	1		T81	1	-	-	-	-
access_err	28404	1		T1	5	T2	105	T4	12
ecc_uncorr_err	255	1		T109	1	T179	1	T188	1
ecc_corr_err	805	1		T111	25	T35	20	T145	11
no_err	86074	1		T1	64	T2	128	T4	43

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	96841	1		T1	530	T8	124	T10	1
check_fail	3	1		T82	1	T83	1	T172	1
access_err	28041	1		T2	123	T4	2	T5	182
ecc_uncorr_err	547	1		T122	1	T177	1	T174	51
ecc_corr_err	805	1		T35	24	T145	10	T68	13
no_err	86356	1		T1	69	T2	110	T4	53

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	96825	1		T1	530	T7	1	T8	124
check_fail	3	1		T82	1	T83	1	T172	1
access_err	28541	1		T1	31	T2	102	T4	16
ecc_uncorr_err	547	1		T3	1	T10	1	T112	1
ecc_corr_err	701	1		T111	8	T42	144	T77	18
no_err	85880	1		T1	38	T2	126	T4	38

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	97100	1		T1	530	T7	1	T8	124
check_fail	1	1		T82	1	-	-	-	-
access_err	27797	1		T2	117	T4	2	T8	8
ecc_uncorr_err	283	1		T145	20	T215	20	T216	1
ecc_corr_err	748	1		T111	25	T35	35	T145	2
no_err	86494	1		T1	69	T2	108	T4	52