Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81
1	Covered	T81

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T4,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T4,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T115,T203,T204
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T81,T82,T83
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T4,T5
CheckFailError	317	Covered	T81
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T6,T13,T56
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T81
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T4,T5
NoError->CheckFailError	317	Covered	T81
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T4,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81
1	0	Covered	T81
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	89484476	88650021	0	0
DigestKnown_A	89484476	88650021	0	0
DigestOffsetMustBeRepresentable_A	1115	1115	0	0
EccErrorState_A	89484476	2813	0	0
ErrorKnown_A	89484476	88650021	0	0
FsmStateKnown_A	89484476	88650021	0	0
InitDoneKnown_A	89484476	88650021	0	0
InitReadLocksPartition_A	89484476	15367212	0	0
InitWriteLocksPartition_A	89484476	15367212	0	0
OffsetMustBeBlockAligned_A	1115	1115	0	0
OtpAddrKnown_A	89484476	88650021	0	0
OtpCmdKnown_A	89484476	88650021	0	0
OtpErrorState_A	89484476	0	0	0
OtpReqKnown_A	89484476	88650021	0	0
OtpSizeKnown_A	89484476	88650021	0	0
OtpWdataKnown_A	89484476	88650021	0	0
ReadLockPropagation_A	89484476	16291263	0	0
SizeMustBeBlockAligned_A	1115	1115	0	0
TlulGntKnown_A	89484476	88650021	0	0
TlulRdataKnown_A	89484476	88650021	0	0
TlulReadOnReadLock_A	89484476	5747	0	0
TlulRerrorKnown_A	89484476	88650021	0	0
TlulRvalidKnown_A	89484476	88650021	0	0
WriteLockPropagation_A	89484476	2953206	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	89484476	32118535	0	0
u_state_regs_A	89484476	88650021	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	2813	0	0
T28	192533	0	0	0
T41	53579	0	0	0
T56	324412	0	0	0
T81	13123	2813	0	0
T118	28966	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T177	11062	0	0	0
T178	16134	0	0	0
T179	12699	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15367212	0	0
T1	80319	65100	0	0
T2	426325	80809	0	0
T3	14362	4863	0	0
T4	43173	501	0	0
T5	302685	42841	0	0
T7	18058	5755	0	0
T8	38850	23802	0	0
T9	18148	12622	0	0
T10	12099	4572	0	0
T11	10219	3426	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15367212	0	0
T1	80319	65100	0	0
T2	426325	80809	0	0
T3	14362	4863	0	0
T4	43173	501	0	0
T5	302685	42841	0	0
T7	18058	5755	0	0
T8	38850	23802	0	0
T9	18148	12622	0	0
T10	12099	4572	0	0
T11	10219	3426	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	16291263	0	0
T1	80319	65850	0	0
T2	426325	125933	0	0
T3	14362	0	0	0
T4	43173	3702	0	0
T5	302685	94903	0	0
T6	0	69798	0	0
T7	18058	0	0	0
T8	38850	29809	0	0
T9	18148	0	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T13	0	78009	0	0
T29	0	10801	0	0
T35	0	18682	0	0
T121	0	74196	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	5747	0	0
T1	80319	12	0	0
T2	426325	28	0	0
T3	14362	0	0	0
T4	43173	6	0	0
T5	302685	12	0	0
T6	0	24	0	0
T7	18058	0	0	0
T8	38850	2	0	0
T9	18148	8	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T13	0	10	0	0
T29	0	3	0	0
T121	0	22	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	2953206	0	0
T4	43173	3654	0	0
T5	302685	0	0	0
T6	78468	0	0	0
T8	38850	0	0	0
T9	18148	0	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T15	22924	0	0	0
T16	0	388145	0	0
T29	0	4213	0	0
T35	0	4888	0	0
T41	0	2071	0	0
T68	0	2725	0	0
T100	0	20101	0	0
T101	0	2468	0	0
T106	0	19411	0	0
T111	0	4315	0	0
T121	80048	0	0	0
T122	13247	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	32118535	0	0
T4	43173	35005	0	0
T5	302685	0	0	0
T6	78468	0	0	0
T7	18058	3578	0	0
T8	38850	2499	0	0
T9	18148	0	0	0
T10	12099	3184	0	0
T11	10219	0	0	0
T16	0	204986	0	0
T29	0	35535	0	0
T35	0	91829	0	0
T109	0	3565	0	0
T111	0	23497	0	0
T121	80048	0	0	0
T122	13247	3793	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T84

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T111,T35,T145

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81
1	Covered	T81

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T115,T203,T204
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T109,T179,T188
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T4
ReadSt->ReadWaitSt	252	Covered	T2,T3,T7
ReadWaitSt->ErrorSt	276	Covered	T175,T205,T168
ReadWaitSt->IdleSt	270	Covered	T2,T3,T7
ResetSt->ErrorSt	315	Covered	T81,T82,T83
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T4
CheckFailError	317	Covered	T81
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T3,T10,T111
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T6,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T4
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T3,T10,T111
MacroEccCorrError->NoError	235	Covered	T35,T42,T77
NoError->AccessError	256	Covered	T1,T2,T4
NoError->CheckFailError	317	Covered	T81
NoError->FsmStateError	289	Covered	T2,T7,T8
NoError->MacroEccCorrError	221	Covered	T3,T10,T111

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T84
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T109,T179,T188
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T4,T5
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T111,T35,T145
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T175,T205,T168
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81
1	0	Covered	T81
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	89484476	88650021	0	0
DigestKnown_A	89484476	88650021	0	0
DigestOffsetMustBeRepresentable_A	1115	1115	0	0
EccErrorState_A	89484476	2813	0	0
ErrorKnown_A	89484476	88650021	0	0
FsmStateKnown_A	89484476	88650021	0	0
InitDoneKnown_A	89484476	88650021	0	0
InitReadLocksPartition_A	89484476	15541503	0	0
InitWriteLocksPartition_A	89484476	15541503	0	0
OffsetMustBeBlockAligned_A	1115	1115	0	0
OtpAddrKnown_A	89484476	88650021	0	0
OtpCmdKnown_A	89484476	88650021	0	0
OtpErrorState_A	89484476	59	0	0
OtpReqKnown_A	89484476	88650021	0	0
OtpSizeKnown_A	89484476	88650021	0	0
OtpWdataKnown_A	89484476	88650021	0	0
ReadLockPropagation_A	89484476	15835478	0	0
SizeMustBeBlockAligned_A	1115	1115	0	0
TlulGntKnown_A	89484476	88650021	0	0
TlulRdataKnown_A	89484476	88650021	0	0
TlulReadOnReadLock_A	89484476	6006	0	0
TlulRerrorKnown_A	89484476	88650021	0	0
TlulRvalidKnown_A	89484476	88650021	0	0
WriteLockPropagation_A	89484476	2371642	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	89484476	29404037	0	0
u_state_regs_A	89484476	88650021	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	2813	0	0
T28	192533	0	0	0
T41	53579	0	0	0
T56	324412	0	0	0
T81	13123	2813	0	0
T118	28966	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T177	11062	0	0	0
T178	16134	0	0	0
T179	12699	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15541503	0	0
T1	80319	65134	0	0
T2	426325	80996	0	0
T3	14362	4897	0	0
T4	43173	637	0	0
T5	302685	43028	0	0
T7	18058	5806	0	0
T8	38850	23836	0	0
T9	18148	12656	0	0
T10	12099	4623	0	0
T11	10219	3477	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15541503	0	0
T1	80319	65134	0	0
T2	426325	80996	0	0
T3	14362	4897	0	0
T4	43173	637	0	0
T5	302685	43028	0	0
T7	18058	5806	0	0
T8	38850	23836	0	0
T9	18148	12656	0	0
T10	12099	4623	0	0
T11	10219	3477	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	59	0	0
T12	121883	0	0	0
T13	87114	0	0	0
T16	340305	0	0	0
T35	113202	0	0	0
T61	16758	0	0	0
T109	10531	1	0	0
T110	16049	0	0	0
T111	105470	0	0	0
T112	10423	0	0	0
T115	20662	0	0	0
T175	0	1	0	0
T179	0	1	0	0
T188	0	1	0	0
T191	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15835478	0	0
T1	80319	65844	0	0
T2	426325	122697	0	0
T3	14362	0	0	0
T4	43173	3867	0	0
T5	302685	107698	0	0
T6	0	69792	0	0
T7	18058	0	0	0
T8	38850	24155	0	0
T9	18148	0	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T13	0	65300	0	0
T16	0	364803	0	0
T29	0	10851	0	0
T35	0	20558	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	6006	0	0
T1	80319	18	0	0
T2	426325	30	0	0
T3	14362	0	0	0
T4	43173	5	0	0
T5	302685	9	0	0
T6	0	11	0	0
T7	18058	0	0	0
T8	38850	5	0	0
T9	18148	16	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T13	0	11	0	0
T29	0	2	0	0
T121	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	2371642	0	0
T12	121883	0	0	0
T13	87114	0	0	0
T16	340305	7366	0	0
T29	64897	3660	0	0
T35	113202	0	0	0
T42	0	5087	0	0
T43	0	1370	0	0
T61	16758	0	0	0
T101	0	18998	0	0
T105	0	1534	0	0
T106	0	10016	0	0
T107	0	5554	0	0
T109	10531	0	0	0
T110	16049	0	0	0
T111	105470	0	0	0
T112	10423	0	0	0
T114	0	8298	0	0
T123	0	8273	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	29404037	0	0
T1	80319	2466	0	0
T2	426325	0	0	0
T3	14362	0	0	0
T4	43173	14580	0	0
T5	302685	0	0	0
T7	18058	0	0	0
T8	38850	2482	0	0
T9	18148	0	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T16	0	193358	0	0
T29	0	27443	0	0
T35	0	91642	0	0
T41	0	34147	0	0
T109	0	3560	0	0
T111	0	29806	0	0
T202	0	2676	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T84,T173

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T145,T68

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T82,T83,T172
1	Covered	T82,T83,T172

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T122,T29,T16

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T122,T29,T16

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T115,T206,T207
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T122,T109,T177
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T174,T208,T167
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T81,T82,T83
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T5
CheckFailError	317	Covered	T82,T83,T172
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T10,T35,T84
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T13,T202,T209
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T82,T83,T172
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T10,T84,T173
MacroEccCorrError->NoError	235	Covered	T35,T68,T79
NoError->AccessError	256	Covered	T2,T4,T5
NoError->CheckFailError	317	Covered	T82,T83,T172
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T10,T35,T84

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T122,T29,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T10,T84,T173
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T122,T177,T189
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T4,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T35,T145,T68
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T174,T208,T167
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T82,T83,T172
1	0	Covered	T82,T83,T172
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	89484476	88650021	0	0
DigestKnown_A	89484476	88650021	0	0
DigestOffsetMustBeRepresentable_A	1115	1115	0	0
EccErrorState_A	89484476	8691	0	0
ErrorKnown_A	89484476	88650021	0	0
FsmStateKnown_A	89484476	88650021	0	0
InitDoneKnown_A	89484476	88650021	0	0
InitReadLocksPartition_A	89484476	15714545	0	0
InitWriteLocksPartition_A	89484476	15714545	0	0
OffsetMustBeBlockAligned_A	1115	1115	0	0
OtpAddrKnown_A	89484476	88650021	0	0
OtpCmdKnown_A	89484476	88650021	0	0
OtpErrorState_A	89484476	55	0	0
OtpReqKnown_A	89484476	88650021	0	0
OtpSizeKnown_A	89484476	88650021	0	0
OtpWdataKnown_A	89484476	88650021	0	0
ReadLockPropagation_A	89484476	15440170	0	0
SizeMustBeBlockAligned_A	1115	1115	0	0
TlulGntKnown_A	89484476	88650021	0	0
TlulRdataKnown_A	89484476	88650021	0	0
TlulReadOnReadLock_A	89484476	6361	0	0
TlulRerrorKnown_A	89484476	88650021	0	0
TlulRvalidKnown_A	89484476	88650021	0	0
WriteLockPropagation_A	89484476	1482221	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	89484476	19161127	0	0
u_state_regs_A	89484476	88650021	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	8691	0	0
T69	92599	0	0	0
T82	8870	2442	0	0
T83	0	3727	0	0
T172	0	2522	0	0
T180	15591	0	0	0
T181	22543	0	0	0
T182	328646	0	0	0
T183	10870	0	0	0
T184	28372	0	0	0
T185	28312	0	0	0
T186	15130	0	0	0
T187	188152	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15714545	0	0
T1	80319	65168	0	0
T2	426325	81183	0	0
T3	14362	4931	0	0
T4	43173	773	0	0
T5	302685	43215	0	0
T7	18058	5857	0	0
T8	38850	23870	0	0
T9	18148	12690	0	0
T10	12099	4674	0	0
T11	10219	3528	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15714545	0	0
T1	80319	65168	0	0
T2	426325	81183	0	0
T3	14362	4931	0	0
T4	43173	773	0	0
T5	302685	43215	0	0
T7	18058	5857	0	0
T8	38850	23870	0	0
T9	18148	12690	0	0
T10	12099	4674	0	0
T11	10219	3528	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	55	0	0
T13	87114	0	0	0
T15	22924	0	0	0
T29	64897	0	0	0
T35	113202	0	0	0
T61	16758	0	0	0
T109	10531	0	0	0
T110	16049	0	0	0
T111	105470	0	0	0
T112	10423	0	0	0
T122	13247	1	0	0
T174	0	1	0	0
T177	0	1	0	0
T183	0	1	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	15440170	0	0
T1	80319	65835	0	0
T2	426325	121528	0	0
T3	14362	0	0	0
T4	43173	3263	0	0
T5	302685	131486	0	0
T7	18058	0	0	0
T8	38850	25249	0	0
T9	18148	0	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T13	0	78003	0	0
T16	0	366255	0	0
T29	0	9781	0	0
T35	0	25914	0	0
T41	0	1199	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1115	1115	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	6361	0	0
T1	80319	18	0	0
T2	426325	26	0	0
T3	14362	0	0	0
T4	43173	4	0	0
T5	302685	12	0	0
T6	0	21	0	0
T7	18058	0	0	0
T8	38850	6	0	0
T9	18148	7	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T13	0	21	0	0
T111	0	15	0	0
T121	0	17	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	1482221	0	0
T12	121883	0	0	0
T13	87114	0	0	0
T16	340305	9517	0	0
T29	64897	14135	0	0
T35	113202	0	0	0
T41	0	2178	0	0
T42	0	3634	0	0
T43	0	1370	0	0
T61	16758	0	0	0
T100	0	8670	0	0
T101	0	7165	0	0
T105	0	8649	0	0
T108	0	5326	0	0
T109	10531	0	0	0
T110	16049	0	0	0
T111	105470	0	0	0
T112	10423	0	0	0
T201	0	102726	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	19161127	0	0
T13	87114	0	0	0
T15	22924	0	0	0
T16	0	190136	0	0
T29	64897	43876	0	0
T35	113202	0	0	0
T41	0	38709	0	0
T42	0	75263	0	0
T61	16758	0	0	0
T100	0	74955	0	0
T101	0	121729	0	0
T105	0	56632	0	0
T109	10531	0	0	0
T110	16049	0	0	0
T111	105470	0	0	0
T112	10423	0	0	0
T122	13247	3771	0	0
T177	0	2722	0	0
T202	0	2659	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0