Unified Coverage Report :: Module :: tlul_lc_gate

Module : tlul_lc_gate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.86	98.04	88.89		85.71	91.67	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate	83.66	98.04	88.89		85.71	95.65	50.00

---

Module Instance : tb.dut.u_tlul_lc_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.66	98.04	88.89		85.71	95.65	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	99.21	92.86		85.71	96.77	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	50	98.04
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	27	96.43
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
192	1	1
193	1	1
194	0	1
195	1	1
196	1	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : tlul_lc_gate

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T2,T5,T16

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T2,T5,T12
1	Covered	T2,T5,T16

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T2,T5,T15

---

FSM Coverage for Module : tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	6	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T2,T5,T15
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T2,T5,T15
StFlush	184	Covered	T18,T20,T21
StOutstanding	174	Covered	T2,T5,T16

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T2,T5,T16
StError->StErrorOutstanding	203	Covered	T2,T5,T15
StErrorOutstanding->StActive	211	Covered	T2,T5,T15
StFlush->StActive	196	Covered	T18,T20,T21
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T2,T5,T16
StOutstanding->StFlush	184	Covered	T18,T20,T21

---

Branch Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	12	85.71
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T2,T5,T16
StActive	0	-	-	-	-	-	-	Covered	T2,T5,T15
StActive	-	1	-	-	-	-	-	Covered	T2,T5,T16
StActive	-	0	-	-	-	-	-	Covered	T2,T5,T15
StOutstanding	-	-	1	-	-	-	-	Covered	T2,T5,T16
StOutstanding	-	-	0	-	-	-	-	Covered	T2,T5,T12
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Covered	T18,T20,T21
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T2,T5,T15
StError	-	-	-	-	-	0	-	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T2,T5,T15
StErrorOutstanding	-	-	-	-	-	-	0	Covered	T17,T18,T19
default	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	89484476	0	0	0
u_state_regs_A	89484476	88650021	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	50	98.04
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	27	96.43
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
192	1	1
193	1	1
194	0	1
195	1	1
196	1	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T2,T5,T16

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T2,T5,T12
1	Covered	T2,T5,T16

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T2,T5,T15

---

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	6	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T2,T5,T15
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T2,T5,T15
StFlush	184	Covered	T18,T20,T21
StOutstanding	174	Covered	T2,T5,T16

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T2,T5,T16
StError->StErrorOutstanding	203	Covered	T2,T5,T15
StErrorOutstanding->StActive	211	Covered	T2,T5,T15
StFlush->StActive	196	Covered	T18,T20,T21
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T2,T5,T16
StOutstanding->StFlush	184	Covered	T18,T20,T21

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	13	12	92.31
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
StActive	1	-	-	-	-	-	-	Covered	T2,T5,T16
StActive	0	-	-	-	-	-	-	Covered	T2,T5,T15
StActive	-	1	-	-	-	-	-	Covered	T2,T5,T16
StActive	-	0	-	-	-	-	-	Covered	T2,T5,T15
StOutstanding	-	-	1	-	-	-	-	Covered	T2,T5,T16
StOutstanding	-	-	0	-	-	-	-	Covered	T2,T5,T12
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Covered	T18,T20,T21
StFlush	-	-	-	0	0	-	-	Excluded		VC_COV_UNR
StError	-	-	-	-	-	1	-	Covered	T2,T5,T15
StError	-	-	-	-	-	0	-	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T2,T5,T15
StErrorOutstanding	-	-	-	-	-	-	0	Covered	T17,T18,T19
default	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	89484476	0	0	0
u_state_regs_A	89484476	88650021	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89484476	88650021	0	0
T1	80319	80045	0	0
T2	426325	426147	0	0
T3	14362	14091	0	0
T4	43173	42386	0	0
T5	302685	302575	0	0
T7	18058	17794	0	0
T8	38850	38605	0	0
T9	18148	17938	0	0
T10	12099	11842	0	0
T11	10219	9976	0	0