SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 12 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sram_0_req_during_flash_addr_req | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_flash_data_req | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_lc_esc | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 0 | |
sram_0_req_during_otbn_req | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_otp_idle | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_sram_1_req | 2 | 2 | 0 | 0.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
lc_esc_off | 0 | 1 | 1 | |
lc_esc_on | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 2 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] | -- | -- | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |