Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
32.44 21.33 30.22 13.29 0.00 21.73 99.69 40.81


Total tests in report: 175
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
30.22 30.22 20.73 20.73 24.35 24.35 35.56 35.56 0.00 0.00 20.77 20.77 93.47 93.47 16.65 16.65 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3773826904
33.18 2.96 20.91 0.18 28.35 4.00 35.94 0.39 0.00 0.00 21.11 0.33 94.40 0.93 31.52 14.87 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3855168400
34.16 0.98 20.91 0.00 28.50 0.15 35.94 0.00 0.00 0.00 21.11 0.00 97.20 2.80 35.45 3.93 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3378998334
34.60 0.44 20.95 0.03 28.89 0.40 35.98 0.04 0.00 0.00 21.30 0.19 97.36 0.16 37.74 2.29 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.4212806388
34.96 0.36 21.14 0.20 29.76 0.87 35.98 0.00 0.00 0.00 21.77 0.48 97.98 0.62 38.10 0.36 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1470075828
35.25 0.29 21.14 0.00 29.76 0.00 36.09 0.11 0.00 0.00 21.77 0.00 98.60 0.62 39.39 1.29 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2595596570
35.38 0.13 21.14 0.00 29.76 0.00 36.13 0.04 0.00 0.00 21.77 0.00 99.38 0.78 39.46 0.07 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1010599678
35.47 0.09 21.14 0.00 29.76 0.00 36.40 0.28 0.00 0.00 21.77 0.00 99.38 0.00 39.81 0.36 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3652087199
35.55 0.08 21.14 0.00 29.84 0.07 36.40 0.00 0.00 0.00 21.77 0.00 99.38 0.00 40.31 0.50 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.4253171255
35.61 0.06 21.21 0.07 29.89 0.05 36.40 0.00 0.00 0.00 21.77 0.00 99.69 0.31 40.31 0.00 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3411450635
35.65 0.04 21.21 0.00 29.91 0.02 36.40 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.60 0.29 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3945827624
35.69 0.03 21.27 0.07 30.09 0.17 36.40 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.60 0.00 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3712712671
35.71 0.02 21.27 0.00 30.09 0.00 36.40 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.74 0.14 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2660299754
35.73 0.02 21.27 0.00 30.11 0.02 36.42 0.02 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.07 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.938719435
35.74 0.01 21.29 0.02 30.16 0.05 36.42 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.00 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.491306010
35.74 0.01 21.30 0.02 30.19 0.02 36.42 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.00 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.663427125
35.75 0.01 21.34 0.03 30.19 0.00 36.42 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.00 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2663717071
35.75 0.01 21.34 0.00 30.21 0.02 36.42 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.00 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.366565999
35.75 0.01 21.34 0.00 30.24 0.02 36.42 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.00 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3259839723
35.76 0.01 21.35 0.02 30.24 0.00 36.42 0.00 0.00 0.00 21.77 0.00 99.69 0.00 40.81 0.00 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1851517349

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2577151354
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2316581965
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2279809068
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1969294422
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2857216072
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.369217801
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3110912384
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.128407078
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3063304185
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3645439731
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1576302385
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1969159920
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2466068605
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2705453919
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4017764251
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2179811299
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2883689363
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1831771013
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2119581953
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4241016932
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.940216901
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.570004830
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1127164555
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1193188433
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3208024159
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2657054800
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3057542350
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2565148875
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1807267787
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2614968241
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2111791653
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1844795487
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1418655654
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3243242725
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2974034102
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.580043961
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4235236470
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.311549582
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.954000366
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3422170938
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3647912792
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3361064589
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.567839205
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.296373036
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1335014877
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.53753301
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.868825914
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1834843744
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3202013552
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.759217065
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.560165687
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3220977996
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1787046670
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1328268275
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2439873
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3930480243
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4080104145
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.554584599
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3962120588
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2487203849
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2115392647
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3026766974
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.284073406
/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.159909920
/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3889588761
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3731557095
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1237497008
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.274028621
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3438671163
/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2235778553
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1890743459
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1719467531
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3132491480
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3774151777
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4204363445
/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2821208487
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1716745076
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2356252833
/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2156963891
/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.140356561
/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3440737484
/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.799615994
/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2157828316
/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1719170476
/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2421312216
/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1032462324
/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1704015907
/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1405914621
/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1843842277
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1070990351
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1663038881
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1004239702
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2576834144
/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3795366572
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.472111534
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3550283151
/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1712616412
/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1499212618
/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1739335892
/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.741534066
/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2968712660
/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.254172674
/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4013436697
/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2158579811
/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.566240766
/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3564097635
/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.511914101
/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4249235014
/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2714204092
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2785939865
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2286366244
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1290820269
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.4019332308
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2091872627
/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2926251747
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2113736290
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2401668401
/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.364068453
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2301105371
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2551035209
/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.381771708
/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3260352029
/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2223326192
/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2576662404
/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.245741858
/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.338776191
/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2473361947
/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3064241650
/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2613837118
/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3939553717
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.786299219
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1524987834
/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3332970271
/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1658024491
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3985429515
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3771077122
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1377057968
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2889953791
/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1379296318
/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1155570635
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1802439450
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.789547491
/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.396513506
/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.45052630
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2022881585
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1176025611
/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.462495318
/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1989811437
/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3708576111
/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.392945647
/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2670763691
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.119151275
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3824133673
/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2683780528
/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3745480770



Total test records in report: 175
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2657054800 Aug 14 04:36:14 PM PDT 24 Aug 14 04:36:19 PM PDT 24 146636491 ps
T2 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2466068605 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:01 PM PDT 24 541434322 ps
T3 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.511914101 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:30 PM PDT 24 590568851 ps
T4 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3773826904 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:15 PM PDT 24 10291375918 ps
T7 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2487203849 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:15 PM PDT 24 87770609 ps
T9 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1831771013 Aug 14 04:36:17 PM PDT 24 Aug 14 04:36:19 PM PDT 24 567688616 ps
T8 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3855168400 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:57 PM PDT 24 73867977 ps
T10 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1807267787 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:02 PM PDT 24 141369276 ps
T18 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3550283151 Aug 14 04:35:54 PM PDT 24 Aug 14 04:35:55 PM PDT 24 49333874 ps
T14 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2235778553 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:36 PM PDT 24 134481796 ps
T11 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1704015907 Aug 14 04:36:39 PM PDT 24 Aug 14 04:36:41 PM PDT 24 39682390 ps
T5 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.570004830 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:58 PM PDT 24 75330969 ps
T16 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1335014877 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:37 PM PDT 24 48260650 ps
T35 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3440737484 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:04 PM PDT 24 539586941 ps
T6 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2595596570 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:37 PM PDT 24 20312831066 ps
T19 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.663427125 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:12 PM PDT 24 1404980456 ps
T17 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3057542350 Aug 14 04:36:23 PM PDT 24 Aug 14 04:36:44 PM PDT 24 2501404982 ps
T28 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3378998334 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:05 PM PDT 24 89558901 ps
T12 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3939553717 Aug 14 04:36:13 PM PDT 24 Aug 14 04:36:14 PM PDT 24 37305903 ps
T25 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2115392647 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:12 PM PDT 24 2709078925 ps
T59 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2113736290 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:01 PM PDT 24 136484423 ps
T15 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3332970271 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:06 PM PDT 24 130881786 ps
T29 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1290820269 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:10 PM PDT 24 222451556 ps
T20 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.4019332308 Aug 14 04:36:19 PM PDT 24 Aug 14 04:36:21 PM PDT 24 70190441 ps
T21 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3930480243 Aug 14 04:35:58 PM PDT 24 Aug 14 04:36:01 PM PDT 24 275946736 ps
T26 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.140356561 Aug 14 04:35:54 PM PDT 24 Aug 14 04:36:14 PM PDT 24 3239988413 ps
T13 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.4212806388 Aug 14 04:36:29 PM PDT 24 Aug 14 04:36:31 PM PDT 24 585856125 ps
T73 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.4253171255 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:06 PM PDT 24 545412265 ps
T74 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3064241650 Aug 14 04:36:18 PM PDT 24 Aug 14 04:36:19 PM PDT 24 109370648 ps
T30 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2576834144 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:05 PM PDT 24 42900041 ps
T31 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.45052630 Aug 14 04:36:11 PM PDT 24 Aug 14 04:36:15 PM PDT 24 1931540046 ps
T75 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2974034102 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:02 PM PDT 24 143216706 ps
T27 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3652087199 Aug 14 04:36:27 PM PDT 24 Aug 14 04:36:43 PM PDT 24 10249786356 ps
T32 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3647912792 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:14 PM PDT 24 248500821 ps
T33 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3824133673 Aug 14 04:36:10 PM PDT 24 Aug 14 04:36:12 PM PDT 24 77184520 ps
T89 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3708576111 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:05 PM PDT 24 102856389 ps
T36 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.938719435 Aug 14 04:35:55 PM PDT 24 Aug 14 04:36:13 PM PDT 24 5254608633 ps
T90 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2421312216 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:08 PM PDT 24 78865070 ps
T34 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3132491480 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:52 PM PDT 24 156768098 ps
T57 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1155570635 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:09 PM PDT 24 110622651 ps
T67 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2683780528 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:06 PM PDT 24 78055586 ps
T68 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2473361947 Aug 14 04:36:44 PM PDT 24 Aug 14 04:36:46 PM PDT 24 559701182 ps
T69 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1969159920 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:53 PM PDT 24 48327772 ps
T37 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2091872627 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:13 PM PDT 24 526694359 ps
T47 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3945827624 Aug 14 04:35:58 PM PDT 24 Aug 14 04:36:17 PM PDT 24 2532584225 ps
T22 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.491306010 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:57 PM PDT 24 74689057 ps
T23 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1004239702 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:02 PM PDT 24 101250021 ps
T24 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1890743459 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:12 PM PDT 24 326333758 ps
T48 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3220977996 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:03 PM PDT 24 36753714 ps
T49 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3795366572 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:07 PM PDT 24 40138927 ps
T50 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.472111534 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:08 PM PDT 24 74566606 ps
T51 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.786299219 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:05 PM PDT 24 221547015 ps
T52 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.381771708 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:48 PM PDT 24 146675638 ps
T91 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.759217065 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:10 PM PDT 24 93725648 ps
T60 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3645439731 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:07 PM PDT 24 567159993 ps
T58 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3745480770 Aug 14 04:36:08 PM PDT 24 Aug 14 04:36:10 PM PDT 24 47523332 ps
T38 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1010599678 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:09 PM PDT 24 1077849875 ps
T77 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2179811299 Aug 14 04:35:57 PM PDT 24 Aug 14 04:36:04 PM PDT 24 1257672708 ps
T92 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.296373036 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:59 PM PDT 24 73505050 ps
T93 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2821208487 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:11 PM PDT 24 536218330 ps
T39 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.868825914 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:03 PM PDT 24 520997734 ps
T94 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3110912384 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:58 PM PDT 24 45607732 ps
T95 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.274028621 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:06 PM PDT 24 92456591 ps
T40 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.560165687 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:05 PM PDT 24 45639371 ps
T85 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.567839205 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:10 PM PDT 24 706220004 ps
T41 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1127164555 Aug 14 04:35:58 PM PDT 24 Aug 14 04:36:00 PM PDT 24 63604202 ps
T62 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1851517349 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:03 PM PDT 24 505318554 ps
T96 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2968712660 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:05 PM PDT 24 137142509 ps
T97 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.119151275 Aug 14 04:36:26 PM PDT 24 Aug 14 04:36:35 PM PDT 24 243060302 ps
T98 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1844795487 Aug 14 04:35:58 PM PDT 24 Aug 14 04:36:01 PM PDT 24 110831462 ps
T61 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.392945647 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:10 PM PDT 24 1168891601 ps
T99 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.254172674 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:04 PM PDT 24 78671420 ps
T100 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1989811437 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:11 PM PDT 24 70373787 ps
T63 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3063304185 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:05 PM PDT 24 235020042 ps
T101 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1658024491 Aug 14 04:35:57 PM PDT 24 Aug 14 04:36:00 PM PDT 24 1444047397 ps
T102 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2156963891 Aug 14 04:36:17 PM PDT 24 Aug 14 04:36:20 PM PDT 24 304280279 ps
T84 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.940216901 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:18 PM PDT 24 9715427393 ps
T70 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2286366244 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:08 PM PDT 24 228171956 ps
T42 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1719467531 Aug 14 04:35:50 PM PDT 24 Aug 14 04:35:59 PM PDT 24 2559537927 ps
T64 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3962120588 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:03 PM PDT 24 132402584 ps
T65 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4017764251 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:08 PM PDT 24 1756985962 ps
T103 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1379296318 Aug 14 04:36:08 PM PDT 24 Aug 14 04:36:09 PM PDT 24 56173346 ps
T104 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3564097635 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:08 PM PDT 24 606360481 ps
T105 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.954000366 Aug 14 04:36:40 PM PDT 24 Aug 14 04:36:41 PM PDT 24 87881252 ps
T78 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3985429515 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:19 PM PDT 24 103427248 ps
T106 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.364068453 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:04 PM PDT 24 701046791 ps
T107 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1719170476 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:18 PM PDT 24 601165662 ps
T108 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2157828316 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:07 PM PDT 24 152438454 ps
T43 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3411450635 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:59 PM PDT 24 1498046031 ps
T109 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2705453919 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:07 PM PDT 24 47979270 ps
T110 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.369217801 Aug 14 04:35:58 PM PDT 24 Aug 14 04:35:59 PM PDT 24 544860091 ps
T83 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3771077122 Aug 14 04:35:53 PM PDT 24 Aug 14 04:36:29 PM PDT 24 18941937295 ps
T111 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.799615994 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:07 PM PDT 24 52421222 ps
T112 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2614968241 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:07 PM PDT 24 71132444 ps
T113 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2926251747 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:59 PM PDT 24 136350825 ps
T114 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2577151354 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:13 PM PDT 24 267976090 ps
T115 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.566240766 Aug 14 04:36:11 PM PDT 24 Aug 14 04:36:13 PM PDT 24 78287204 ps
T116 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3202013552 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:14 PM PDT 24 2443426623 ps
T117 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.554584599 Aug 14 04:36:23 PM PDT 24 Aug 14 04:36:24 PM PDT 24 36416243 ps
T118 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2279809068 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:58 PM PDT 24 200893243 ps
T119 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1418655654 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:03 PM PDT 24 119859636 ps
T120 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2714204092 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:08 PM PDT 24 37244523 ps
T121 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3889588761 Aug 14 04:36:20 PM PDT 24 Aug 14 04:36:21 PM PDT 24 44777372 ps
T122 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4080104145 Aug 14 04:36:18 PM PDT 24 Aug 14 04:36:20 PM PDT 24 582132732 ps
T123 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3422170938 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:04 PM PDT 24 530922653 ps
T76 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.366565999 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:51 PM PDT 24 283171291 ps
T82 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3259839723 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:32 PM PDT 24 3710607738 ps
T79 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1328268275 Aug 14 04:36:21 PM PDT 24 Aug 14 04:36:27 PM PDT 24 102273672 ps
T124 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2889953791 Aug 14 04:36:22 PM PDT 24 Aug 14 04:36:24 PM PDT 24 78293265 ps
T125 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4013436697 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:14 PM PDT 24 137698013 ps
T88 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2551035209 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:27 PM PDT 24 20248510115 ps
T44 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1969294422 Aug 14 04:35:53 PM PDT 24 Aug 14 04:35:55 PM PDT 24 591771202 ps
T126 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1524987834 Aug 14 04:36:11 PM PDT 24 Aug 14 04:36:13 PM PDT 24 115003972 ps
T127 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1663038881 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:09 PM PDT 24 4017912465 ps
T128 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4249235014 Aug 14 04:36:37 PM PDT 24 Aug 14 04:36:38 PM PDT 24 60927220 ps
T129 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1032462324 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:44 PM PDT 24 145482354 ps
T53 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3438671163 Aug 14 04:36:26 PM PDT 24 Aug 14 04:36:27 PM PDT 24 52128935 ps
T80 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1499212618 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:09 PM PDT 24 331314274 ps
T130 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.741534066 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:06 PM PDT 24 532456197 ps
T131 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1576302385 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:01 PM PDT 24 42500340 ps
T132 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4235236470 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:10 PM PDT 24 1850275603 ps
T45 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2785939865 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:10 PM PDT 24 550185278 ps
T81 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3731557095 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:05 PM PDT 24 501037656 ps
T133 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.338776191 Aug 14 04:36:11 PM PDT 24 Aug 14 04:36:12 PM PDT 24 39019895 ps
T134 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1237497008 Aug 14 04:36:20 PM PDT 24 Aug 14 04:36:30 PM PDT 24 1007445748 ps
T135 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2857216072 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:56 PM PDT 24 68000198 ps
T46 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.789547491 Aug 14 04:36:19 PM PDT 24 Aug 14 04:36:21 PM PDT 24 72029443 ps
T136 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2613837118 Aug 14 04:36:10 PM PDT 24 Aug 14 04:36:12 PM PDT 24 575697698 ps
T137 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3208024159 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:05 PM PDT 24 1250572776 ps
T138 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1377057968 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:15 PM PDT 24 195879035 ps
T139 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2111791653 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:08 PM PDT 24 233192619 ps
T140 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2356252833 Aug 14 04:35:54 PM PDT 24 Aug 14 04:35:55 PM PDT 24 39008612 ps
T141 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.462495318 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:05 PM PDT 24 111428173 ps
T142 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1405914621 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:04 PM PDT 24 89720987 ps
T143 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.159909920 Aug 14 04:36:17 PM PDT 24 Aug 14 04:36:18 PM PDT 24 139175060 ps
T144 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.245741858 Aug 14 04:36:08 PM PDT 24 Aug 14 04:36:09 PM PDT 24 142646047 ps
T145 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3712712671 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:06 PM PDT 24 145995770 ps
T146 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2663717071 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:36 PM PDT 24 2804759159 ps
T147 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2883689363 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:11 PM PDT 24 1040592113 ps
T148 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2223326192 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:14 PM PDT 24 79463343 ps
T149 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1802439450 Aug 14 04:36:17 PM PDT 24 Aug 14 04:36:21 PM PDT 24 394294237 ps
T150 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2670763691 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:08 PM PDT 24 180028675 ps
T151 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1843842277 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:09 PM PDT 24 134081456 ps
T66 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1470075828 Aug 14 04:35:54 PM PDT 24 Aug 14 04:35:56 PM PDT 24 120271472 ps
T56 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.284073406 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:30 PM PDT 24 134798161 ps
T152 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1716745076 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:00 PM PDT 24 109723797 ps
T153 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3260352029 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:06 PM PDT 24 163072297 ps
T54 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4204363445 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:13 PM PDT 24 50684575 ps
T154 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.396513506 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:18 PM PDT 24 130922505 ps
T87 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2439873 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:22 PM PDT 24 1237056938 ps
T155 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1834843744 Aug 14 04:36:53 PM PDT 24 Aug 14 04:36:58 PM PDT 24 110196469 ps
T156 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3774151777 Aug 14 04:35:47 PM PDT 24 Aug 14 04:35:49 PM PDT 24 137365002 ps
T157 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3243242725 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:06 PM PDT 24 608864384 ps
T158 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.580043961 Aug 14 04:36:13 PM PDT 24 Aug 14 04:36:16 PM PDT 24 135175782 ps
T159 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3026766974 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:09 PM PDT 24 263375700 ps
T160 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.53753301 Aug 14 04:36:11 PM PDT 24 Aug 14 04:36:12 PM PDT 24 94764687 ps
T161 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1176025611 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:10 PM PDT 24 676123023 ps
T162 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2576662404 Aug 14 04:36:08 PM PDT 24 Aug 14 04:36:10 PM PDT 24 72313137 ps
T163 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2401668401 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:54 PM PDT 24 81522118 ps
T164 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1193188433 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:07 PM PDT 24 43041030 ps
T165 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2022881585 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:58 PM PDT 24 377446393 ps
T166 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1739335892 Aug 14 04:35:57 PM PDT 24 Aug 14 04:36:29 PM PDT 24 18943036489 ps
T167 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3361064589 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:59 PM PDT 24 101229805 ps
T71 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2565148875 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:05 PM PDT 24 293252287 ps
T168 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2301105371 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:55 PM PDT 24 1168700476 ps
T169 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.128407078 Aug 14 04:35:43 PM PDT 24 Aug 14 04:35:45 PM PDT 24 69309053 ps
T170 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2119581953 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:06 PM PDT 24 524619888 ps
T171 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4241016932 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:11 PM PDT 24 93114675 ps
T72 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2316581965 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:02 PM PDT 24 94759730 ps
T172 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1787046670 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:10 PM PDT 24 86649459 ps
T173 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.311549582 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:12 PM PDT 24 370130415 ps
T174 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2158579811 Aug 14 04:36:29 PM PDT 24 Aug 14 04:36:31 PM PDT 24 41214631 ps
T55 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1070990351 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:56 PM PDT 24 116182386 ps
T175 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1712616412 Aug 14 04:35:50 PM PDT 24 Aug 14 04:35:52 PM PDT 24 53715873 ps
T86 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2660299754 Aug 14 04:35:47 PM PDT 24 Aug 14 04:36:07 PM PDT 24 1372995463 ps

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3773826904
Short name T4
Test name
Test status
Simulation time 10291375918 ps
CPU time 13.6 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:15 PM PDT 24
Peak memory 238824 kb
Host smart-7e46714f-5385-4872-b230-a85f4515ed35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773826904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3773826904
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3855168400
Short name T8
Test name
Test status
Simulation time 73867977 ps
CPU time 4.61 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 245872 kb
Host smart-97f9ded6-76c9-44da-a3b0-1390882fc81c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855168400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3855168400
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3378998334
Short name T28
Test name
Test status
Simulation time 89558901 ps
CPU time 4.62 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 238484 kb
Host smart-37f6b5f7-512d-484e-be47-c9279518e500
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378998334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.3378998334
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.4212806388
Short name T13
Test name
Test status
Simulation time 585856125 ps
CPU time 1.89 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 229928 kb
Host smart-d3231be2-8a17-43a2-97d1-bfc0a44023f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212806388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.4212806388
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1470075828
Short name T66
Test name
Test status
Simulation time 120271472 ps
CPU time 2.49 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 238488 kb
Host smart-fda107dc-783b-4ee3-a355-3cce6f71d2f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470075828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.1470075828
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2595596570
Short name T6
Test name
Test status
Simulation time 20312831066 ps
CPU time 34.42 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 238716 kb
Host smart-0a1ff9af-211c-48fa-be93-f489533aff93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595596570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2595596570
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1010599678
Short name T38
Test name
Test status
Simulation time 1077849875 ps
CPU time 3.6 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 241556 kb
Host smart-14acf7bf-896b-4b0e-a525-1a1ed569eab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010599678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1010599678
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3652087199
Short name T27
Test name
Test status
Simulation time 10249786356 ps
CPU time 16.38 seconds
Started Aug 14 04:36:27 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 244108 kb
Host smart-667591dd-aa94-4e85-809d-cdf7d2f27f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652087199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3652087199
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.4253171255
Short name T73
Test name
Test status
Simulation time 545412265 ps
CPU time 1.6 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 229564 kb
Host smart-a2ddb863-942f-4a7d-ba6d-4882884543fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253171255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.4253171255
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3411450635
Short name T43
Test name
Test status
Simulation time 1498046031 ps
CPU time 2.19 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 238532 kb
Host smart-87ef6ab4-8c95-4b5f-a371-c51352e794a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411450635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3411450635
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3945827624
Short name T47
Test name
Test status
Simulation time 2532584225 ps
CPU time 18.23 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:36:17 PM PDT 24
Peak memory 244172 kb
Host smart-630bcb9b-879d-4c0c-929c-885dda77430b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945827624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.3945827624
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3712712671
Short name T145
Test name
Test status
Simulation time 145995770 ps
CPU time 5.9 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 245732 kb
Host smart-baac330f-1698-467b-aa2b-7e90eb658561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712712671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3712712671
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2660299754
Short name T86
Test name
Test status
Simulation time 1372995463 ps
CPU time 19.64 seconds
Started Aug 14 04:35:47 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 243668 kb
Host smart-8e27ae4b-ee62-4900-9b6e-dadb0831de9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660299754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2660299754
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.938719435
Short name T36
Test name
Test status
Simulation time 5254608633 ps
CPU time 16.7 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 244304 kb
Host smart-9f250674-2700-429e-ac39-77cb34c42d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938719435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_int
g_err.938719435
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.491306010
Short name T22
Test name
Test status
Simulation time 74689057 ps
CPU time 2.05 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 244412 kb
Host smart-6b36339f-b35f-4e8d-959d-5fa74f1641c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491306010 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.491306010
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.663427125
Short name T19
Test name
Test status
Simulation time 1404980456 ps
CPU time 5.74 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 246508 kb
Host smart-6c3877a3-eb37-4ced-b1ea-5ec20d575346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663427125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.663427125
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2663717071
Short name T146
Test name
Test status
Simulation time 2804759159 ps
CPU time 7.67 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 245752 kb
Host smart-066253d9-69bc-47bb-a1a4-375b4862baa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663717071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2663717071
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.366565999
Short name T76
Test name
Test status
Simulation time 283171291 ps
CPU time 1.84 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 240416 kb
Host smart-2c1bcea4-a7ac-4db1-9bbf-096819393423
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366565999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.366565999
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3259839723
Short name T82
Test name
Test status
Simulation time 3710607738 ps
CPU time 20.28 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:32 PM PDT 24
Peak memory 244528 kb
Host smart-047b0646-3572-4b91-b061-34b9b9b94d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259839723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3259839723
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1851517349
Short name T62
Test name
Test status
Simulation time 505318554 ps
CPU time 4.37 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:03 PM PDT 24
Peak memory 245912 kb
Host smart-c7b96ef2-2020-4570-83d2-89f79169276b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851517349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.1851517349
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2577151354
Short name T114
Test name
Test status
Simulation time 267976090 ps
CPU time 5.55 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 238572 kb
Host smart-edc44bed-b3fa-43b0-9629-cb450b4269f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577151354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2577151354
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2316581965
Short name T72
Test name
Test status
Simulation time 94759730 ps
CPU time 2.01 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 240256 kb
Host smart-1ce1a9a3-76ed-4cfa-bc23-b06c7d4d2ea6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316581965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2316581965
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2279809068
Short name T118
Test name
Test status
Simulation time 200893243 ps
CPU time 2.62 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 244508 kb
Host smart-04868826-8b62-4686-824f-17348f24ce00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279809068 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2279809068
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1969294422
Short name T44
Test name
Test status
Simulation time 591771202 ps
CPU time 2.44 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 240696 kb
Host smart-c36a83a1-0231-444d-868d-791ab3ab91ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969294422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1969294422
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2857216072
Short name T135
Test name
Test status
Simulation time 68000198 ps
CPU time 1.44 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 229504 kb
Host smart-5506352f-552d-4b92-b59a-a014adbccc5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857216072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2857216072
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.369217801
Short name T110
Test name
Test status
Simulation time 544860091 ps
CPU time 1.37 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 229184 kb
Host smart-130e48c1-ba1d-4906-883d-cf59d656664f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369217801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.369217801
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3110912384
Short name T94
Test name
Test status
Simulation time 45607732 ps
CPU time 1.3 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 230244 kb
Host smart-d0b27d68-7fd8-4c35-bb13-94b510ba20f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110912384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3110912384
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.128407078
Short name T169
Test name
Test status
Simulation time 69309053 ps
CPU time 2.26 seconds
Started Aug 14 04:35:43 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 238464 kb
Host smart-3ad08b0f-dbe0-41d9-81a1-29917f737ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128407078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct
rl_same_csr_outstanding.128407078
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3063304185
Short name T63
Test name
Test status
Simulation time 235020042 ps
CPU time 3.73 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 238504 kb
Host smart-429e9892-b124-43c6-b4d8-2bd725d54a50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063304185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.3063304185
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3645439731
Short name T60
Test name
Test status
Simulation time 567159993 ps
CPU time 8.08 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 238576 kb
Host smart-11c630ee-efdc-4678-8bdd-9999354ef2e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645439731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.3645439731
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1576302385
Short name T131
Test name
Test status
Simulation time 42500340 ps
CPU time 1.56 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 240568 kb
Host smart-732d61c2-5877-40f0-8789-ea0a1ef2e7e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576302385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1576302385
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1969159920
Short name T69
Test name
Test status
Simulation time 48327772 ps
CPU time 1.46 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 229844 kb
Host smart-0b9ba75f-0ef1-4cba-bdbe-38d2ee7fb4d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969159920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1969159920
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2466068605
Short name T2
Test name
Test status
Simulation time 541434322 ps
CPU time 2 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 229280 kb
Host smart-733cbeb2-a74b-4409-a355-6554f83fb302
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466068605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2466068605
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2705453919
Short name T109
Test name
Test status
Simulation time 47979270 ps
CPU time 1.36 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 229728 kb
Host smart-4b2f0eca-956f-49a2-bd70-1437dc30bcde
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705453919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2705453919
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4017764251
Short name T65
Test name
Test status
Simulation time 1756985962 ps
CPU time 4.7 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 238540 kb
Host smart-028af2eb-a857-4b24-9090-50177cda9ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017764251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.4017764251
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2179811299
Short name T77
Test name
Test status
Simulation time 1257672708 ps
CPU time 6.15 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 245968 kb
Host smart-2c86ed87-3d89-4201-b98a-6f327d16518a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179811299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2179811299
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2883689363
Short name T147
Test name
Test status
Simulation time 1040592113 ps
CPU time 3.2 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 243600 kb
Host smart-493751ef-76fe-4462-a6b0-49733bd1cf8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883689363 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2883689363
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1831771013
Short name T9
Test name
Test status
Simulation time 567688616 ps
CPU time 1.65 seconds
Started Aug 14 04:36:17 PM PDT 24
Finished Aug 14 04:36:19 PM PDT 24
Peak memory 238436 kb
Host smart-c2f8101d-e6e4-4348-a9ee-ce3a6d5c7940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831771013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1831771013
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2119581953
Short name T170
Test name
Test status
Simulation time 524619888 ps
CPU time 4.2 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 241764 kb
Host smart-8fec578b-e6ee-411c-a9ad-5a267e0a8a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119581953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2119581953
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4241016932
Short name T171
Test name
Test status
Simulation time 93114675 ps
CPU time 3.62 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 245240 kb
Host smart-d51431e8-502e-4821-91a0-86f991356911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241016932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.4241016932
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.940216901
Short name T84
Test name
Test status
Simulation time 9715427393 ps
CPU time 11.36 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:18 PM PDT 24
Peak memory 238676 kb
Host smart-aa0b3231-6dd2-4048-956e-b671375484e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940216901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in
tg_err.940216901
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.570004830
Short name T5
Test name
Test status
Simulation time 75330969 ps
CPU time 2.06 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 244112 kb
Host smart-91d28241-824d-4108-97e9-14662f381a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570004830 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.570004830
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1127164555
Short name T41
Test name
Test status
Simulation time 63604202 ps
CPU time 1.7 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 240992 kb
Host smart-6e1bdba3-6f88-4e87-b057-e55ec6f441c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127164555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1127164555
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1193188433
Short name T164
Test name
Test status
Simulation time 43041030 ps
CPU time 1.37 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 229796 kb
Host smart-dfc76446-1897-4229-9b5a-d175c8541d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193188433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1193188433
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3208024159
Short name T137
Test name
Test status
Simulation time 1250572776 ps
CPU time 2.76 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 238436 kb
Host smart-aa417a7a-9f51-4832-86ad-86aa288f4085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208024159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3208024159
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2657054800
Short name T1
Test name
Test status
Simulation time 146636491 ps
CPU time 5.43 seconds
Started Aug 14 04:36:14 PM PDT 24
Finished Aug 14 04:36:19 PM PDT 24
Peak memory 246656 kb
Host smart-ea5088b9-4d33-4dd5-ab08-2431f698d8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657054800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2657054800
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3057542350
Short name T17
Test name
Test status
Simulation time 2501404982 ps
CPU time 21.38 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:36:44 PM PDT 24
Peak memory 238788 kb
Host smart-4de3cc27-24a0-4514-bdbf-951cdf776629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057542350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3057542350
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2565148875
Short name T71
Test name
Test status
Simulation time 293252287 ps
CPU time 2.92 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 238532 kb
Host smart-e322e6ab-4f1a-4be3-a659-3a324458368e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565148875 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2565148875
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1807267787
Short name T10
Test name
Test status
Simulation time 141369276 ps
CPU time 1.55 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 238392 kb
Host smart-0d1f5317-d4ac-48d5-88a5-7a0eb7e02b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807267787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1807267787
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2614968241
Short name T112
Test name
Test status
Simulation time 71132444 ps
CPU time 1.39 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 230264 kb
Host smart-87feea66-ecee-49ed-9815-494114143ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614968241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2614968241
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2111791653
Short name T139
Test name
Test status
Simulation time 233192619 ps
CPU time 2.86 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 238460 kb
Host smart-be0439d6-dc29-4810-a17d-c7e7b16ff47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111791653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.2111791653
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1844795487
Short name T98
Test name
Test status
Simulation time 110831462 ps
CPU time 3.32 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 245616 kb
Host smart-461b5d19-53b8-43d1-a9a4-95784cd00229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844795487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1844795487
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1418655654
Short name T119
Test name
Test status
Simulation time 119859636 ps
CPU time 3.17 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:03 PM PDT 24
Peak memory 246728 kb
Host smart-53bc876f-3f03-4f27-a2d3-6dc590dbef0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418655654 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1418655654
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3243242725
Short name T157
Test name
Test status
Simulation time 608864384 ps
CPU time 2.29 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 240416 kb
Host smart-54c2b990-2c77-4b67-8bfc-1e791a609304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243242725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3243242725
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2974034102
Short name T75
Test name
Test status
Simulation time 143216706 ps
CPU time 1.31 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 230260 kb
Host smart-3ba9b65b-7f5c-4f3c-a520-6a4f33ac58e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974034102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2974034102
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.580043961
Short name T158
Test name
Test status
Simulation time 135175782 ps
CPU time 3.38 seconds
Started Aug 14 04:36:13 PM PDT 24
Finished Aug 14 04:36:16 PM PDT 24
Peak memory 238476 kb
Host smart-f93cc58c-eb8f-43ce-884f-c2914c8ce403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580043961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c
trl_same_csr_outstanding.580043961
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4235236470
Short name T132
Test name
Test status
Simulation time 1850275603 ps
CPU time 10.76 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238644 kb
Host smart-5d8416f0-c28d-45cc-b1e4-00624b3c2c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235236470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.4235236470
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.311549582
Short name T173
Test name
Test status
Simulation time 370130415 ps
CPU time 2.97 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 246828 kb
Host smart-a9e7709a-de18-4b6f-9f0c-0bd876f8a543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311549582 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.311549582
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.954000366
Short name T105
Test name
Test status
Simulation time 87881252 ps
CPU time 1.68 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:41 PM PDT 24
Peak memory 240644 kb
Host smart-c4eacff4-81d7-42cd-aa76-911d69bcadef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954000366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.954000366
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3422170938
Short name T123
Test name
Test status
Simulation time 530922653 ps
CPU time 1.99 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 229896 kb
Host smart-03e8a03d-f6b2-4ee3-84b5-1294906ba99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422170938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3422170938
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3647912792
Short name T32
Test name
Test status
Simulation time 248500821 ps
CPU time 2.28 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 238484 kb
Host smart-445842a6-0992-43da-8c83-b4c424f41c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647912792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.3647912792
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3361064589
Short name T167
Test name
Test status
Simulation time 101229805 ps
CPU time 3.42 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 246664 kb
Host smart-a8748667-b6bf-4487-a4bc-02b54823acb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361064589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3361064589
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.567839205
Short name T85
Test name
Test status
Simulation time 706220004 ps
CPU time 9.43 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238580 kb
Host smart-b42ac23b-22a7-457e-be50-a562d7bea40d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567839205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.567839205
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.296373036
Short name T92
Test name
Test status
Simulation time 73505050 ps
CPU time 2.52 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 246636 kb
Host smart-54a9998e-babe-40a2-8e2f-bc08598ebf1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296373036 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.296373036
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1335014877
Short name T16
Test name
Test status
Simulation time 48260650 ps
CPU time 1.9 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 240384 kb
Host smart-e6ce8879-3347-46a7-8204-48f6c8bb4077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335014877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1335014877
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.53753301
Short name T160
Test name
Test status
Simulation time 94764687 ps
CPU time 1.32 seconds
Started Aug 14 04:36:11 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 229464 kb
Host smart-0af8875f-2dff-484b-ad18-24ea0916ad58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53753301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.53753301
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.868825914
Short name T39
Test name
Test status
Simulation time 520997734 ps
CPU time 3.43 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:03 PM PDT 24
Peak memory 241716 kb
Host smart-aaad7125-dc38-4ccc-98e4-1a2841b66b60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868825914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.868825914
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1834843744
Short name T155
Test name
Test status
Simulation time 110196469 ps
CPU time 4.51 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:58 PM PDT 24
Peak memory 246596 kb
Host smart-050d5122-3e83-4384-95d1-4c3df893c69c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834843744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1834843744
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3202013552
Short name T116
Test name
Test status
Simulation time 2443426623 ps
CPU time 10.31 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 243780 kb
Host smart-3c90b058-ccf0-4f43-a100-e3340c1f988f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202013552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.3202013552
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.759217065
Short name T91
Test name
Test status
Simulation time 93725648 ps
CPU time 2.5 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 246504 kb
Host smart-bbc27190-9831-4f88-a532-37e46b45170e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759217065 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.759217065
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.560165687
Short name T40
Test name
Test status
Simulation time 45639371 ps
CPU time 1.8 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 240624 kb
Host smart-57325cde-ebaa-49df-bb45-71e6de5ed567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560165687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.560165687
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3220977996
Short name T48
Test name
Test status
Simulation time 36753714 ps
CPU time 1.38 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:03 PM PDT 24
Peak memory 229580 kb
Host smart-937ec3ef-c6c7-49ea-a25f-120340f1d8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220977996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3220977996
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1787046670
Short name T172
Test name
Test status
Simulation time 86649459 ps
CPU time 1.97 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238488 kb
Host smart-823b2a41-154f-4e30-8242-8bea4e8cf78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787046670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.1787046670
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1328268275
Short name T79
Test name
Test status
Simulation time 102273672 ps
CPU time 5.46 seconds
Started Aug 14 04:36:21 PM PDT 24
Finished Aug 14 04:36:27 PM PDT 24
Peak memory 245752 kb
Host smart-b75762c6-920b-4ead-91ca-f51db26f5914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328268275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1328268275
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2439873
Short name T87
Test name
Test status
Simulation time 1237056938 ps
CPU time 19.21 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:22 PM PDT 24
Peak memory 238592 kb
Host smart-34f2ae67-651f-438c-b93c-19387b30c723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg
_err.2439873
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3930480243
Short name T21
Test name
Test status
Simulation time 275946736 ps
CPU time 2.6 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 246112 kb
Host smart-2a60f719-d20b-471c-96db-0d5464b0939f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930480243 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3930480243
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4080104145
Short name T122
Test name
Test status
Simulation time 582132732 ps
CPU time 1.69 seconds
Started Aug 14 04:36:18 PM PDT 24
Finished Aug 14 04:36:20 PM PDT 24
Peak memory 238504 kb
Host smart-2b0eece0-b6be-46e4-a6b9-e36789350fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080104145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.4080104145
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.554584599
Short name T117
Test name
Test status
Simulation time 36416243 ps
CPU time 1.37 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:36:24 PM PDT 24
Peak memory 230272 kb
Host smart-6c8b3011-c1f0-480e-94ae-0599ca8cc9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554584599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.554584599
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3962120588
Short name T64
Test name
Test status
Simulation time 132402584 ps
CPU time 3.17 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:03 PM PDT 24
Peak memory 238436 kb
Host smart-568427bc-bb9c-4f3d-a744-2b979c20b22c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962120588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.3962120588
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2487203849
Short name T7
Test name
Test status
Simulation time 87770609 ps
CPU time 3.1 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:15 PM PDT 24
Peak memory 245600 kb
Host smart-4875d1ed-a4a2-4d7a-9841-8c2c193cc1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487203849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.2487203849
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2115392647
Short name T25
Test name
Test status
Simulation time 2709078925 ps
CPU time 8.88 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 243724 kb
Host smart-15cb9e92-458c-435d-9274-a2aa6db6b6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115392647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2115392647
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3026766974
Short name T159
Test name
Test status
Simulation time 263375700 ps
CPU time 2.4 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 244008 kb
Host smart-cb8fdfb6-cb94-4ca5-8128-3e0b82ecee69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026766974 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3026766974
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.284073406
Short name T56
Test name
Test status
Simulation time 134798161 ps
CPU time 1.49 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 238644 kb
Host smart-9ae807cb-582e-4a07-8e79-23bd4c7f5eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284073406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.284073406
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.159909920
Short name T143
Test name
Test status
Simulation time 139175060 ps
CPU time 1.43 seconds
Started Aug 14 04:36:17 PM PDT 24
Finished Aug 14 04:36:18 PM PDT 24
Peak memory 229556 kb
Host smart-a15e64f6-f8b5-4343-b488-b56066bf53bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159909920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.159909920
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3889588761
Short name T121
Test name
Test status
Simulation time 44777372 ps
CPU time 1.85 seconds
Started Aug 14 04:36:20 PM PDT 24
Finished Aug 14 04:36:21 PM PDT 24
Peak memory 241508 kb
Host smart-4d43afc9-2fdd-46e7-9f4d-641e494b07da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889588761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3889588761
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3731557095
Short name T81
Test name
Test status
Simulation time 501037656 ps
CPU time 5.72 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 246656 kb
Host smart-24009d3c-f5cd-4f67-898b-38d9b4072986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731557095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3731557095
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1237497008
Short name T134
Test name
Test status
Simulation time 1007445748 ps
CPU time 9.96 seconds
Started Aug 14 04:36:20 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 243460 kb
Host smart-61150118-3d7a-4c30-9a35-6410208633a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237497008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1237497008
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.274028621
Short name T95
Test name
Test status
Simulation time 92456591 ps
CPU time 2.1 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 244596 kb
Host smart-69ad4a63-b627-4d34-bdf7-3cea066d6b85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274028621 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.274028621
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3438671163
Short name T53
Test name
Test status
Simulation time 52128935 ps
CPU time 1.76 seconds
Started Aug 14 04:36:26 PM PDT 24
Finished Aug 14 04:36:27 PM PDT 24
Peak memory 240756 kb
Host smart-9ffe5c6b-0188-406b-950b-a1d2b767a684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438671163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3438671163
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2235778553
Short name T14
Test name
Test status
Simulation time 134481796 ps
CPU time 1.35 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 230332 kb
Host smart-154acf40-1f09-4de8-819f-918eeb0bf7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235778553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2235778553
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1890743459
Short name T24
Test name
Test status
Simulation time 326333758 ps
CPU time 5.44 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 246496 kb
Host smart-d2f6b919-0bf0-4528-87a8-7d54c672117d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890743459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1890743459
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1719467531
Short name T42
Test name
Test status
Simulation time 2559537927 ps
CPU time 8.27 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 238636 kb
Host smart-06335382-5aff-4b63-8b20-9ce51ac5a563
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719467531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.1719467531
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3132491480
Short name T34
Test name
Test status
Simulation time 156768098 ps
CPU time 3.57 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 238504 kb
Host smart-c6d0c93e-9e5d-45b6-a403-62bd82c4d3f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132491480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3132491480
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3774151777
Short name T156
Test name
Test status
Simulation time 137365002 ps
CPU time 2.47 seconds
Started Aug 14 04:35:47 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 247012 kb
Host smart-8ea78ed3-1a5d-4fd0-93c2-245b9b9b71b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774151777 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3774151777
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4204363445
Short name T54
Test name
Test status
Simulation time 50684575 ps
CPU time 1.49 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 240080 kb
Host smart-869d1a2f-cfe9-436d-a32b-315fdaaa6f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204363445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.4204363445
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2821208487
Short name T93
Test name
Test status
Simulation time 536218330 ps
CPU time 1.67 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 229820 kb
Host smart-7b0cb407-1324-4555-aef7-40801cf2729d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821208487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2821208487
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1716745076
Short name T152
Test name
Test status
Simulation time 109723797 ps
CPU time 1.41 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 230132 kb
Host smart-d5741214-4b13-4704-908e-200a0e5eeaca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716745076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1716745076
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2356252833
Short name T140
Test name
Test status
Simulation time 39008612 ps
CPU time 1.37 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 229668 kb
Host smart-063d0adb-e099-419f-a5dc-7ff4f74d5a98
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356252833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.2356252833
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2156963891
Short name T102
Test name
Test status
Simulation time 304280279 ps
CPU time 2.97 seconds
Started Aug 14 04:36:17 PM PDT 24
Finished Aug 14 04:36:20 PM PDT 24
Peak memory 238424 kb
Host smart-af2aa928-48a8-47e4-95c1-3e5cef8b38d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156963891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.2156963891
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.140356561
Short name T26
Test name
Test status
Simulation time 3239988413 ps
CPU time 20.14 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 245508 kb
Host smart-8dfb844c-a331-470f-9db4-dfdf21a0cbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140356561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int
g_err.140356561
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3440737484
Short name T35
Test name
Test status
Simulation time 539586941 ps
CPU time 1.7 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 229776 kb
Host smart-690db526-c4b4-4bcf-aa57-673b6fc8c5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440737484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3440737484
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.799615994
Short name T111
Test name
Test status
Simulation time 52421222 ps
CPU time 1.44 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 229556 kb
Host smart-bfa81595-5e5d-4e6e-8e05-40a9e34a521a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799615994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.799615994
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2157828316
Short name T108
Test name
Test status
Simulation time 152438454 ps
CPU time 1.52 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 229812 kb
Host smart-2ed674d8-4e6a-4592-8420-165905701fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157828316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2157828316
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1719170476
Short name T107
Test name
Test status
Simulation time 601165662 ps
CPU time 1.81 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:18 PM PDT 24
Peak memory 229856 kb
Host smart-464b2e9b-7a0d-4359-b439-cf4f4dfdbe0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719170476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1719170476
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2421312216
Short name T90
Test name
Test status
Simulation time 78865070 ps
CPU time 1.36 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 229560 kb
Host smart-bcf76dd2-65dc-4369-be85-07d379286565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421312216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2421312216
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1032462324
Short name T129
Test name
Test status
Simulation time 145482354 ps
CPU time 1.48 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:44 PM PDT 24
Peak memory 229568 kb
Host smart-3c6cbcc9-fc43-41ea-bc7e-cb5b169608e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032462324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1032462324
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1704015907
Short name T11
Test name
Test status
Simulation time 39682390 ps
CPU time 1.43 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:41 PM PDT 24
Peak memory 229496 kb
Host smart-9a85592c-2711-492d-9478-c4b203473c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704015907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1704015907
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1405914621
Short name T142
Test name
Test status
Simulation time 89720987 ps
CPU time 1.41 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 230272 kb
Host smart-7f1ac1b7-f371-4af9-8dc8-4c578b3f0cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405914621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1405914621
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1843842277
Short name T151
Test name
Test status
Simulation time 134081456 ps
CPU time 1.39 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 230320 kb
Host smart-708d7272-6ea3-468d-84f1-ee60cca3253e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843842277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1843842277
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1070990351
Short name T55
Test name
Test status
Simulation time 116182386 ps
CPU time 3.78 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 238448 kb
Host smart-b2551804-15d1-4759-8ac2-77bf56f01685
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070990351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.1070990351
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1663038881
Short name T127
Test name
Test status
Simulation time 4017912465 ps
CPU time 6.55 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 238708 kb
Host smart-dc75c17e-26ba-4146-967e-f0f85c840727
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663038881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.1663038881
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1004239702
Short name T23
Test name
Test status
Simulation time 101250021 ps
CPU time 2.58 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 246112 kb
Host smart-7096021b-c11d-4999-b1d4-e9f92c63b4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004239702 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1004239702
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2576834144
Short name T30
Test name
Test status
Simulation time 42900041 ps
CPU time 1.49 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 240072 kb
Host smart-456d0946-d144-4dc3-b3bf-bfa02ed9178e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576834144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2576834144
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3795366572
Short name T49
Test name
Test status
Simulation time 40138927 ps
CPU time 1.35 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 229872 kb
Host smart-81bd7a43-d9fb-4c2c-bff5-02c80eefb6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795366572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3795366572
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.472111534
Short name T50
Test name
Test status
Simulation time 74566606 ps
CPU time 1.34 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 229224 kb
Host smart-bae14c62-63c2-4919-9d2a-e56c41b053b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472111534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.472111534
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3550283151
Short name T18
Test name
Test status
Simulation time 49333874 ps
CPU time 1.37 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 229400 kb
Host smart-6b26c99f-bd26-496b-bc26-fad486bcec74
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550283151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3550283151
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1712616412
Short name T175
Test name
Test status
Simulation time 53715873 ps
CPU time 1.99 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 238508 kb
Host smart-336cb312-b5d2-44fc-b1dd-9c6914d93d3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712616412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1712616412
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1499212618
Short name T80
Test name
Test status
Simulation time 331314274 ps
CPU time 7.22 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 246196 kb
Host smart-bcd0e542-e6ab-45ed-88a6-ffff276edd8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499212618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1499212618
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1739335892
Short name T166
Test name
Test status
Simulation time 18943036489 ps
CPU time 31.61 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 238748 kb
Host smart-2f23d84a-bb25-4fbf-b78a-3cf0be287ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739335892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.1739335892
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.741534066
Short name T130
Test name
Test status
Simulation time 532456197 ps
CPU time 1.58 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 229832 kb
Host smart-052cbc6c-4ca7-43bd-a2be-8a183bd8c485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741534066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.741534066
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2968712660
Short name T96
Test name
Test status
Simulation time 137142509 ps
CPU time 1.45 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 230256 kb
Host smart-340c057c-59e0-4a3f-ab2a-af109701abf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968712660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2968712660
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.254172674
Short name T99
Test name
Test status
Simulation time 78671420 ps
CPU time 1.57 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 229940 kb
Host smart-80da36b6-a1c1-46ac-9420-76b856316e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254172674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.254172674
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4013436697
Short name T125
Test name
Test status
Simulation time 137698013 ps
CPU time 1.56 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 229868 kb
Host smart-b7fe3441-0f66-492a-abab-f569fc8127f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013436697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.4013436697
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2158579811
Short name T174
Test name
Test status
Simulation time 41214631 ps
CPU time 1.4 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 230212 kb
Host smart-8e6b7523-9c0d-4765-8200-b118f02e7756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158579811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2158579811
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.566240766
Short name T115
Test name
Test status
Simulation time 78287204 ps
CPU time 1.38 seconds
Started Aug 14 04:36:11 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 229816 kb
Host smart-f436f464-a7c0-47dd-8f22-2543ce17f68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566240766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.566240766
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3564097635
Short name T104
Test name
Test status
Simulation time 606360481 ps
CPU time 1.87 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 229508 kb
Host smart-45d4598d-0ca6-4eb1-b479-0cfb254a78b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564097635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3564097635
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.511914101
Short name T3
Test name
Test status
Simulation time 590568851 ps
CPU time 1.63 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 229472 kb
Host smart-ff2678c3-513f-4f23-a17d-15d9a23adbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511914101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.511914101
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4249235014
Short name T128
Test name
Test status
Simulation time 60927220 ps
CPU time 1.34 seconds
Started Aug 14 04:36:37 PM PDT 24
Finished Aug 14 04:36:38 PM PDT 24
Peak memory 229556 kb
Host smart-d3a04d0d-34d2-4214-bbc8-937eb914aeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249235014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.4249235014
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2714204092
Short name T120
Test name
Test status
Simulation time 37244523 ps
CPU time 1.32 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 229804 kb
Host smart-193e52c7-494b-4880-9afd-795f308596e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714204092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2714204092
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2785939865
Short name T45
Test name
Test status
Simulation time 550185278 ps
CPU time 6.67 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238460 kb
Host smart-9493f28f-25f0-4dc0-baaf-38fe3552f856
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785939865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.2785939865
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2286366244
Short name T70
Test name
Test status
Simulation time 228171956 ps
CPU time 5.25 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 238404 kb
Host smart-4d1dec9e-bc38-446b-b740-552633256f45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286366244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2286366244
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1290820269
Short name T29
Test name
Test status
Simulation time 222451556 ps
CPU time 2.19 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238524 kb
Host smart-ef290a39-0d7e-4dda-99c5-8a334d509c44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290820269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.1290820269
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.4019332308
Short name T20
Test name
Test status
Simulation time 70190441 ps
CPU time 2.19 seconds
Started Aug 14 04:36:19 PM PDT 24
Finished Aug 14 04:36:21 PM PDT 24
Peak memory 244132 kb
Host smart-f19bf847-d58a-46f4-a35d-1831106c6c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019332308 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.4019332308
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2091872627
Short name T37
Test name
Test status
Simulation time 526694359 ps
CPU time 1.88 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 238472 kb
Host smart-08a86558-d37f-4018-8f7b-bae54e301cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091872627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2091872627
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2926251747
Short name T113
Test name
Test status
Simulation time 136350825 ps
CPU time 1.43 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 230268 kb
Host smart-5a42d994-97d5-4162-a936-d76dd972c5d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926251747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2926251747
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2113736290
Short name T59
Test name
Test status
Simulation time 136484423 ps
CPU time 1.35 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 230116 kb
Host smart-330e8608-47e0-4d94-98e3-96d8450fcae5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113736290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.2113736290
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2401668401
Short name T163
Test name
Test status
Simulation time 81522118 ps
CPU time 1.4 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 229396 kb
Host smart-fed80201-b53c-4ffb-94e1-eb7f5bab99a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401668401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2401668401
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.364068453
Short name T106
Test name
Test status
Simulation time 701046791 ps
CPU time 2.51 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 238580 kb
Host smart-16040eae-c3bf-437d-8052-5ef0d78fd2cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364068453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_same_csr_outstanding.364068453
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2301105371
Short name T168
Test name
Test status
Simulation time 1168700476 ps
CPU time 5.95 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 245752 kb
Host smart-a7596571-45f2-48ae-97bc-9361345ed905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301105371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2301105371
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2551035209
Short name T88
Test name
Test status
Simulation time 20248510115 ps
CPU time 26.41 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:27 PM PDT 24
Peak memory 244420 kb
Host smart-0485b4bf-3969-4105-b186-e2525843565e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551035209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.2551035209
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.381771708
Short name T52
Test name
Test status
Simulation time 146675638 ps
CPU time 1.46 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 229596 kb
Host smart-fee126b5-6674-4ae1-a56a-e31c799c1f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381771708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.381771708
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3260352029
Short name T153
Test name
Test status
Simulation time 163072297 ps
CPU time 1.38 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 229520 kb
Host smart-2af94dbe-245c-45b4-94d7-71f4b2c237ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260352029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3260352029
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2223326192
Short name T148
Test name
Test status
Simulation time 79463343 ps
CPU time 1.35 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 229544 kb
Host smart-f810795b-6432-4e1f-87d5-30985d0d1563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223326192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2223326192
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2576662404
Short name T162
Test name
Test status
Simulation time 72313137 ps
CPU time 1.39 seconds
Started Aug 14 04:36:08 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 229520 kb
Host smart-7a96dc22-7750-4dda-aab4-0ed76f8f0899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576662404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2576662404
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.245741858
Short name T144
Test name
Test status
Simulation time 142646047 ps
CPU time 1.39 seconds
Started Aug 14 04:36:08 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 229588 kb
Host smart-55a68a18-bff2-4aa8-bae2-e9e86b38bba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245741858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.245741858
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.338776191
Short name T133
Test name
Test status
Simulation time 39019895 ps
CPU time 1.42 seconds
Started Aug 14 04:36:11 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 229616 kb
Host smart-778665eb-44f7-4230-bbf5-6ea3e5fbcbf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338776191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.338776191
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2473361947
Short name T68
Test name
Test status
Simulation time 559701182 ps
CPU time 1.57 seconds
Started Aug 14 04:36:44 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 229516 kb
Host smart-70ca4f37-f1a8-4f65-a2bf-be2b70f40b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473361947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2473361947
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3064241650
Short name T74
Test name
Test status
Simulation time 109370648 ps
CPU time 1.42 seconds
Started Aug 14 04:36:18 PM PDT 24
Finished Aug 14 04:36:19 PM PDT 24
Peak memory 230244 kb
Host smart-955da1bf-70c7-4702-bc20-c2011353ee45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064241650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3064241650
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2613837118
Short name T136
Test name
Test status
Simulation time 575697698 ps
CPU time 2.03 seconds
Started Aug 14 04:36:10 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 229520 kb
Host smart-e6c4abdb-e37f-4b58-b9dd-37210b1f9e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613837118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2613837118
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3939553717
Short name T12
Test name
Test status
Simulation time 37305903 ps
CPU time 1.37 seconds
Started Aug 14 04:36:13 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 229616 kb
Host smart-d947d07f-4e23-4407-aee0-7de3f29128eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939553717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3939553717
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.786299219
Short name T51
Test name
Test status
Simulation time 221547015 ps
CPU time 2.92 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 244924 kb
Host smart-7c1b6f40-f5c7-4ca6-aba4-804f2d700ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786299219 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.786299219
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1524987834
Short name T126
Test name
Test status
Simulation time 115003972 ps
CPU time 1.65 seconds
Started Aug 14 04:36:11 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 240368 kb
Host smart-4296cb7d-de88-4480-9820-f5c3fec44b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524987834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1524987834
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3332970271
Short name T15
Test name
Test status
Simulation time 130881786 ps
CPU time 1.38 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 230264 kb
Host smart-89e214e1-d754-45b0-a5c5-050f4a0fccfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332970271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3332970271
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1658024491
Short name T101
Test name
Test status
Simulation time 1444047397 ps
CPU time 3.24 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 238500 kb
Host smart-e623ada0-3371-4a5a-97c4-ba999cceb378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658024491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1658024491
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3985429515
Short name T78
Test name
Test status
Simulation time 103427248 ps
CPU time 2.97 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:19 PM PDT 24
Peak memory 245796 kb
Host smart-8ddfeeb0-891a-456f-9e33-77ea3f343539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985429515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3985429515
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3771077122
Short name T83
Test name
Test status
Simulation time 18941937295 ps
CPU time 36.2 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 244292 kb
Host smart-2b726a88-9db6-456d-bd5c-790c1c69ffe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771077122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3771077122
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1377057968
Short name T138
Test name
Test status
Simulation time 195879035 ps
CPU time 3.1 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:15 PM PDT 24
Peak memory 246804 kb
Host smart-b60b4ffe-6718-4918-b3d1-7100622480ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377057968 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1377057968
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2889953791
Short name T124
Test name
Test status
Simulation time 78293265 ps
CPU time 1.64 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:24 PM PDT 24
Peak memory 240132 kb
Host smart-10ca15e3-e6cd-4ff6-8d22-ca0c59b5adc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889953791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2889953791
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1379296318
Short name T103
Test name
Test status
Simulation time 56173346 ps
CPU time 1.39 seconds
Started Aug 14 04:36:08 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 229480 kb
Host smart-56a76173-7c54-4cd0-94ad-16718e4ec342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379296318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1379296318
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1155570635
Short name T57
Test name
Test status
Simulation time 110622651 ps
CPU time 3.13 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 238472 kb
Host smart-bb6924fc-b4ba-428f-a0cc-6dc5b396311a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155570635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1155570635
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1802439450
Short name T149
Test name
Test status
Simulation time 394294237 ps
CPU time 3.95 seconds
Started Aug 14 04:36:17 PM PDT 24
Finished Aug 14 04:36:21 PM PDT 24
Peak memory 246824 kb
Host smart-c52f15bc-d517-497f-98e3-cb81ef3948ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802439450 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1802439450
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.789547491
Short name T46
Test name
Test status
Simulation time 72029443 ps
CPU time 1.58 seconds
Started Aug 14 04:36:19 PM PDT 24
Finished Aug 14 04:36:21 PM PDT 24
Peak memory 238440 kb
Host smart-39756c62-2b8a-46f6-92c2-2911dd51e641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789547491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.789547491
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.396513506
Short name T154
Test name
Test status
Simulation time 130922505 ps
CPU time 1.46 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:18 PM PDT 24
Peak memory 230268 kb
Host smart-6973177f-04d9-420b-8da1-66b6329a1e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396513506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.396513506
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.45052630
Short name T31
Test name
Test status
Simulation time 1931540046 ps
CPU time 3.99 seconds
Started Aug 14 04:36:11 PM PDT 24
Finished Aug 14 04:36:15 PM PDT 24
Peak memory 238484 kb
Host smart-f37a5837-f6ab-4909-8ad5-008667521dc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45052630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctr
l_same_csr_outstanding.45052630
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2022881585
Short name T165
Test name
Test status
Simulation time 377446393 ps
CPU time 3.83 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 245512 kb
Host smart-9134df06-1352-495f-bb27-7c893d108f04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022881585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2022881585
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1176025611
Short name T161
Test name
Test status
Simulation time 676123023 ps
CPU time 9.44 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238580 kb
Host smart-20101e38-ba76-4f67-96aa-250e9810c74a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176025611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1176025611
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.462495318
Short name T141
Test name
Test status
Simulation time 111428173 ps
CPU time 3.08 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 246728 kb
Host smart-269a53fc-db2b-45c3-97d2-66ae4d0468bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462495318 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.462495318
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1989811437
Short name T100
Test name
Test status
Simulation time 70373787 ps
CPU time 1.57 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 240808 kb
Host smart-8379fc2b-deff-44d2-8ccf-dc078210c62e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989811437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1989811437
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3708576111
Short name T89
Test name
Test status
Simulation time 102856389 ps
CPU time 1.36 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 229512 kb
Host smart-dec3a824-a7c9-46ba-8978-991c72dd00cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708576111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3708576111
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.392945647
Short name T61
Test name
Test status
Simulation time 1168891601 ps
CPU time 2.65 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 241520 kb
Host smart-a1c6b9ea-576e-47fb-a276-65a2fd83ea80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392945647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.392945647
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2670763691
Short name T150
Test name
Test status
Simulation time 180028675 ps
CPU time 6.04 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 246540 kb
Host smart-2c555aac-2f5a-4814-8762-1f05804bfa45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670763691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2670763691
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.119151275
Short name T97
Test name
Test status
Simulation time 243060302 ps
CPU time 3.07 seconds
Started Aug 14 04:36:26 PM PDT 24
Finished Aug 14 04:36:35 PM PDT 24
Peak memory 246792 kb
Host smart-e7cb5d7b-2652-4584-9a95-bcf97acfec27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119151275 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.119151275
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3824133673
Short name T33
Test name
Test status
Simulation time 77184520 ps
CPU time 1.6 seconds
Started Aug 14 04:36:10 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 240708 kb
Host smart-87760061-20a4-40d3-8a49-979ff7ade382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824133673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3824133673
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2683780528
Short name T67
Test name
Test status
Simulation time 78055586 ps
CPU time 1.46 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 230280 kb
Host smart-81c38e26-552c-4d45-8408-5c0e7749d6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683780528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2683780528
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3745480770
Short name T58
Test name
Test status
Simulation time 47523332 ps
CPU time 2.05 seconds
Started Aug 14 04:36:08 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 238504 kb
Host smart-b7976572-4656-4978-a773-9c4bf7d5dd07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745480770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3745480770
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest
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