Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4706541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2579406

1

T1

15

T2

1117

T3

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6150494	1			T1	1		T2	2858		T3	233
values[0x0]	536206	1			T1	23		T2	177		T3	4
values[0x1]	599247	1			T1	27		T2	163		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3465038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3820909

1

T1

24

T2

1689

T3

131

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21926	1			T1	1		T2	10		T3	3
valid_sources[0x01]	31022	1			T2	16		T6	1		T9	40
valid_sources[0x02]	20981	1			T1	1		T2	14		T5	6
valid_sources[0x03]	32600	1			T2	11		T3	4		T5	25
valid_sources[0x04]	42259	1			T2	19		T5	18		T9	38
valid_sources[0x05]	24614	1			T2	11		T3	2		T5	108
valid_sources[0x06]	22525	1			T2	21		T5	23		T6	2
valid_sources[0x07]	27703	1			T2	12		T3	1		T5	65
valid_sources[0x08]	20748	1			T2	16		T3	3		T5	14
valid_sources[0x09]	23036	1			T2	14		T3	1		T5	27
valid_sources[0x0a]	24198	1			T2	8		T3	2		T5	146
valid_sources[0x0b]	22087	1			T2	12		T3	1		T5	78
valid_sources[0x0c]	21090	1			T2	11		T3	1		T5	115
valid_sources[0x0d]	35514	1			T1	1		T2	12		T3	2
valid_sources[0x0e]	20789	1			T2	12		T5	29		T6	1
valid_sources[0x0f]	25294	1			T2	13		T5	33		T6	5
valid_sources[0x10]	24649	1			T2	11		T3	5		T5	84
valid_sources[0x11]	24193	1			T2	12		T5	52		T6	4
valid_sources[0x12]	26635	1			T2	6		T5	75		T6	1
valid_sources[0x13]	25788	1			T2	10		T5	89		T9	25
valid_sources[0x14]	22572	1			T1	1		T2	11		T3	3
valid_sources[0x15]	34010	1			T2	13		T3	1		T5	14
valid_sources[0x16]	96965	1			T2	14		T3	2		T5	146
valid_sources[0x17]	22843	1			T2	17		T3	1		T5	23
valid_sources[0x18]	26911	1			T2	8		T3	6		T5	96
valid_sources[0x19]	21960	1			T2	21		T5	204		T6	1
valid_sources[0x1a]	34370	1			T2	9		T3	1		T5	44
valid_sources[0x1b]	22928	1			T2	7		T3	1		T5	24
valid_sources[0x1c]	22659	1			T2	18		T3	1		T5	38
valid_sources[0x1d]	31550	1			T2	10		T3	2		T5	24
valid_sources[0x1e]	21335	1			T2	18		T3	2		T5	111
valid_sources[0x1f]	21308	1			T2	12		T5	48		T9	28
valid_sources[0x20]	20333	1			T1	1		T2	10		T3	4
valid_sources[0x21]	20743	1			T2	10		T3	1		T5	1
valid_sources[0x22]	21191	1			T2	11		T3	2		T5	93
valid_sources[0x23]	25313	1			T2	11		T3	2		T5	67
valid_sources[0x24]	24735	1			T1	1		T2	10		T5	123
valid_sources[0x25]	20739	1			T2	11		T6	2		T9	50
valid_sources[0x26]	22220	1			T2	15		T3	1		T5	113
valid_sources[0x27]	20563	1			T1	1		T2	18		T3	1
valid_sources[0x28]	21214	1			T2	11		T5	24		T9	44
valid_sources[0x29]	23141	1			T2	19		T5	46		T6	3
valid_sources[0x2a]	20882	1			T2	8		T3	1		T9	18
valid_sources[0x2b]	20578	1			T2	8		T3	1		T5	18
valid_sources[0x2c]	22490	1			T2	11		T3	3		T5	11
valid_sources[0x2d]	20748	1			T2	9		T3	1		T5	9
valid_sources[0x2e]	27969	1			T2	10		T3	2		T5	42
valid_sources[0x2f]	20474	1			T2	9		T3	1		T5	32
valid_sources[0x30]	33631	1			T2	10		T9	47		T11	55
valid_sources[0x31]	22145	1			T2	18		T3	1		T5	10
valid_sources[0x32]	21057	1			T1	1		T2	8		T3	2
valid_sources[0x33]	33665	1			T2	13		T3	2		T5	51
valid_sources[0x34]	20623	1			T1	1		T2	12		T3	2
valid_sources[0x35]	23687	1			T2	17		T5	38		T9	13
valid_sources[0x36]	38026	1			T2	11		T5	60		T6	4
valid_sources[0x37]	31539	1			T1	1		T2	16		T3	2
valid_sources[0x38]	20942	1			T2	9		T5	94		T9	40
valid_sources[0x39]	25287	1			T2	17		T5	14		T6	2
valid_sources[0x3a]	38340	1			T1	1		T2	11		T5	26
valid_sources[0x3b]	21411	1			T2	19		T3	2		T5	29
valid_sources[0x3c]	25534	1			T1	1		T2	8		T3	1
valid_sources[0x3d]	31086	1			T2	14		T3	2		T5	53
valid_sources[0x3e]	33924	1			T2	15		T5	60		T6	1
valid_sources[0x3f]	20717	1			T2	16		T3	1		T5	85
valid_sources[0x40]	23525	1			T2	16		T3	1		T5	40
valid_sources[0x41]	29581	1			T2	16		T3	1		T5	83
valid_sources[0x42]	21366	1			T2	12		T5	212		T9	37
valid_sources[0x43]	26394	1			T2	16		T3	1		T5	169
valid_sources[0x44]	27390	1			T1	1		T2	17		T3	1
valid_sources[0x45]	20922	1			T2	8		T5	72		T9	54
valid_sources[0x46]	20458	1			T2	16		T3	1		T5	109
valid_sources[0x47]	22540	1			T1	1		T2	11		T3	3
valid_sources[0x48]	81630	1			T2	9		T5	4		T6	1
valid_sources[0x49]	39944	1			T2	12		T3	2		T5	75
valid_sources[0x4a]	25630	1			T1	2		T2	13		T3	3
valid_sources[0x4b]	22367	1			T1	1		T2	6		T3	3
valid_sources[0x4c]	21455	1			T2	10		T3	2		T9	21
valid_sources[0x4d]	24208	1			T2	15		T3	1		T5	16
valid_sources[0x4e]	38761	1			T1	1		T2	14		T3	2
valid_sources[0x4f]	21716	1			T1	1		T2	9		T5	34
valid_sources[0x50]	34243	1			T2	10		T3	1		T5	13
valid_sources[0x51]	22187	1			T1	1		T2	7		T5	52
valid_sources[0x52]	22089	1			T1	1		T2	13		T3	1
valid_sources[0x53]	21374	1			T2	9		T3	1		T5	58
valid_sources[0x54]	20781	1			T1	1		T2	12		T6	1
valid_sources[0x55]	27222	1			T2	23		T3	1		T5	114
valid_sources[0x56]	22644	1			T2	10		T5	75		T6	2
valid_sources[0x57]	30482	1			T2	9		T3	2		T9	17
valid_sources[0x58]	24826	1			T2	10		T5	43		T6	3
valid_sources[0x59]	21840	1			T1	2		T2	8		T3	2
valid_sources[0x5a]	29301	1			T2	12		T3	1		T5	53
valid_sources[0x5b]	21210	1			T2	10		T3	2		T5	41
valid_sources[0x5c]	29446	1			T2	10		T5	43		T9	15
valid_sources[0x5d]	27854	1			T1	1		T2	7		T3	1
valid_sources[0x5e]	55222	1			T2	14		T5	194		T9	58
valid_sources[0x5f]	29954	1			T2	12		T3	2		T5	99
valid_sources[0x60]	29542	1			T1	1		T2	16		T3	1
valid_sources[0x61]	20957	1			T2	17		T3	3		T6	1
valid_sources[0x62]	22402	1			T2	11		T3	1		T5	48
valid_sources[0x63]	23562	1			T2	22		T3	3		T5	18
valid_sources[0x64]	22071	1			T2	12		T3	1		T5	135
valid_sources[0x65]	21971	1			T2	18		T3	1		T5	2
valid_sources[0x66]	27117	1			T2	9		T5	39		T9	65
valid_sources[0x67]	25476	1			T2	13		T3	7		T5	32
valid_sources[0x68]	28214	1			T2	13		T3	1		T5	8
valid_sources[0x69]	24333	1			T2	13		T3	2		T5	14
valid_sources[0x6a]	26888	1			T2	12		T3	1		T5	90
valid_sources[0x6b]	34091	1			T2	9		T5	20		T6	1
valid_sources[0x6c]	25559	1			T2	12		T3	1		T5	22
valid_sources[0x6d]	24474	1			T2	8		T5	28		T9	26
valid_sources[0x6e]	20476	1			T2	10		T3	3		T5	61
valid_sources[0x6f]	21877	1			T2	10		T3	3		T5	31
valid_sources[0x70]	28666	1			T2	13		T3	1		T5	3
valid_sources[0x71]	34126	1			T2	13		T3	2		T5	40
valid_sources[0x72]	20835	1			T2	11		T3	2		T5	2
valid_sources[0x73]	28828	1			T2	15		T5	64		T9	40
valid_sources[0x74]	23822	1			T2	12		T5	73		T9	52
valid_sources[0x75]	31667	1			T2	13		T3	2		T5	13
valid_sources[0x76]	22147	1			T2	12		T5	112		T6	2
valid_sources[0x77]	25282	1			T2	17		T5	64		T6	1
valid_sources[0x78]	25549	1			T2	10		T3	1		T5	69
valid_sources[0x79]	27630	1			T2	11		T3	1		T5	97
valid_sources[0x7a]	33010	1			T2	14		T3	2		T5	63
valid_sources[0x7b]	24450	1			T2	9		T5	53		T6	3
valid_sources[0x7c]	22865	1			T2	8		T3	1		T5	32
valid_sources[0x7d]	20087	1			T2	11		T3	1		T5	53
valid_sources[0x7e]	27904	1			T2	10		T5	16		T9	38
valid_sources[0x7f]	20477	1			T2	12		T6	2		T9	51
valid_sources[0x80]	21416	1			T2	9		T3	1		T5	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2049861

1

T2

973

T3

75

T4

34551

values[0x0]

all_enables

biggest_size

298610

1

T1

9

T2

88

T3

2

values[0x1]

all_enables

biggest_size

230935

1

T1

6

T2

56

T3

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

531490

1

T2

40

T3

20

T4

1220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	179098	1			T2	20		T3	10		T4	610
values[0x0]	184487	1			T2	11		T3	9		T4	302
values[0x1]	194260	1			T2	9		T3	1		T4	308

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

543212

1

T2

40

T3

20

T4

1220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2219	1			T7	114		T97	2		T66	2
valid_sources[0x01]	2214	1			T101	1		T66	2		T61	55
valid_sources[0x02]	2127	1			T11	2		T7	127		T97	2
valid_sources[0x03]	2104	1			T11	1		T64	5		T66	5
valid_sources[0x04]	2108	1			T11	1		T91	1		T66	6
valid_sources[0x05]	2095	1			T11	1		T12	70		T13	53
valid_sources[0x06]	2004	1			T7	50		T97	1		T93	1
valid_sources[0x07]	2023	1			T97	1		T64	2		T66	4
valid_sources[0x08]	2100	1			T11	1		T97	1		T101	1
valid_sources[0x09]	2223	1			T66	1		T70	1		T196	2
valid_sources[0x0a]	2177	1			T3	1		T11	1		T66	2
valid_sources[0x0b]	2458	1			T7	21		T97	4		T92	1
valid_sources[0x0c]	2624	1			T11	1		T7	192		T14	2
valid_sources[0x0d]	2416	1			T7	18		T97	3		T66	3
valid_sources[0x0e]	2320	1			T11	1		T66	5		T195	2
valid_sources[0x0f]	2423	1			T11	2		T101	1		T14	1
valid_sources[0x10]	2109	1			T66	4		T94	2		T155	2
valid_sources[0x11]	2050	1			T101	2		T92	2		T66	5
valid_sources[0x12]	1940	1			T64	4		T66	5		T94	1
valid_sources[0x13]	2307	1			T11	1		T7	114		T66	1
valid_sources[0x14]	2100	1			T3	1		T11	3		T7	157
valid_sources[0x15]	2453	1			T66	3		T134	1		T195	1
valid_sources[0x16]	2100	1			T92	1		T66	7		T12	89
valid_sources[0x17]	2077	1			T11	1		T7	12		T66	1
valid_sources[0x18]	2367	1			T7	109		T93	1		T66	3
valid_sources[0x19]	1740	1			T66	5		T94	1		T134	1
valid_sources[0x1a]	4016	1			T11	1		T7	21		T93	1
valid_sources[0x1b]	1948	1			T93	1		T66	3		T12	81
valid_sources[0x1c]	3854	1			T7	57		T66	4		T99	2
valid_sources[0x1d]	2125	1			T7	106		T93	2		T134	1
valid_sources[0x1e]	2441	1			T7	167		T93	1		T66	3
valid_sources[0x1f]	2054	1			T66	5		T94	1		T61	8
valid_sources[0x20]	2217	1			T11	2		T7	155		T93	3
valid_sources[0x21]	2147	1			T11	2		T101	1		T66	5
valid_sources[0x22]	1904	1			T11	1		T101	1		T93	6
valid_sources[0x23]	2354	1			T11	1		T101	2		T66	5
valid_sources[0x24]	1927	1			T11	1		T7	86		T97	2
valid_sources[0x25]	2255	1			T11	1		T66	2		T12	58
valid_sources[0x26]	2275	1			T11	4		T101	2		T64	4
valid_sources[0x27]	2123	1			T11	2		T92	2		T66	9
valid_sources[0x28]	2244	1			T11	1		T101	1		T92	1
valid_sources[0x29]	1861	1			T11	1		T66	4		T94	1
valid_sources[0x2a]	1807	1			T11	1		T148	3		T66	1
valid_sources[0x2b]	2028	1			T11	1		T7	63		T101	1
valid_sources[0x2c]	2181	1			T101	2		T92	1		T66	3
valid_sources[0x2d]	1855	1			T11	1		T7	68		T101	1
valid_sources[0x2e]	1997	1			T11	2		T97	1		T66	4
valid_sources[0x2f]	2484	1			T11	1		T7	12		T66	3
valid_sources[0x30]	2228	1			T7	169		T64	3		T93	5
valid_sources[0x31]	2030	1			T11	1		T66	7		T194	6
valid_sources[0x32]	2020	1			T7	62		T97	2		T93	1
valid_sources[0x33]	2433	1			T66	2		T94	1		T61	33
valid_sources[0x34]	1950	1			T97	1		T66	2		T134	2
valid_sources[0x35]	2882	1			T11	1		T66	3		T195	2
valid_sources[0x36]	1925	1			T14	1		T66	4		T156	1
valid_sources[0x37]	2302	1			T11	1		T7	217		T101	1
valid_sources[0x38]	1919	1			T3	1		T11	1		T97	1
valid_sources[0x39]	2422	1			T11	2		T7	82		T66	6
valid_sources[0x3a]	2296	1			T96	200		T66	1		T94	1
valid_sources[0x3b]	2108	1			T101	2		T93	2		T12	116
valid_sources[0x3c]	2033	1			T7	79		T66	4		T134	1
valid_sources[0x3d]	1955	1			T3	1		T148	1		T66	2
valid_sources[0x3e]	1963	1			T3	1		T93	4		T66	1
valid_sources[0x3f]	1968	1			T101	1		T92	1		T93	1
valid_sources[0x40]	2036	1			T7	30		T101	2		T93	2
valid_sources[0x41]	2282	1			T11	1		T148	1		T93	1
valid_sources[0x42]	2362	1			T3	1		T7	25		T66	3
valid_sources[0x43]	2144	1			T66	6		T70	3		T195	1
valid_sources[0x44]	2131	1			T101	3		T66	2		T94	1
valid_sources[0x45]	2228	1			T14	1		T66	7		T195	3
valid_sources[0x46]	1940	1			T93	1		T66	5		T12	80
valid_sources[0x47]	2121	1			T11	1		T66	1		T134	1
valid_sources[0x48]	2092	1			T7	50		T97	2		T92	3
valid_sources[0x49]	1799	1			T11	1		T7	7		T97	5
valid_sources[0x4a]	2886	1			T11	1		T101	2		T93	3
valid_sources[0x4b]	1980	1			T66	2		T94	1		T195	1
valid_sources[0x4c]	2172	1			T61	12		T155	8		T195	1
valid_sources[0x4d]	2806	1			T97	2		T101	1		T66	2
valid_sources[0x4e]	1957	1			T11	2		T97	1		T91	1
valid_sources[0x4f]	2139	1			T7	2		T14	1		T66	2
valid_sources[0x50]	2294	1			T66	6		T195	2		T196	2
valid_sources[0x51]	2139	1			T11	4		T7	9		T92	1
valid_sources[0x52]	2059	1			T11	2		T93	3		T66	4
valid_sources[0x53]	2104	1			T11	1		T101	1		T93	1
valid_sources[0x54]	2017	1			T11	1		T148	1		T66	4
valid_sources[0x55]	2064	1			T101	2		T64	1		T66	3
valid_sources[0x56]	2737	1			T11	1		T7	343		T91	1
valid_sources[0x57]	1968	1			T66	3		T155	3		T195	1
valid_sources[0x58]	2274	1			T64	1		T66	4		T61	23
valid_sources[0x59]	2063	1			T7	30		T93	1		T66	5
valid_sources[0x5a]	1964	1			T97	2		T66	1		T61	1
valid_sources[0x5b]	2264	1			T3	1		T11	1		T7	189
valid_sources[0x5c]	2602	1			T11	1		T97	7		T66	3
valid_sources[0x5d]	2153	1			T11	2		T92	1		T66	4
valid_sources[0x5e]	2040	1			T7	100		T97	4		T66	4
valid_sources[0x5f]	2097	1			T11	1		T101	1		T66	2
valid_sources[0x60]	2022	1			T11	1		T7	11		T101	1
valid_sources[0x61]	2624	1			T7	105		T97	1		T64	1
valid_sources[0x62]	2238	1			T66	1		T61	4		T134	1
valid_sources[0x63]	1848	1			T7	4		T101	1		T66	5
valid_sources[0x64]	2398	1			T101	1		T66	2		T61	9
valid_sources[0x65]	1837	1			T11	1		T93	5		T66	1
valid_sources[0x66]	2106	1			T97	1		T92	2		T66	2
valid_sources[0x67]	2215	1			T11	1		T93	1		T66	4
valid_sources[0x68]	2361	1			T7	104		T66	1		T61	11
valid_sources[0x69]	2154	1			T97	1		T101	1		T66	1
valid_sources[0x6a]	2092	1			T11	1		T97	1		T66	1
valid_sources[0x6b]	2305	1			T11	2		T7	202		T66	4
valid_sources[0x6c]	2676	1			T11	3		T7	660		T66	3
valid_sources[0x6d]	2057	1			T11	1		T101	1		T66	2
valid_sources[0x6e]	2385	1			T66	2		T94	1		T12	85
valid_sources[0x6f]	2075	1			T97	1		T93	1		T66	3
valid_sources[0x70]	2280	1			T66	3		T12	85		T135	1
valid_sources[0x71]	2034	1			T11	1		T66	3		T61	4
valid_sources[0x72]	1813	1			T11	1		T101	1		T64	1
valid_sources[0x73]	1994	1			T3	1		T11	1		T66	3
valid_sources[0x74]	2628	1			T66	3		T12	71		T191	3
valid_sources[0x75]	1978	1			T11	1		T14	1		T66	3
valid_sources[0x76]	2120	1			T11	3		T97	1		T66	5
valid_sources[0x77]	2091	1			T3	1		T11	2		T7	33
valid_sources[0x78]	2653	1			T11	2		T101	1		T93	12
valid_sources[0x79]	2448	1			T97	3		T66	4		T61	52
valid_sources[0x7a]	2164	1			T11	2		T66	3		T94	2
valid_sources[0x7b]	1756	1			T11	1		T66	4		T337	5
valid_sources[0x7c]	2072	1			T101	1		T91	3		T66	1
valid_sources[0x7d]	3432	1			T92	1		T66	3		T94	1
valid_sources[0x7e]	2352	1			T11	2		T7	254		T93	2
valid_sources[0x7f]	2038	1			T66	4		T61	19		T134	1
valid_sources[0x80]	1937	1			T11	1		T7	48		T91	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

165608

1

T2

20

T3

10

T4

610

values[0x0]

all_enables

biggest_size

183029

1

T2

11

T3

9

T4

302

values[0x1]

all_enables

biggest_size

182853

1

T2

9

T3

1

T4

308