Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.13	94.16	96.15	96.73		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	96441441	360974	0	0
check_regwen_rd_A	96441441	680	0	0
check_timeout_rd_A	96441441	401	0	0
check_trigger_regwen_rd_A	96441441	748	0	0
consistency_check_period_rd_A	96441441	843	0	0
creator_sw_cfg_read_lock_rd_A	96441441	449	0	0
direct_access_address_rd_A	96441441	273	0	0
direct_access_wdata_0_rd_A	96441441	23	0	0
direct_access_wdata_1_rd_A	96441441	72	0	0
integrity_check_period_rd_A	96441441	757	0	0
intr_enable_rd_A	96441441	1691	0	0
owner_sw_cfg_read_lock_rd_A	96441441	477	0	0
rot_creator_auth_codesign_read_lock_rd_A	96441441	370	0	0
rot_creator_auth_state_read_lock_rd_A	96441441	451	0	0
vendor_test_read_lock_rd_A	96441441	457	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	360974	0	0
T7	417643	7489	0	0
T8	40619	0	0	0
T12	0	14426	0	0
T13	0	9142	0	0
T15	0	1590	0	0
T23	0	10899	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T57	0	5266	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T164	0	6622	0	0
T240	0	9913	0	0
T265	0	7035	0	0
T266	0	6646	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	680	0	0
T7	417643	33	0	0
T8	40619	0	0	0
T17	0	9	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	28	0	0
T248	0	34	0	0
T249	0	20	0	0
T294	0	29	0	0
T295	0	11	0	0
T296	0	13	0	0
T297	0	27	0	0
T298	0	4	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	401	0	0
T7	417643	53	0	0
T8	40619	0	0	0
T17	0	25	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	33	0	0
T248	0	28	0	0
T249	0	7	0	0
T294	0	43	0	0
T295	0	12	0	0
T296	0	16	0	0
T297	0	19	0	0
T298	0	13	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	748	0	0
T7	417643	52	0	0
T8	40619	0	0	0
T17	0	34	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	35	0	0
T248	0	10	0	0
T249	0	20	0	0
T294	0	39	0	0
T295	0	6	0	0
T296	0	12	0	0
T297	0	20	0	0
T298	0	15	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	843	0	0
T7	417643	41	0	0
T8	40619	0	0	0
T17	0	41	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	37	0	0
T248	0	31	0	0
T249	0	9	0	0
T294	0	35	0	0
T295	0	19	0	0
T296	0	4	0	0
T297	0	27	0	0
T298	0	12	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	449	0	0
T7	417643	40	0	0
T8	40619	0	0	0
T17	0	32	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	25	0	0
T248	0	14	0	0
T249	0	15	0	0
T294	0	48	0	0
T295	0	9	0	0
T296	0	8	0	0
T297	0	17	0	0
T298	0	21	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	273	0	0
T7	417643	60	0	0
T8	40619	0	0	0
T17	0	17	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	26	0	0
T248	0	19	0	0
T249	0	8	0	0
T294	0	45	0	0
T295	0	7	0	0
T296	0	8	0	0
T297	0	21	0	0
T298	0	14	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	23	0	0
T7	417643	5	0	0
T8	40619	0	0	0
T17	0	4	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T294	0	9	0	0
T295	0	2	0	0
T299	0	3	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	72	0	0
T7	417643	24	0	0
T8	40619	0	0	0
T17	0	3	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	9	0	0
T248	0	22	0	0
T294	0	13	0	0
T298	0	1	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	757	0	0
T7	417643	51	0	0
T8	40619	0	0	0
T17	0	15	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	29	0	0
T248	0	18	0	0
T249	0	5	0	0
T294	0	46	0	0
T295	0	1	0	0
T296	0	20	0	0
T297	0	23	0	0
T298	0	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	1691	0	0
T7	417643	86	0	0
T8	40619	0	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	50	0	0
T248	0	43	0	0
T249	0	17	0	0
T293	0	28	0	0
T294	0	75	0	0
T300	0	6	0	0
T301	0	44	0	0
T302	0	39	0	0
T303	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	477	0	0
T7	417643	36	0	0
T8	40619	0	0	0
T17	0	27	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	33	0	0
T248	0	31	0	0
T249	0	10	0	0
T294	0	55	0	0
T295	0	17	0	0
T296	0	17	0	0
T297	0	15	0	0
T298	0	4	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	370	0	0
T7	417643	47	0	0
T8	40619	0	0	0
T17	0	15	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	31	0	0
T248	0	20	0	0
T249	0	14	0	0
T294	0	39	0	0
T295	0	9	0	0
T296	0	3	0	0
T297	0	23	0	0
T298	0	9	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	451	0	0
T7	417643	38	0	0
T8	40619	0	0	0
T17	0	24	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	55	0	0
T248	0	11	0	0
T249	0	17	0	0
T294	0	52	0	0
T295	0	4	0	0
T296	0	11	0	0
T297	0	7	0	0
T298	0	12	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96441441	457	0	0
T7	417643	49	0	0
T8	40619	0	0	0
T17	0	22	0	0
T24	83812	0	0	0
T28	20410	0	0	0
T63	16559	0	0	0
T64	9660	0	0	0
T95	22346	0	0	0
T96	138993	0	0	0
T97	33387	0	0	0
T101	68151	0	0	0
T235	0	53	0	0
T248	0	31	0	0
T249	0	15	0	0
T294	0	35	0	0
T295	0	7	0	0
T296	0	12	0	0
T297	0	30	0	0
T298	0	1	0	0