Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4143746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2379793

1

T1

239

T2

186

T3

259

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5487172	1			T1	477		T2	333		T3	688
values[0x0]	490945	1			T1	147		T2	108		T3	156
values[0x1]	545422	1			T1	147		T2	116		T3	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3066110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3457429

1

T1

388

T2

282

T3

452

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20263	1			T2	9		T3	4		T4	21
valid_sources[0x01]	20997	1			T3	1		T4	21		T10	5
valid_sources[0x02]	20492	1			T3	5		T4	20		T10	11
valid_sources[0x03]	22564	1			T2	3		T3	3		T4	16
valid_sources[0x04]	20217	1			T2	2		T3	1		T4	23
valid_sources[0x05]	19974	1			T2	1		T3	1		T4	21
valid_sources[0x06]	29049	1			T2	1		T4	22		T10	12
valid_sources[0x07]	19895	1			T2	4		T3	4		T4	22
valid_sources[0x08]	19362	1			T2	2		T3	2		T4	21
valid_sources[0x09]	22161	1			T2	3		T3	2		T4	26
valid_sources[0x0a]	19648	1			T2	2		T3	2		T4	22
valid_sources[0x0b]	20039	1			T2	2		T4	25		T10	13
valid_sources[0x0c]	19634	1			T2	1		T3	5		T4	24
valid_sources[0x0d]	19110	1			T2	1		T3	3		T4	27
valid_sources[0x0e]	23193	1			T2	3		T3	4		T4	24
valid_sources[0x0f]	18836	1			T3	1		T4	18		T10	7
valid_sources[0x10]	19035	1			T2	1		T3	3		T4	14
valid_sources[0x11]	21161	1			T2	2		T3	4		T4	19
valid_sources[0x12]	20943	1			T2	4		T3	3		T4	22
valid_sources[0x13]	21356	1			T2	3		T3	1		T4	25
valid_sources[0x14]	20598	1			T2	3		T3	3		T4	28
valid_sources[0x15]	21752	1			T2	1		T3	2		T4	20
valid_sources[0x16]	20626	1			T2	10		T4	25		T10	6
valid_sources[0x17]	21620	1			T2	7		T3	1		T4	28
valid_sources[0x18]	22057	1			T2	3		T3	4		T4	25
valid_sources[0x19]	25102	1			T2	2		T3	2		T4	16
valid_sources[0x1a]	19921	1			T2	1		T3	1		T4	30
valid_sources[0x1b]	37105	1			T2	2		T4	28		T10	10
valid_sources[0x1c]	22525	1			T3	3		T4	24		T10	11
valid_sources[0x1d]	19495	1			T2	1		T3	5		T4	25
valid_sources[0x1e]	26658	1			T2	2		T3	8		T4	14
valid_sources[0x1f]	19157	1			T2	1		T3	2		T4	23
valid_sources[0x20]	23145	1			T2	3		T3	5		T4	18
valid_sources[0x21]	24312	1			T3	4		T4	30		T10	11
valid_sources[0x22]	23416	1			T2	6		T3	7		T4	20
valid_sources[0x23]	18828	1			T2	1		T3	2		T4	19
valid_sources[0x24]	20219	1			T2	1		T3	5		T4	19
valid_sources[0x25]	20501	1			T2	2		T3	15		T4	25
valid_sources[0x26]	23578	1			T2	1		T3	1		T4	15
valid_sources[0x27]	26095	1			T2	3		T3	2		T4	25
valid_sources[0x28]	19790	1			T2	2		T3	2		T4	20
valid_sources[0x29]	24903	1			T2	3		T3	2		T4	28
valid_sources[0x2a]	27801	1			T3	1		T4	30		T10	6
valid_sources[0x2b]	93230	1			T2	4		T3	3		T4	24
valid_sources[0x2c]	19481	1			T2	1		T3	14		T4	19
valid_sources[0x2d]	19443	1			T2	1		T3	4		T4	22
valid_sources[0x2e]	29073	1			T2	3		T3	5		T4	30
valid_sources[0x2f]	20067	1			T2	2		T3	1		T4	27
valid_sources[0x30]	22447	1			T2	7		T3	2		T4	23
valid_sources[0x31]	28600	1			T3	10		T4	25		T10	11
valid_sources[0x32]	19627	1			T3	3		T4	19		T10	19
valid_sources[0x33]	19689	1			T3	5		T4	25		T10	9
valid_sources[0x34]	20439	1			T2	3		T3	3		T4	24
valid_sources[0x35]	22406	1			T2	3		T3	5		T4	10
valid_sources[0x36]	18972	1			T2	4		T3	1		T4	21
valid_sources[0x37]	19938	1			T2	6		T3	2		T4	29
valid_sources[0x38]	29108	1			T2	3		T4	23		T10	14
valid_sources[0x39]	31737	1			T2	4		T3	6		T4	25
valid_sources[0x3a]	20565	1			T2	3		T3	5		T4	23
valid_sources[0x3b]	46156	1			T2	4		T3	10		T4	34
valid_sources[0x3c]	20088	1			T2	3		T3	9		T4	20
valid_sources[0x3d]	21721	1			T2	6		T3	1		T4	32
valid_sources[0x3e]	20209	1			T2	5		T3	3		T4	18
valid_sources[0x3f]	25758	1			T2	1		T3	2		T4	27
valid_sources[0x40]	19982	1			T2	2		T3	6		T4	24
valid_sources[0x41]	42950	1			T2	5		T3	7		T4	24
valid_sources[0x42]	26615	1			T2	1		T3	5		T4	25
valid_sources[0x43]	30188	1			T2	4		T3	2		T4	16
valid_sources[0x44]	27700	1			T2	1		T3	7		T4	14
valid_sources[0x45]	31914	1			T3	3		T4	19		T10	11
valid_sources[0x46]	20179	1			T2	2		T3	2		T4	26
valid_sources[0x47]	19064	1			T2	1		T3	3		T4	20
valid_sources[0x48]	35757	1			T3	5		T4	23		T10	9
valid_sources[0x49]	58853	1			T2	1		T3	4		T4	24
valid_sources[0x4a]	30021	1			T2	1		T3	9		T4	28
valid_sources[0x4b]	29244	1			T2	3		T3	5		T4	22
valid_sources[0x4c]	25992	1			T3	2		T4	24		T10	7
valid_sources[0x4d]	20068	1			T2	1		T3	4		T4	26
valid_sources[0x4e]	30335	1			T2	1		T3	2		T4	23
valid_sources[0x4f]	30971	1			T2	3		T3	8		T4	29
valid_sources[0x50]	21321	1			T2	2		T3	2		T4	18
valid_sources[0x51]	45134	1			T2	4		T3	4		T4	20
valid_sources[0x52]	23398	1			T2	3		T3	5		T4	20
valid_sources[0x53]	19087	1			T2	1		T3	5		T4	27
valid_sources[0x54]	19278	1			T2	4		T3	1		T4	24
valid_sources[0x55]	27122	1			T2	4		T3	1		T4	31
valid_sources[0x56]	21288	1			T3	2		T4	19		T10	20
valid_sources[0x57]	20970	1			T2	1		T3	3		T4	33
valid_sources[0x58]	20233	1			T3	10		T4	16		T10	11
valid_sources[0x59]	20249	1			T2	3		T3	5		T4	26
valid_sources[0x5a]	30024	1			T2	1		T3	7		T4	25
valid_sources[0x5b]	19961	1			T3	1		T4	21		T10	17
valid_sources[0x5c]	35590	1			T2	1		T3	6		T4	26
valid_sources[0x5d]	19527	1			T2	3		T3	3		T4	27
valid_sources[0x5e]	26611	1			T3	6		T4	23		T10	9
valid_sources[0x5f]	19106	1			T2	1		T3	4		T4	26
valid_sources[0x60]	20381	1			T2	1		T3	6		T4	31
valid_sources[0x61]	20302	1			T3	3		T4	24		T10	3
valid_sources[0x62]	20131	1			T2	6		T3	2		T4	25
valid_sources[0x63]	19791	1			T2	3		T4	26		T10	16
valid_sources[0x64]	19071	1			T2	3		T3	7		T4	13
valid_sources[0x65]	22628	1			T3	5		T4	32		T10	11
valid_sources[0x66]	19558	1			T2	7		T3	10		T4	20
valid_sources[0x67]	20428	1			T2	2		T3	6		T4	16
valid_sources[0x68]	19436	1			T2	2		T3	2		T4	29
valid_sources[0x69]	27351	1			T3	5		T4	14		T10	9
valid_sources[0x6a]	20247	1			T2	3		T3	3		T4	22
valid_sources[0x6b]	30502	1			T2	5		T3	2		T4	22
valid_sources[0x6c]	19389	1			T2	2		T3	6		T4	30
valid_sources[0x6d]	19149	1			T3	3		T4	22		T10	4
valid_sources[0x6e]	106673	1			T2	3		T3	8		T4	20
valid_sources[0x6f]	19165	1			T2	1		T3	1		T4	34
valid_sources[0x70]	19761	1			T3	3		T4	28		T10	8
valid_sources[0x71]	18929	1			T2	1		T3	7		T4	27
valid_sources[0x72]	33962	1			T2	2		T3	4		T4	16
valid_sources[0x73]	31046	1			T2	2		T3	9		T4	30
valid_sources[0x74]	19764	1			T3	7		T4	28		T10	12
valid_sources[0x75]	32551	1			T2	4		T4	19		T10	9
valid_sources[0x76]	20921	1			T2	3		T3	4		T4	18
valid_sources[0x77]	20337	1			T3	2		T4	13		T10	11
valid_sources[0x78]	19352	1			T2	2		T3	1		T4	30
valid_sources[0x79]	19139	1			T3	3		T4	21		T10	13
valid_sources[0x7a]	32086	1			T2	2		T3	4		T4	26
valid_sources[0x7b]	33220	1			T2	4		T3	7		T4	24
valid_sources[0x7c]	23881	1			T2	5		T3	1		T4	21
valid_sources[0x7d]	21610	1			T2	7		T3	4		T4	24
valid_sources[0x7e]	20207	1			T3	4		T4	13		T10	15
valid_sources[0x7f]	25270	1			T2	1		T3	4		T4	28
valid_sources[0x80]	19667	1			T2	1		T3	5		T4	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1895869

1

T1

109

T2

95

T3

131

values[0x0]

all_enables

biggest_size

272795

1

T1

71

T2

43

T3

76

values[0x1]

all_enables

biggest_size

211129

1

T1

59

T2

48

T3

52

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463738

1

T4

100

T10

60

T5

160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	159283	1			T4	50		T10	30		T5	80
values[0x0]	161085	1			T4	27		T10	19		T5	39
values[0x1]	168997	1			T4	23		T10	11		T5	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

474908

1

T4

100

T10

60

T5

160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1581	1			T10	1		T7	1		T8	54
valid_sources[0x01]	1986	1			T10	1		T5	2		T11	1
valid_sources[0x02]	1792	1			T11	1		T7	22		T76	1
valid_sources[0x03]	2095	1			T11	1		T7	101		T8	49
valid_sources[0x04]	1514	1			T8	85		T166	4		T109	1
valid_sources[0x05]	2464	1			T10	1		T12	1		T7	6
valid_sources[0x06]	2012	1			T11	2		T7	133		T8	48
valid_sources[0x07]	1948	1			T4	6		T5	9		T7	15
valid_sources[0x08]	1554	1			T7	22		T76	1		T8	64
valid_sources[0x09]	1759	1			T7	15		T8	64		T95	1
valid_sources[0x0a]	1802	1			T5	1		T11	1		T76	1
valid_sources[0x0b]	1888	1			T10	1		T7	46		T76	1
valid_sources[0x0c]	1804	1			T7	13		T8	55		T166	5
valid_sources[0x0d]	2106	1			T7	100		T8	73		T137	1
valid_sources[0x0e]	2019	1			T5	1		T7	63		T8	57
valid_sources[0x0f]	1972	1			T11	1		T12	1		T7	107
valid_sources[0x10]	2649	1			T10	2		T11	1		T7	43
valid_sources[0x11]	1970	1			T12	2		T7	11		T76	1
valid_sources[0x12]	2016	1			T11	2		T7	47		T8	68
valid_sources[0x13]	1700	1			T7	38		T8	71		T142	1
valid_sources[0x14]	1877	1			T4	3		T7	75		T8	64
valid_sources[0x15]	1732	1			T7	49		T76	1		T8	55
valid_sources[0x16]	1562	1			T10	1		T11	2		T12	1
valid_sources[0x17]	1904	1			T10	1		T11	1		T12	1
valid_sources[0x18]	1739	1			T7	45		T8	62		T68	100
valid_sources[0x19]	2155	1			T11	2		T12	2		T7	62
valid_sources[0x1a]	1630	1			T10	2		T5	2		T11	1
valid_sources[0x1b]	1740	1			T5	6		T7	19		T8	68
valid_sources[0x1c]	1896	1			T10	1		T11	1		T12	1
valid_sources[0x1d]	2004	1			T10	1		T5	5		T7	63
valid_sources[0x1e]	2000	1			T11	3		T7	8		T8	66
valid_sources[0x1f]	1973	1			T8	50		T15	17		T339	1
valid_sources[0x20]	1803	1			T5	4		T12	1		T7	54
valid_sources[0x21]	1830	1			T7	9		T8	52		T166	3
valid_sources[0x22]	1740	1			T4	11		T10	1		T11	1
valid_sources[0x23]	1748	1			T7	28		T8	52		T15	4
valid_sources[0x24]	1820	1			T7	34		T8	59		T95	1
valid_sources[0x25]	1867	1			T5	1		T11	1		T7	67
valid_sources[0x26]	1999	1			T5	3		T11	1		T7	11
valid_sources[0x27]	1858	1			T12	1		T7	33		T8	56
valid_sources[0x28]	1875	1			T10	1		T12	1		T7	6
valid_sources[0x29]	1839	1			T4	4		T12	2		T7	6
valid_sources[0x2a]	1993	1			T10	1		T8	55		T137	1
valid_sources[0x2b]	1957	1			T11	1		T12	1		T8	61
valid_sources[0x2c]	1684	1			T7	15		T8	63		T15	7
valid_sources[0x2d]	1992	1			T11	2		T8	63		T110	200
valid_sources[0x2e]	1766	1			T11	3		T7	7		T8	47
valid_sources[0x2f]	2021	1			T5	2		T11	2		T7	9
valid_sources[0x30]	1629	1			T4	1		T10	2		T7	7
valid_sources[0x31]	1652	1			T11	3		T7	11		T76	1
valid_sources[0x32]	1600	1			T11	2		T8	61		T166	1
valid_sources[0x33]	1953	1			T4	3		T7	64		T8	61
valid_sources[0x34]	1812	1			T11	1		T7	8		T8	60
valid_sources[0x35]	1846	1			T10	2		T11	1		T12	1
valid_sources[0x36]	1981	1			T5	2		T7	227		T8	57
valid_sources[0x37]	1897	1			T7	174		T8	50		T9	2
valid_sources[0x38]	1698	1			T5	1		T76	3		T8	56
valid_sources[0x39]	1890	1			T11	2		T12	1		T7	9
valid_sources[0x3a]	1821	1			T11	1		T8	67		T137	1
valid_sources[0x3b]	2415	1			T7	267		T76	2		T8	59
valid_sources[0x3c]	1697	1			T11	3		T7	25		T8	55
valid_sources[0x3d]	2001	1			T5	6		T11	2		T7	26
valid_sources[0x3e]	2064	1			T7	38		T8	77		T99	6
valid_sources[0x3f]	2190	1			T10	1		T11	1		T12	1
valid_sources[0x40]	1686	1			T76	1		T8	56		T109	1
valid_sources[0x41]	1966	1			T5	1		T11	1		T7	77
valid_sources[0x42]	2366	1			T7	121		T8	56		T137	1
valid_sources[0x43]	1734	1			T5	2		T12	4		T7	8
valid_sources[0x44]	2225	1			T11	4		T7	27		T8	57
valid_sources[0x45]	2298	1			T11	1		T7	32		T8	52
valid_sources[0x46]	1821	1			T10	2		T11	1		T12	1
valid_sources[0x47]	1892	1			T11	1		T8	48		T142	6
valid_sources[0x48]	1569	1			T11	1		T12	1		T7	18
valid_sources[0x49]	1667	1			T11	2		T12	1		T7	34
valid_sources[0x4a]	1898	1			T5	6		T7	74		T8	59
valid_sources[0x4b]	2024	1			T7	8		T76	1		T8	61
valid_sources[0x4c]	1912	1			T11	2		T7	31		T8	55
valid_sources[0x4d]	1837	1			T5	2		T11	3		T76	2
valid_sources[0x4e]	1617	1			T11	1		T7	4		T8	67
valid_sources[0x4f]	1586	1			T11	2		T7	7		T8	63
valid_sources[0x50]	2058	1			T11	3		T12	1		T7	19
valid_sources[0x51]	1805	1			T11	1		T7	47		T76	1
valid_sources[0x52]	1872	1			T12	1		T7	23		T8	57
valid_sources[0x53]	1751	1			T12	1		T7	20		T8	59
valid_sources[0x54]	1906	1			T12	1		T7	43		T8	62
valid_sources[0x55]	2299	1			T10	3		T7	108		T8	53
valid_sources[0x56]	1738	1			T10	1		T7	10		T76	1
valid_sources[0x57]	1659	1			T7	29		T8	51		T15	4
valid_sources[0x58]	1739	1			T12	2		T7	24		T76	1
valid_sources[0x59]	2037	1			T11	1		T12	1		T7	15
valid_sources[0x5a]	1804	1			T13	100		T7	38		T8	52
valid_sources[0x5b]	1944	1			T8	55		T137	1		T15	4
valid_sources[0x5c]	1852	1			T5	12		T11	1		T12	1
valid_sources[0x5d]	1710	1			T10	1		T8	37		T401	1
valid_sources[0x5e]	1654	1			T4	1		T7	65		T8	60
valid_sources[0x5f]	1761	1			T5	1		T11	3		T7	18
valid_sources[0x60]	1859	1			T5	3		T11	3		T7	29
valid_sources[0x61]	1940	1			T7	24		T8	63		T15	3
valid_sources[0x62]	1821	1			T11	2		T12	1		T7	8
valid_sources[0x63]	1725	1			T4	4		T7	84		T76	1
valid_sources[0x64]	1745	1			T11	2		T12	1		T7	20
valid_sources[0x65]	2270	1			T11	4		T7	95		T8	49
valid_sources[0x66]	1765	1			T4	3		T7	33		T8	57
valid_sources[0x67]	1922	1			T4	5		T10	1		T7	37
valid_sources[0x68]	2443	1			T12	1		T8	52		T137	1
valid_sources[0x69]	1912	1			T5	3		T7	12		T76	2
valid_sources[0x6a]	1672	1			T4	4		T12	1		T8	46
valid_sources[0x6b]	1864	1			T7	27		T8	67		T109	1
valid_sources[0x6c]	1733	1			T11	3		T8	60		T166	5
valid_sources[0x6d]	1961	1			T8	62		T9	1		T15	4
valid_sources[0x6e]	1995	1			T7	1		T76	1		T8	66
valid_sources[0x6f]	2013	1			T11	1		T7	6		T8	92
valid_sources[0x70]	1702	1			T7	4		T8	47		T15	5
valid_sources[0x71]	1688	1			T8	59		T15	5		T103	1
valid_sources[0x72]	1850	1			T5	3		T7	37		T8	56
valid_sources[0x73]	1805	1			T5	3		T11	1		T12	1
valid_sources[0x74]	2093	1			T11	1		T7	29		T8	55
valid_sources[0x75]	1592	1			T10	2		T7	35		T76	1
valid_sources[0x76]	1983	1			T7	61		T8	45		T137	1
valid_sources[0x77]	2075	1			T4	4		T5	2		T7	26
valid_sources[0x78]	1751	1			T11	2		T7	2		T76	2
valid_sources[0x79]	1746	1			T10	2		T7	2		T8	71
valid_sources[0x7a]	2147	1			T11	2		T7	80		T8	55
valid_sources[0x7b]	1706	1			T5	5		T7	56		T8	59
valid_sources[0x7c]	1663	1			T7	16		T76	2		T8	56
valid_sources[0x7d]	1919	1			T5	3		T11	1		T12	1
valid_sources[0x7e]	1802	1			T10	1		T5	5		T11	2
valid_sources[0x7f]	1763	1			T7	18		T8	53		T15	2
valid_sources[0x80]	2245	1			T7	6		T8	46		T15	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

145782

1

T4

50

T10

30

T5

80

values[0x0]

all_enables

biggest_size

159602

1

T4

27

T10

19

T5

39

values[0x1]

all_enables

biggest_size

158354

1

T4

23

T10

11

T5

41