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Module Instance : tb.dut.u_otp_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 98.07 97.16 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 98.07 97.16 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.19 94.16 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_otp_arb
Line Coverage for Instance : tb.dut.u_otp_arb
Line No.TotalCoveredPercent
TOTAL20720398.07
CONT_ASSIGN6211100.00
CONT_ASSIGN11211100.00
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CONT_ASSIGN11811100.00
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CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
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CONT_ASSIGN12811100.00
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CONT_ASSIGN13811100.00
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CONT_ASSIGN14811100.00
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CONT_ASSIGN14800
CONT_ASSIGN15011100.00
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CONT_ASSIGN15000
CONT_ASSIGN15111100.00
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CONT_ASSIGN15100
CONT_ASSIGN15511100.00
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CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
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CONT_ASSIGN15611100.00
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CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
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CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN156100.00
CONT_ASSIGN16011100.00
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CONT_ASSIGN16000
CONT_ASSIGN16111100.00
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CONT_ASSIGN16300
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CONT_ASSIGN16311100.00
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CONT_ASSIGN16300
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CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
112 13 14
118 14 14
122 13 14
126 14 14
128 14 14
138 2 2
148 14 14(1 unreachable)
150 14 14(1 unreachable)
151 14 14(1 unreachable)
155 14 15
156 14 15
160 14 14(1 unreachable)
161 15 15
163 11 11(4 unreachable)
164 15 15
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_otp_arb
TotalCoveredPercent
Conditions52951497.16
Logical52951497.16
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
118-15696.83
156-16498.00

Branch Coverage for Instance : tb.dut.u_otp_arb
Line No.TotalCoveredPercent
Branches 88 88 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CheckHotOne_A 91088385 90242584 0 0
CheckNGreaterZero_A 1118 1118 0 0
GntImpliesReady_A 91088385 1269539 0 0
GntImpliesValid_A 91088385 1269539 0 0
GrantKnown_A 91088385 90242584 0 0
IdxKnown_A 91088385 90242584 0 0
IndexIsCorrect_A 91088385 1269539 0 0
LockArbDecision_A 91088385 6491250 0 0
NoReadyValidNoGrant_A 91088385 6934940 0 0
ReadyAndValidImplyGrant_A 91088385 1269539 0 0
ReqAndReadyImplyGrant_A 91088385 1269539 0 0
ReqImpliesValid_A 91088385 7762152 0 0
ReqStaysHighUntilGranted0_M 91088385 6491250 0 0
RoundRobin_A 91088385 0 0 1107
ValidKnown_A 91088385 90242584 0 0
gen_data_port_assertion.DataFlow_A 91088385 1269539 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 90242584 0 0
T1 13602 13427 0 0
T2 11640 11368 0 0
T3 16395 16147 0 0
T4 37444 36690 0 0
T5 45136 44040 0 0
T6 102177 101355 0 0
T10 25593 25322 0 0
T11 18212 17932 0 0
T12 79294 78617 0 0
T13 82776 82075 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1118 1118 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 1269539 0 0
T1 13602 164 0 0
T2 11640 138 0 0
T3 16395 277 0 0
T4 37444 832 0 0
T5 45136 1249 0 0
T6 102177 784 0 0
T10 25593 156 0 0
T11 18212 138 0 0
T12 79294 760 0 0
T13 82776 854 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 1269539 0 0
T1 13602 164 0 0
T2 11640 138 0 0
T3 16395 277 0 0
T4 37444 832 0 0
T5 45136 1249 0 0
T6 102177 784 0 0
T10 25593 156 0 0
T11 18212 138 0 0
T12 79294 760 0 0
T13 82776 854 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 90242584 0 0
T1 13602 13427 0 0
T2 11640 11368 0 0
T3 16395 16147 0 0
T4 37444 36690 0 0
T5 45136 44040 0 0
T6 102177 101355 0 0
T10 25593 25322 0 0
T11 18212 17932 0 0
T12 79294 78617 0 0
T13 82776 82075 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 90242584 0 0
T1 13602 13427 0 0
T2 11640 11368 0 0
T3 16395 16147 0 0
T4 37444 36690 0 0
T5 45136 44040 0 0
T6 102177 101355 0 0
T10 25593 25322 0 0
T11 18212 17932 0 0
T12 79294 78617 0 0
T13 82776 82075 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 1269539 0 0
T1 13602 164 0 0
T2 11640 138 0 0
T3 16395 277 0 0
T4 37444 832 0 0
T5 45136 1249 0 0
T6 102177 784 0 0
T10 25593 156 0 0
T11 18212 138 0 0
T12 79294 760 0 0
T13 82776 854 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 6491250 0 0
T1 13602 676 0 0
T2 11640 624 0 0
T3 16395 1532 0 0
T4 37444 5872 0 0
T5 45136 8477 0 0
T6 102177 7031 0 0
T10 25593 1344 0 0
T11 18212 1639 0 0
T12 79294 5331 0 0
T13 82776 6099 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 6934940 0 0
T1 13602 1391 0 0
T2 11640 1080 0 0
T3 16395 2280 0 0
T4 37444 4970 0 0
T5 45136 6269 0 0
T6 102177 4388 0 0
T10 25593 1010 0 0
T11 18212 497 0 0
T12 79294 4843 0 0
T13 82776 4840 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 1269539 0 0
T1 13602 164 0 0
T2 11640 138 0 0
T3 16395 277 0 0
T4 37444 832 0 0
T5 45136 1249 0 0
T6 102177 784 0 0
T10 25593 156 0 0
T11 18212 138 0 0
T12 79294 760 0 0
T13 82776 854 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 1269539 0 0
T1 13602 164 0 0
T2 11640 138 0 0
T3 16395 277 0 0
T4 37444 832 0 0
T5 45136 1249 0 0
T6 102177 784 0 0
T10 25593 156 0 0
T11 18212 138 0 0
T12 79294 760 0 0
T13 82776 854 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 7762152 0 0
T1 13602 842 0 0
T2 11640 762 0 0
T3 16395 1812 0 0
T4 37444 6704 0 0
T5 45136 9727 0 0
T6 102177 7819 0 0
T10 25593 1500 0 0
T11 18212 1778 0 0
T12 79294 6094 0 0
T13 82776 6954 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 6491250 0 0
T1 13602 676 0 0
T2 11640 624 0 0
T3 16395 1532 0 0
T4 37444 5872 0 0
T5 45136 8477 0 0
T6 102177 7031 0 0
T10 25593 1344 0 0
T11 18212 1639 0 0
T12 79294 5331 0 0
T13 82776 6099 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 0 0 1107

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 90242584 0 0
T1 13602 13427 0 0
T2 11640 11368 0 0
T3 16395 16147 0 0
T4 37444 36690 0 0
T5 45136 44040 0 0
T6 102177 101355 0 0
T10 25593 25322 0 0
T11 18212 17932 0 0
T12 79294 78617 0 0
T13 82776 82075 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91088385 1269539 0 0
T1 13602 164 0 0
T2 11640 138 0 0
T3 16395 277 0 0
T4 37444 832 0 0
T5 45136 1249 0 0
T6 102177 784 0 0
T10 25593 156 0 0
T11 18212 138 0 0
T12 79294 760 0 0
T13 82776 854 0 0