SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_tlul_data_integ_dec |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_tlul_data_integ_dec |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 160 | 160 | 100.00 |
Total Bits 0->1 | 80 | 80 | 100.00 |
Total Bits 1->0 | 80 | 80 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 160 | 160 | 100.00 |
Port Bits 0->1 | 80 | 80 | 100.00 |
Port Bits 1->0 | 80 | 80 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[38:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
data_o[31:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 160 | 160 | 100.00 |
Total Bits 0->1 | 80 | 80 | 100.00 |
Total Bits 1->0 | 80 | 80 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 160 | 160 | 100.00 |
Port Bits 0->1 | 80 | 80 | 100.00 |
Port Bits 1->0 | 80 | 80 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[38:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
data_o[31:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 160 | 160 | 100.00 |
Total Bits 0->1 | 80 | 80 | 100.00 |
Total Bits 1->0 | 80 | 80 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 160 | 160 | 100.00 |
Port Bits 0->1 | 80 | 80 | 100.00 |
Port Bits 1->0 | 80 | 80 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[38:0] | Yes | Yes | T13,T7,T8 | Yes | T13,T7,T8 | INPUT |
data_o[31:0] | Yes | Yes | T13,T7,T8 | Yes | T13,T7,T8 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T7,T8,T98 | Yes | T7,T8,T98 | OUTPUT |
err_o[1:0] | Yes | Yes | T13,T7,T8 | Yes | T13,T7,T8 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |