Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T171,T169,T172
1	Covered	T171,T169,T172

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T5,T11
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T110,T197,T198
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T10,T5,T6
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T2,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T10,T5,T6
CheckFailError	317	Covered	T171,T169,T172
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T10,T8,T9
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T10,T5,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T171,T169,T172
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T10,T5,T6
NoError->CheckFailError	317	Covered	T171,T169,T172
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T98,T143
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T76
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T10,T11,T76
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T171,T169,T172
1	0	Covered	T171,T169,T172
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T66,T108
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	91088385	90242584	0	0
DigestKnown_A	91088385	90242584	0	0
DigestOffsetMustBeRepresentable_A	1118	1118	0	0
EccErrorState_A	91088385	8767	0	0
ErrorKnown_A	91088385	90242584	0	0
FsmStateKnown_A	91088385	90242584	0	0
InitDoneKnown_A	91088385	90242584	0	0
InitReadLocksPartition_A	91088385	16324395	0	0
InitWriteLocksPartition_A	91088385	16324395	0	0
OffsetMustBeBlockAligned_A	1118	1118	0	0
OtpAddrKnown_A	91088385	90242584	0	0
OtpCmdKnown_A	91088385	90242584	0	0
OtpErrorState_A	91088385	0	0	0
OtpReqKnown_A	91088385	90242584	0	0
OtpSizeKnown_A	91088385	90242584	0	0
OtpWdataKnown_A	91088385	90242584	0	0
ReadLockPropagation_A	91088385	16054075	0	0
SizeMustBeBlockAligned_A	1118	1118	0	0
TlulGntKnown_A	91088385	90242584	0	0
TlulRdataKnown_A	91088385	90242584	0	0
TlulReadOnReadLock_A	91088385	5745	0	0
TlulRerrorKnown_A	91088385	90242584	0	0
TlulRvalidKnown_A	91088385	90242584	0	0
WriteLockPropagation_A	91088385	2717963	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	91088385	30977357	0	0
u_state_regs_A	91088385	90242584	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	8767	0	0
T22	993553	0	0	0
T25	14962	0	0	0
T169	0	2557	0	0
T171	13276	3390	0	0
T172	0	2820	0	0
T175	361188	0	0	0
T181	50917	0	0	0
T182	8438	0	0	0
T183	8642	0	0	0
T184	480473	0	0	0
T185	22032	0	0	0
T186	14538	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16324395	0	0
T1	13602	3701	0	0
T2	11640	3430	0	0
T3	16395	3822	0	0
T4	37444	604	0	0
T5	45136	921	0	0
T6	102177	1301	0	0
T10	25593	12553	0	0
T11	18212	10548	0	0
T12	79294	4965	0	0
T13	82776	529	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16324395	0	0
T1	13602	3701	0	0
T2	11640	3430	0	0
T3	16395	3822	0	0
T4	37444	604	0	0
T5	45136	921	0	0
T6	102177	1301	0	0
T10	25593	12553	0	0
T11	18212	10548	0	0
T12	79294	4965	0	0
T13	82776	529	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16054075	0	0
T4	37444	1351	0	0
T5	45136	2635	0	0
T6	102177	11082	0	0
T7	0	97587	0	0
T8	0	225252	0	0
T10	25593	19784	0	0
T11	18212	10144	0	0
T12	79294	31471	0	0
T13	82776	30269	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T76	0	1262	0	0
T108	18863	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	5745	0	0
T5	45136	1	0	0
T6	102177	2	0	0
T7	365646	5	0	0
T8	0	37	0	0
T10	25593	7	0	0
T11	18212	10	0	0
T12	79294	7	0	0
T13	82776	8	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T68	0	9	0	0
T76	0	1	0	0
T108	18863	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	2717963	0	0
T4	37444	2065	0	0
T5	45136	595	0	0
T6	102177	19128	0	0
T10	25593	0	0	0
T11	18212	0	0	0
T12	79294	10471	0	0
T13	82776	0	0	0
T15	0	30261	0	0
T43	17259	0	0	0
T58	0	8937	0	0
T66	11069	0	0	0
T68	0	24789	0	0
T98	0	26173	0	0
T106	0	9493	0	0
T107	0	17302	0	0
T108	18863	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	30977357	0	0
T4	37444	18579	0	0
T5	45136	32491	0	0
T6	102177	90061	0	0
T10	25593	2631	0	0
T11	18212	0	0	0
T12	79294	61702	0	0
T13	82776	65166	0	0
T43	17259	10520	0	0
T66	11069	2599	0	0
T108	18863	3417	0	0
T177	0	2345	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T108,T163

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T58,T167,T173

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T171,T169
1	Covered	T77,T171,T169

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T5,T11
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T110,T197,T198
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T177,T178,T179
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T10,T5,T12
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T167,T173,T199
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T2,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T10,T5,T12
CheckFailError	317	Covered	T77,T171,T169
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T1,T108,T163
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T10,T8,T9
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T12,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T171,T169
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T108,T163
MacroEccCorrError->NoError	235	Covered	T58,T73,T112
NoError->AccessError	256	Covered	T10,T5,T12
NoError->CheckFailError	317	Covered	T77,T171,T169
NoError->FsmStateError	289	Covered	T2,T3,T11
NoError->MacroEccCorrError	221	Covered	T1,T108,T163

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T108,T163
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T177,T178,T179
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T98,T104
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T5,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T58,T167,T173
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T167,T173,T199
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T76
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T10,T11,T76
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T171,T169
1	0	Covered	T77,T171,T169
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	91088385	90242584	0	0
DigestKnown_A	91088385	90242584	0	0
DigestOffsetMustBeRepresentable_A	1118	1118	0	0
EccErrorState_A	91088385	12385	0	0
ErrorKnown_A	91088385	90242584	0	0
FsmStateKnown_A	91088385	90242584	0	0
InitDoneKnown_A	91088385	90242584	0	0
InitReadLocksPartition_A	91088385	16500058	0	0
InitWriteLocksPartition_A	91088385	16500058	0	0
OffsetMustBeBlockAligned_A	1118	1118	0	0
OtpAddrKnown_A	91088385	90242584	0	0
OtpCmdKnown_A	91088385	90242584	0	0
OtpErrorState_A	91088385	89	0	0
OtpReqKnown_A	91088385	90242584	0	0
OtpSizeKnown_A	91088385	90242584	0	0
OtpWdataKnown_A	91088385	90242584	0	0
ReadLockPropagation_A	91088385	15674051	0	0
SizeMustBeBlockAligned_A	1118	1118	0	0
TlulGntKnown_A	91088385	90242584	0	0
TlulRdataKnown_A	91088385	90242584	0	0
TlulReadOnReadLock_A	91088385	5813	0	0
TlulRerrorKnown_A	91088385	90242584	0	0
TlulRvalidKnown_A	91088385	90242584	0	0
WriteLockPropagation_A	91088385	2992809	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	91088385	31257070	0	0
u_state_regs_A	91088385	90242584	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	12385	0	0
T9	85575	0	0	0
T21	106448	0	0	0
T28	10654	0	0	0
T29	19196	0	0	0
T68	109340	0	0	0
T77	13259	3618	0	0
T109	25684	0	0	0
T110	70624	0	0	0
T166	64149	0	0	0
T169	0	2557	0	0
T171	0	3390	0	0
T172	0	2820	0	0
T180	12353	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16500058	0	0
T1	13602	3735	0	0
T2	11640	3447	0	0
T3	16395	3873	0	0
T4	37444	757	0	0
T5	45136	1159	0	0
T6	102177	1488	0	0
T10	25593	12587	0	0
T11	18212	10599	0	0
T12	79294	5101	0	0
T13	82776	699	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16500058	0	0
T1	13602	3735	0	0
T2	11640	3447	0	0
T3	16395	3873	0	0
T4	37444	757	0	0
T5	45136	1159	0	0
T6	102177	1488	0	0
T10	25593	12587	0	0
T11	18212	10599	0	0
T12	79294	5101	0	0
T13	82776	699	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	89	0	0
T8	464936	0	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T163	9872	0	0	0
T164	17085	1	0	0
T165	12227	0	0	0
T167	0	2	0	0
T177	7983	1	0	0
T178	16167	1	0	0
T179	10365	1	0	0
T180	0	1	0	0
T187	17268	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T191	0	1	0	0
T193	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	15674051	0	0
T4	37444	539	0	0
T5	45136	2455	0	0
T6	102177	14952	0	0
T7	0	104692	0	0
T8	0	236761	0	0
T10	25593	19780	0	0
T11	18212	10142	0	0
T12	79294	31444	0	0
T13	82776	36822	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T68	0	37291	0	0
T108	18863	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	5813	0	0
T5	45136	3	0	0
T6	102177	0	0	0
T7	365646	7	0	0
T8	0	39	0	0
T9	0	12	0	0
T10	25593	5	0	0
T11	18212	8	0	0
T12	79294	4	0	0
T13	82776	12	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T68	0	8	0	0
T76	0	3	0	0
T108	18863	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	2992809	0	0
T5	45136	1282	0	0
T6	102177	19484	0	0
T7	365646	0	0	0
T11	18212	0	0	0
T12	79294	10471	0	0
T13	82776	0	0	0
T15	0	50972	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T68	0	13150	0	0
T98	0	15668	0	0
T99	0	3329	0	0
T103	0	6869	0	0
T104	0	2186	0	0
T105	0	32462	0	0
T108	18863	0	0	0
T177	7983	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	31257070	0	0
T4	37444	18494	0	0
T5	45136	24621	0	0
T6	102177	89891	0	0
T10	25593	2614	0	0
T11	18212	0	0	0
T12	79294	61583	0	0
T13	82776	65030	0	0
T43	17259	10452	0	0
T66	11069	0	0	0
T108	18863	0	0	0
T164	0	3049	0	0
T177	0	2340	0	0
T178	0	3347	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T97,T82,T174

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T73,T175,T81

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T176,T172,T170
1	Covered	T176,T172,T170

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T6,T12
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T10
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T110,T197,T198
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T177,T178,T179
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T12,T13
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T137,T175,T200
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T2,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T12,T13
CheckFailError	317	Covered	T176,T172,T170
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T97,T82,T174
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T98,T143
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T12,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T176,T172,T170
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T97,T82,T174
MacroEccCorrError->NoError	235	Covered	T73,T81,T201
NoError->AccessError	256	Covered	T6,T12,T13
NoError->CheckFailError	317	Covered	T176,T172,T170
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T97,T82,T174

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T97,T82,T174
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T187,T165,T101
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T98,T125
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T12,T13
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T73,T175,T81
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T137,T175,T200
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T11,T76,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T11,T76,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T176,T172,T170
1	0	Covered	T176,T172,T170
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	91088385	90242584	0	0
DigestKnown_A	91088385	90242584	0	0
DigestOffsetMustBeRepresentable_A	1118	1118	0	0
EccErrorState_A	91088385	8996	0	0
ErrorKnown_A	91088385	90242584	0	0
FsmStateKnown_A	91088385	90242584	0	0
InitDoneKnown_A	91088385	90242584	0	0
InitReadLocksPartition_A	91088385	16674532	0	0
InitWriteLocksPartition_A	91088385	16674532	0	0
OffsetMustBeBlockAligned_A	1118	1118	0	0
OtpAddrKnown_A	91088385	90242584	0	0
OtpCmdKnown_A	91088385	90242584	0	0
OtpErrorState_A	91088385	45	0	0
OtpReqKnown_A	91088385	90242584	0	0
OtpSizeKnown_A	91088385	90242584	0	0
OtpWdataKnown_A	91088385	90242584	0	0
ReadLockPropagation_A	91088385	16853850	0	0
SizeMustBeBlockAligned_A	1118	1118	0	0
TlulGntKnown_A	91088385	90242584	0	0
TlulRdataKnown_A	91088385	90242584	0	0
TlulReadOnReadLock_A	91088385	6268	0	0
TlulRerrorKnown_A	91088385	90242584	0	0
TlulRvalidKnown_A	91088385	90242584	0	0
WriteLockPropagation_A	91088385	1512128	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	91088385	20188682	0	0
u_state_regs_A	91088385	90242584	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	8996	0	0
T170	0	2399	0	0
T172	0	2820	0	0
T176	11119	3777	0	0
T202	145750	0	0	0
T203	35656	0	0	0
T204	38859	0	0	0
T205	6137	0	0	0
T206	5228	0	0	0
T207	12429	0	0	0
T208	3885	0	0	0
T209	90981	0	0	0
T210	28265	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16674532	0	0
T1	13602	3769	0	0
T2	11640	3464	0	0
T3	16395	3924	0	0
T4	37444	910	0	0
T5	45136	1397	0	0
T6	102177	1675	0	0
T10	25593	12621	0	0
T11	18212	10650	0	0
T12	79294	5237	0	0
T13	82776	869	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16674532	0	0
T1	13602	3769	0	0
T2	11640	3464	0	0
T3	16395	3924	0	0
T4	37444	910	0	0
T5	45136	1397	0	0
T6	102177	1675	0	0
T10	25593	12621	0	0
T11	18212	10650	0	0
T12	79294	5237	0	0
T13	82776	869	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	45	0	0
T8	464936	0	0	0
T9	85575	0	0	0
T68	109340	0	0	0
T76	17277	0	0	0
T77	13259	0	0	0
T101	0	1	0	0
T137	0	1	0	0
T142	7417	0	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T165	12227	1	0	0
T175	0	1	0	0
T187	17268	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	16853850	0	0
T4	37444	1886	0	0
T5	45136	2857	0	0
T6	102177	10619	0	0
T7	0	127071	0	0
T8	0	217514	0	0
T10	25593	14652	0	0
T11	18212	10140	0	0
T12	79294	28702	0	0
T13	82776	26743	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T76	0	2291	0	0
T108	18863	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118	1118	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	6268	0	0
T6	102177	2	0	0
T7	365646	5	0	0
T8	0	27	0	0
T9	0	27	0	0
T11	18212	8	0	0
T12	79294	13	0	0
T13	82776	5	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T68	0	9	0	0
T76	0	2	0	0
T108	18863	0	0	0
T166	0	20	0	0
T177	7983	0	0	0
T178	16167	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	1512128	0	0
T4	37444	5104	0	0
T5	45136	0	0	0
T6	102177	0	0	0
T10	25593	0	0	0
T11	18212	0	0	0
T12	79294	10471	0	0
T13	82776	0	0	0
T15	0	9834	0	0
T43	17259	0	0	0
T58	0	3842	0	0
T66	11069	0	0	0
T68	0	12255	0	0
T98	0	11558	0	0
T104	0	2186	0	0
T105	0	17421	0	0
T107	0	17934	0	0
T108	18863	0	0	0
T137	0	1406	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	20188682	0	0
T4	37444	27322	0	0
T5	45136	0	0	0
T6	102177	0	0	0
T10	25593	2597	0	0
T11	18212	0	0	0
T12	79294	61464	0	0
T13	82776	0	0	0
T43	17259	0	0	0
T66	11069	0	0	0
T68	0	85712	0	0
T96	0	3082	0	0
T108	18863	0	0	0
T109	0	15982	0	0
T137	0	23372	0	0
T165	0	2685	0	0
T166	0	3109	0	0
T187	0	3900	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91088385	90242584	0	0
T1	13602	13427	0	0
T2	11640	11368	0	0
T3	16395	16147	0	0
T4	37444	36690	0	0
T5	45136	44040	0	0
T6	102177	101355	0	0
T10	25593	25322	0	0
T11	18212	17932	0	0
T12	79294	78617	0	0
T13	82776	82075	0	0