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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_otp_ctrl_dai.PartSelMustBeOnehot_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblBlockWidthGe8_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblCmdKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblDataKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblModeKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblMtxReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblSelKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.ScrmblValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[0].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[10].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[1].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[2].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[3].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[4].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[5].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[6].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[7].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[8].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.gen_part_sel[9].PartEndMax_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckHotOne_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckNGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_dai.u_state_regs_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.NonceWidth_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A	0	0	94449309	35429	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A	0	0	94449309	35429	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A	0	0	94449309	35429	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A	0	0	94449309	29987556	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A	0	0	94449309	63547818	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A	0	0	94449309	35429	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A	0	0	94449309	35429	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A	0	0	94449309	30025266	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M	0	0	94449309	29987556	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A	0	0	94449309	35429	0	0
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_kdi.u_state_regs_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.ErrorKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.LcAckKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.LcErrKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_lci.u_state_regs_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A	0	0	94449309	246516	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A	0	0	94449309	131180	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A	0	0	94449309	260708	0	0
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_rsp_fifo.DataKnown_A	0	0	94449309	15906643	0	0
tb.dut.u_otp_rsp_fifo.DepthKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_rsp_fifo.RvalidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_rsp_fifo.WreadyKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	94449309	15906643	0	0
tb.dut.u_part_sel_idx.CheckHotOne_A	0	0	94449309	93573084	0	0
tb.dut.u_part_sel_idx.CheckNGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_part_sel_idx.GrantKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_part_sel_idx.IdxKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_part_sel_idx.Priority_A	0	0	94449309	93573084	0	0
tb.dut.u_part_sel_idx.ReqImpliesValid_A	0	0	94449309	93573084	0	0
tb.dut.u_part_sel_idx.ValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A	0	0	94449309	42488618	0	0
tb.dut.u_prim_edn_req.DataOutputValid_A	0	0	94449309	225786	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	94449309	452120	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	94449309	452017	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	215975046	452420	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	94449309	225458	0	0
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_reg_core.en2addrHit	0	0	97064673	6731143	0	0
tb.dut.u_reg_core.reAfterRv	0	0	97064673	6731143	0	0
tb.dut.u_reg_core.rePulse	0	0	97064673	5814158	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	97064673	9335805	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	97064673	13661074	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	97064673	1290063	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	97064673	976259	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	97064673	7579405	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	97064673	12684815	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	97064673	96142547	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1296	1296	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1296	1296	0	0
tb.dut.u_reg_core.wePulse	0	0	97064673	916985	0	0
tb.dut.u_scrmbl_mtx.CheckHotOne_A	0	0	94449309	93573084	0	0
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_scrmbl_mtx.GrantKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_scrmbl_mtx.IdxKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A	0	0	94449309	51741124	0	0
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A	0	0	94449309	41831960	0	0
tb.dut.u_scrmbl_mtx.ValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.WeOutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty	0	0	94449309	83687	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull	0	0	94449309	83687	0	0
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A	0	0	94449309	1406737	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	94449309	1406737	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A	0	0	94449309	205563	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	94449309	205563	0	0
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg	0	0	1121	1121	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A	0	0	94449309	550287	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	94449309	550287	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1121	1121	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A	0	0	1121	1121	0	0
tb.dut.u_tlul_lc_gate.u_state_regs_A	0	0	94449309	93573084	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1121	1121	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1121	1121	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_arb.RoundRobin_A	0	0	94449309	0	0	1113
tb.dut.u_otp_arb.RoundRobin_A	0	0	94449309	0	0	1113
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	94449309	0	0	1113
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	94449309	0	0	1113
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	94449309	93532356	0	3339
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	94449309	0	0	1113

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	97065575	428	428	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	97065575	118	118	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	97065575	118	118	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	97065575	66	66	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	97065575	28	28	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	97065575	57	57	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	97065575	53	53	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	97065575	3838	3838	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	97065575	6260	6260	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	97065575	3462538	3462538	1214
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	97065575	336	336	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	97065575	119	119	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	97065575	124	124	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	97065575	87	87	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	97065575	6	6	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	97065575	72	72	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	97065575	94	94	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	97065575	1142	1142	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	97065575	2135	2135	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	97065575	60077	60077	55

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	97065575	428	428	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	97065575	118	118	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	97065575	118	118	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	97065575	66	66	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	97065575	28	28	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	97065575	57	57	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	97065575	53	53	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	97065575	3838	3838	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	97065575	6260	6260	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	97065575	3462538	3462538	1214
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	97065575	336	336	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	97065575	119	119	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	97065575	124	124	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	97065575	87	87	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	97065575	6	6	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	97065575	72	72	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	97065575	94	94	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	97065575	1142	1142	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	97065575	2135	2135	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	97065575	60077	60077	55