Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4528913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2539969

1

T1

244

T2

2

T3

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5951290	1			T1	942		T2	1		T3	302
values[0x0]	527100	1			T1	148		T2	3		T3	8
values[0x1]	590492	1			T1	144		T2	7		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3339307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3729575

1

T1

526

T2

2

T3

138

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75944	1			T1	10		T5	18		T6	37
valid_sources[0x01]	20337	1			T1	8		T5	8		T6	10
valid_sources[0x02]	22433	1			T1	2		T3	1		T5	12
valid_sources[0x03]	26549	1			T1	5		T5	14		T6	12
valid_sources[0x04]	22402	1			T1	3		T3	3		T5	9
valid_sources[0x05]	21632	1			T3	3		T5	20		T6	26
valid_sources[0x06]	23391	1			T1	4		T3	1		T5	20
valid_sources[0x07]	20657	1			T1	2		T5	18		T6	9
valid_sources[0x08]	20977	1			T1	5		T5	4		T6	32
valid_sources[0x09]	35557	1			T1	3		T3	1		T5	15
valid_sources[0x0a]	20110	1			T1	6		T3	2		T5	10
valid_sources[0x0b]	23190	1			T1	9		T3	2		T5	8
valid_sources[0x0c]	25948	1			T1	1		T5	4		T6	7
valid_sources[0x0d]	24084	1			T1	1		T3	3		T5	15
valid_sources[0x0e]	29752	1			T1	2		T3	1		T5	14
valid_sources[0x0f]	20467	1			T1	3		T3	1		T5	1
valid_sources[0x10]	39790	1			T1	2		T3	2		T5	12
valid_sources[0x11]	23403	1			T1	2		T3	1		T5	12
valid_sources[0x12]	40065	1			T1	4		T3	1		T5	8
valid_sources[0x13]	23694	1			T1	7		T3	2		T5	16
valid_sources[0x14]	19862	1			T1	12		T3	1		T5	12
valid_sources[0x15]	22486	1			T1	3		T5	4		T6	24
valid_sources[0x16]	34514	1			T1	4		T3	3		T5	21
valid_sources[0x17]	34770	1			T1	7		T3	5		T5	10
valid_sources[0x18]	19725	1			T1	2		T5	15		T6	19
valid_sources[0x19]	128632	1			T1	7		T3	1		T5	15
valid_sources[0x1a]	21847	1			T1	8		T3	1		T5	5
valid_sources[0x1b]	37454	1			T1	6		T5	15		T6	29
valid_sources[0x1c]	29071	1			T1	2		T3	4		T5	23
valid_sources[0x1d]	33074	1			T1	8		T3	1		T5	16
valid_sources[0x1e]	22979	1			T1	4		T3	2		T5	13
valid_sources[0x1f]	26962	1			T1	7		T3	2		T5	29
valid_sources[0x20]	20165	1			T1	6		T5	7		T6	34
valid_sources[0x21]	27755	1			T1	3		T3	1		T5	9
valid_sources[0x22]	20082	1			T1	5		T3	1		T5	12
valid_sources[0x23]	27820	1			T1	3		T5	7		T6	32
valid_sources[0x24]	24628	1			T1	6		T3	1		T5	16
valid_sources[0x25]	20930	1			T1	5		T3	2		T5	13
valid_sources[0x26]	20499	1			T1	8		T3	1		T5	2
valid_sources[0x27]	19420	1			T1	4		T3	1		T5	18
valid_sources[0x28]	21377	1			T3	3		T5	12		T6	12
valid_sources[0x29]	85276	1			T1	6		T3	1		T5	8
valid_sources[0x2a]	19551	1			T1	5		T3	2		T5	19
valid_sources[0x2b]	39140	1			T1	3		T3	2		T5	8
valid_sources[0x2c]	30940	1			T1	6		T5	10		T6	36
valid_sources[0x2d]	21764	1			T1	6		T5	8		T6	11
valid_sources[0x2e]	20579	1			T1	5		T3	3		T5	12
valid_sources[0x2f]	23997	1			T1	4		T5	13		T6	6
valid_sources[0x30]	31315	1			T1	3		T3	1		T5	13
valid_sources[0x31]	148945	1			T1	7		T3	1		T5	8
valid_sources[0x32]	21789	1			T1	8		T3	1		T5	29
valid_sources[0x33]	21142	1			T1	2		T5	18		T6	26
valid_sources[0x34]	32522	1			T1	5		T3	2		T5	14
valid_sources[0x35]	23313	1			T1	5		T3	1		T5	30
valid_sources[0x36]	27327	1			T1	7		T3	1		T5	18
valid_sources[0x37]	20668	1			T1	5		T5	6		T6	30
valid_sources[0x38]	21044	1			T1	3		T5	6		T6	39
valid_sources[0x39]	32356	1			T1	6		T3	1		T5	32
valid_sources[0x3a]	22522	1			T1	3		T3	2		T4	1019
valid_sources[0x3b]	31866	1			T1	6		T3	1		T5	8
valid_sources[0x3c]	123309	1			T1	7		T3	1		T5	24
valid_sources[0x3d]	24964	1			T1	6		T3	1		T5	18
valid_sources[0x3e]	20242	1			T1	5		T3	1		T5	11
valid_sources[0x3f]	20297	1			T1	4		T5	10		T6	9
valid_sources[0x40]	24719	1			T1	2		T5	5		T6	20
valid_sources[0x41]	23690	1			T1	2		T3	2		T5	16
valid_sources[0x42]	20191	1			T1	6		T3	1		T5	18
valid_sources[0x43]	20289	1			T1	2		T3	1		T5	21
valid_sources[0x44]	21310	1			T1	4		T5	30		T11	15
valid_sources[0x45]	23523	1			T1	7		T3	5		T5	25
valid_sources[0x46]	20268	1			T1	9		T5	8		T6	18
valid_sources[0x47]	21584	1			T1	7		T3	1		T5	21
valid_sources[0x48]	21084	1			T1	8		T5	18		T6	18
valid_sources[0x49]	20128	1			T1	2		T3	1		T5	15
valid_sources[0x4a]	20336	1			T1	6		T3	1		T5	5
valid_sources[0x4b]	21251	1			T1	4		T3	1		T5	5
valid_sources[0x4c]	20121	1			T1	1		T5	7		T6	7
valid_sources[0x4d]	21174	1			T1	2		T3	1		T5	7
valid_sources[0x4e]	33230	1			T1	3		T5	13		T6	2
valid_sources[0x4f]	31087	1			T1	4		T5	10		T6	19
valid_sources[0x50]	20815	1			T1	3		T3	2		T5	11
valid_sources[0x51]	25182	1			T1	9		T3	1		T5	9
valid_sources[0x52]	20131	1			T5	16		T6	6		T11	6
valid_sources[0x53]	37632	1			T1	5		T3	1		T5	3
valid_sources[0x54]	21404	1			T1	5		T3	1		T5	22
valid_sources[0x55]	20956	1			T1	5		T3	2		T5	11
valid_sources[0x56]	38050	1			T1	12		T5	2		T6	5
valid_sources[0x57]	21973	1			T1	12		T3	1		T5	28
valid_sources[0x58]	21160	1			T1	9		T3	2		T5	7
valid_sources[0x59]	27666	1			T1	8		T3	1		T5	10
valid_sources[0x5a]	23884	1			T1	5		T5	10		T6	2
valid_sources[0x5b]	28258	1			T1	12		T5	28		T6	58
valid_sources[0x5c]	31825	1			T1	3		T3	2		T5	6
valid_sources[0x5d]	27941	1			T1	7		T3	1		T5	12
valid_sources[0x5e]	32304	1			T1	5		T5	16		T6	14
valid_sources[0x5f]	29251	1			T1	6		T5	10		T6	39
valid_sources[0x60]	167715	1			T1	6		T3	1		T5	16
valid_sources[0x61]	20781	1			T1	6		T3	2		T5	17
valid_sources[0x62]	21942	1			T1	5		T5	13		T6	17
valid_sources[0x63]	20611	1			T1	4		T3	2		T5	10
valid_sources[0x64]	26753	1			T1	3		T3	1		T5	4
valid_sources[0x65]	24161	1			T1	6		T5	9		T6	16
valid_sources[0x66]	47709	1			T1	6		T5	2		T6	14
valid_sources[0x67]	28691	1			T1	5		T5	4		T6	19
valid_sources[0x68]	32418	1			T1	7		T3	3		T5	6
valid_sources[0x69]	24078	1			T1	3		T3	1		T5	9
valid_sources[0x6a]	20623	1			T1	5		T3	2		T5	16
valid_sources[0x6b]	19913	1			T1	6		T3	4		T5	18
valid_sources[0x6c]	22464	1			T1	4		T3	1		T5	16
valid_sources[0x6d]	20505	1			T1	5		T3	1		T5	15
valid_sources[0x6e]	29517	1			T1	4		T3	2		T5	19
valid_sources[0x6f]	20371	1			T1	9		T3	1		T5	10
valid_sources[0x70]	22856	1			T1	7		T3	2		T5	14
valid_sources[0x71]	33614	1			T1	7		T3	2		T5	28
valid_sources[0x72]	20235	1			T1	4		T3	1		T5	17
valid_sources[0x73]	31923	1			T1	2		T2	11		T3	3
valid_sources[0x74]	23927	1			T1	5		T3	2		T5	5
valid_sources[0x75]	31864	1			T1	8		T3	1		T5	19
valid_sources[0x76]	21653	1			T1	6		T3	1		T5	9
valid_sources[0x77]	25339	1			T1	5		T5	27		T6	19
valid_sources[0x78]	21718	1			T1	4		T3	2		T5	10
valid_sources[0x79]	20804	1			T1	2		T3	1		T5	5
valid_sources[0x7a]	25119	1			T1	4		T3	2		T5	10
valid_sources[0x7b]	22538	1			T1	10		T3	1		T5	13
valid_sources[0x7c]	19484	1			T1	4		T3	1		T5	19
valid_sources[0x7d]	25242	1			T1	8		T3	2		T5	14
valid_sources[0x7e]	21862	1			T1	4		T5	17		T6	6
valid_sources[0x7f]	26704	1			T1	1		T5	17		T6	17
valid_sources[0x80]	27814	1			T1	4		T5	14		T6	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2014569

1

T1

136

T3

53

T4

115

values[0x0]

all_enables

biggest_size

295182

1

T1

61

T2

1

T3

5

values[0x1]

all_enables

biggest_size

230218

1

T1

47

T2

1

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

534693

1

T3

20

T5

80

T6

1555

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	175703	1			T3	10		T5	40		T6	396
values[0x0]	186324	1			T3	5		T5	16		T6	579
values[0x1]	196687	1			T3	5		T5	24		T6	636

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

546071

1

T3

20

T5

80

T6

1583

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2283	1			T6	5		T7	31		T118	2
valid_sources[0x01]	2053	1			T6	5		T7	30		T47	1
valid_sources[0x02]	1907	1			T5	1		T6	5		T7	20
valid_sources[0x03]	2599	1			T6	3		T7	22		T117	3
valid_sources[0x04]	1795	1			T6	6		T11	1		T7	28
valid_sources[0x05]	2402	1			T6	6		T11	1		T7	16
valid_sources[0x06]	1979	1			T3	3		T6	7		T12	1
valid_sources[0x07]	2071	1			T6	6		T7	35		T117	3
valid_sources[0x08]	2225	1			T6	6		T7	16		T47	1
valid_sources[0x09]	2365	1			T6	5		T7	22		T47	1
valid_sources[0x0a]	2238	1			T6	4		T11	2		T7	21
valid_sources[0x0b]	2248	1			T6	12		T12	2		T7	25
valid_sources[0x0c]	2183	1			T6	6		T12	1		T7	27
valid_sources[0x0d]	2209	1			T6	7		T7	28		T40	5
valid_sources[0x0e]	1848	1			T6	8		T7	21		T117	1
valid_sources[0x0f]	1786	1			T6	2		T7	29		T40	1
valid_sources[0x10]	2675	1			T6	10		T7	20		T117	3
valid_sources[0x11]	1848	1			T6	8		T7	26		T110	1
valid_sources[0x12]	2291	1			T5	1		T6	8		T11	1
valid_sources[0x13]	2101	1			T6	5		T7	17		T117	4
valid_sources[0x14]	2150	1			T6	7		T11	1		T12	1
valid_sources[0x15]	2201	1			T5	2		T6	4		T7	16
valid_sources[0x16]	2172	1			T5	1		T6	8		T12	1
valid_sources[0x17]	2224	1			T6	8		T7	28		T117	5
valid_sources[0x18]	2138	1			T6	8		T12	2		T7	19
valid_sources[0x19]	2467	1			T6	14		T12	1		T7	23
valid_sources[0x1a]	2054	1			T5	1		T6	5		T7	31
valid_sources[0x1b]	1927	1			T5	1		T6	8		T12	2
valid_sources[0x1c]	1995	1			T6	4		T7	14		T117	2
valid_sources[0x1d]	2560	1			T3	1		T6	5		T11	1
valid_sources[0x1e]	2085	1			T5	1		T6	9		T28	1
valid_sources[0x1f]	2227	1			T6	4		T12	1		T28	1
valid_sources[0x20]	2367	1			T6	7		T7	25		T112	6
valid_sources[0x21]	2315	1			T6	8		T7	23		T117	1
valid_sources[0x22]	2140	1			T5	1		T6	7		T7	18
valid_sources[0x23]	2240	1			T5	1		T6	12		T11	1
valid_sources[0x24]	2070	1			T6	3		T28	1		T7	23
valid_sources[0x25]	2722	1			T6	5		T12	1		T7	27
valid_sources[0x26]	2084	1			T6	5		T12	1		T7	24
valid_sources[0x27]	2322	1			T6	2		T7	20		T71	7
valid_sources[0x28]	2141	1			T6	3		T12	3		T7	22
valid_sources[0x29]	2341	1			T6	6		T7	17		T47	1
valid_sources[0x2a]	2506	1			T5	3		T6	5		T11	3
valid_sources[0x2b]	2125	1			T6	8		T11	1		T12	1
valid_sources[0x2c]	1976	1			T6	8		T7	33		T71	8
valid_sources[0x2d]	2166	1			T6	4		T11	1		T12	1
valid_sources[0x2e]	1791	1			T6	13		T11	1		T7	21
valid_sources[0x2f]	2194	1			T5	4		T6	9		T11	3
valid_sources[0x30]	1894	1			T6	5		T7	23		T118	2
valid_sources[0x31]	3422	1			T6	3		T7	25		T27	1
valid_sources[0x32]	2364	1			T5	5		T6	10		T7	31
valid_sources[0x33]	1985	1			T5	1		T6	9		T7	21
valid_sources[0x34]	2017	1			T6	6		T7	18		T117	2
valid_sources[0x35]	2120	1			T5	2		T6	5		T11	2
valid_sources[0x36]	1844	1			T6	6		T7	22		T71	3
valid_sources[0x37]	1967	1			T5	2		T6	4		T11	1
valid_sources[0x38]	1892	1			T6	8		T7	18		T117	1
valid_sources[0x39]	2945	1			T6	6		T12	1		T7	31
valid_sources[0x3a]	2364	1			T6	5		T7	29		T117	3
valid_sources[0x3b]	1807	1			T6	8		T11	2		T12	2
valid_sources[0x3c]	1848	1			T6	9		T11	1		T7	22
valid_sources[0x3d]	2186	1			T6	9		T11	1		T12	1
valid_sources[0x3e]	2189	1			T6	9		T12	1		T7	33
valid_sources[0x3f]	2306	1			T6	6		T12	2		T7	30
valid_sources[0x40]	1909	1			T6	7		T28	2		T7	32
valid_sources[0x41]	2102	1			T6	11		T12	1		T7	24
valid_sources[0x42]	1968	1			T5	1		T6	5		T12	1
valid_sources[0x43]	2441	1			T5	5		T6	4		T11	1
valid_sources[0x44]	1810	1			T6	4		T7	25		T117	1
valid_sources[0x45]	2025	1			T6	9		T7	22		T117	1
valid_sources[0x46]	2006	1			T6	5		T7	17		T118	1
valid_sources[0x47]	2277	1			T6	5		T11	1		T28	2
valid_sources[0x48]	2073	1			T6	3		T7	22		T47	3
valid_sources[0x49]	2683	1			T6	8		T7	26		T117	2
valid_sources[0x4a]	2074	1			T6	7		T11	4		T7	27
valid_sources[0x4b]	1786	1			T6	3		T7	36		T27	2
valid_sources[0x4c]	1906	1			T5	1		T6	6		T7	25
valid_sources[0x4d]	2130	1			T5	3		T6	8		T7	19
valid_sources[0x4e]	2266	1			T5	1		T6	18		T12	3
valid_sources[0x4f]	1872	1			T6	8		T7	21		T71	1
valid_sources[0x50]	2263	1			T6	7		T7	29		T118	3
valid_sources[0x51]	1962	1			T6	4		T11	1		T7	31
valid_sources[0x52]	1993	1			T6	2		T7	21		T40	1
valid_sources[0x53]	1952	1			T6	4		T7	29		T71	2
valid_sources[0x54]	1765	1			T6	5		T11	2		T7	34
valid_sources[0x55]	2280	1			T6	10		T11	6		T12	1
valid_sources[0x56]	2211	1			T6	9		T7	20		T27	1
valid_sources[0x57]	2277	1			T6	3		T11	1		T7	17
valid_sources[0x58]	2354	1			T6	4		T11	1		T7	24
valid_sources[0x59]	1912	1			T6	10		T7	27		T118	1
valid_sources[0x5a]	2344	1			T5	1		T6	7		T12	3
valid_sources[0x5b]	1869	1			T6	4		T12	1		T7	20
valid_sources[0x5c]	2469	1			T5	1		T6	4		T7	19
valid_sources[0x5d]	1891	1			T6	7		T11	2		T7	27
valid_sources[0x5e]	1870	1			T5	1		T6	7		T7	16
valid_sources[0x5f]	2274	1			T6	6		T12	1		T28	2
valid_sources[0x60]	2561	1			T6	7		T7	14		T117	3
valid_sources[0x61]	2184	1			T6	13		T12	1		T7	28
valid_sources[0x62]	2010	1			T6	8		T11	1		T7	23
valid_sources[0x63]	2086	1			T6	12		T11	1		T12	1
valid_sources[0x64]	3809	1			T6	7		T28	2		T7	38
valid_sources[0x65]	2186	1			T5	2		T6	3		T7	16
valid_sources[0x66]	1913	1			T6	8		T12	3		T7	23
valid_sources[0x67]	1943	1			T6	5		T7	27		T71	2
valid_sources[0x68]	2322	1			T5	2		T6	8		T11	2
valid_sources[0x69]	1817	1			T6	5		T7	17		T71	4
valid_sources[0x6a]	2237	1			T5	1		T6	7		T12	1
valid_sources[0x6b]	2325	1			T6	4		T11	2		T28	1
valid_sources[0x6c]	1909	1			T6	4		T7	28		T27	3
valid_sources[0x6d]	1859	1			T6	6		T11	3		T12	1
valid_sources[0x6e]	2317	1			T6	8		T7	24		T27	1
valid_sources[0x6f]	2222	1			T6	4		T12	1		T7	21
valid_sources[0x70]	2099	1			T6	3		T7	22		T117	1
valid_sources[0x71]	2135	1			T6	9		T11	1		T28	1
valid_sources[0x72]	2357	1			T6	8		T7	20		T118	3
valid_sources[0x73]	2153	1			T6	4		T12	1		T7	33
valid_sources[0x74]	1817	1			T6	9		T11	2		T7	27
valid_sources[0x75]	1964	1			T6	3		T7	28		T40	2
valid_sources[0x76]	3774	1			T6	7		T11	3		T7	28
valid_sources[0x77]	2144	1			T6	1		T7	28		T71	2
valid_sources[0x78]	2979	1			T6	6		T12	3		T7	34
valid_sources[0x79]	2541	1			T6	15		T7	26		T117	1
valid_sources[0x7a]	1884	1			T5	1		T6	4		T7	27
valid_sources[0x7b]	2423	1			T6	10		T11	2		T28	3
valid_sources[0x7c]	2035	1			T5	2		T6	3		T28	1
valid_sources[0x7d]	2116	1			T5	1		T6	6		T11	2
valid_sources[0x7e]	2244	1			T6	5		T7	27		T119	2
valid_sources[0x7f]	1926	1			T6	8		T12	1		T7	24
valid_sources[0x80]	2033	1			T6	2		T12	2		T7	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

164693

1

T3

10

T5

40

T6

379

values[0x0]

all_enables

biggest_size

184968

1

T3

5

T5

16

T6

577

values[0x1]

all_enables

biggest_size

185032

1

T3

5

T5

24

T6

599