Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T4,T6
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78
1	Covered	T78

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T1,T4,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T12
1	1	Covered	T1,T4,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T5
ReadWaitSt	252	Covered	T1,T4,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T10
IdleSt->ReadSt	236	Covered	T1,T4,T5
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T110,T8,T175
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T4,T6
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T4,T6
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T78
FsmStateError	289	Covered	T1,T4,T10
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T146,T70,T38
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T78
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T4,T10
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T78
NoError->FsmStateError	289	Covered	T1,T4,T10
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T26,T27,T104
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78
1	0	Covered	T78
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T10
1	0	Covered	T1,T4,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	94449309	93573084	0	0
DigestKnown_A	94449309	93573084	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	94449309	2199	0	0
ErrorKnown_A	94449309	93573084	0	0
FsmStateKnown_A	94449309	93573084	0	0
InitDoneKnown_A	94449309	93573084	0	0
InitReadLocksPartition_A	94449309	16397969	0	0
InitWriteLocksPartition_A	94449309	16397969	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	94449309	93573084	0	0
OtpCmdKnown_A	94449309	93573084	0	0
OtpErrorState_A	94449309	0	0	0
OtpReqKnown_A	94449309	93573084	0	0
OtpSizeKnown_A	94449309	93573084	0	0
OtpWdataKnown_A	94449309	93573084	0	0
ReadLockPropagation_A	94449309	18146709	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	94449309	93573084	0	0
TlulRdataKnown_A	94449309	93573084	0	0
TlulReadOnReadLock_A	94449309	6164	0	0
TlulRerrorKnown_A	94449309	93573084	0	0
TlulRvalidKnown_A	94449309	93573084	0	0
WriteLockPropagation_A	94449309	2723139	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	94449309	31832252	0	0
u_state_regs_A	94449309	93573084	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	2199	0	0
T78	14230	2199	0	0
T143	636928	0	0	0
T153	4750	0	0	0
T154	47890	0	0	0
T155	12559	0	0	0
T156	10765	0	0	0
T157	22654	0	0	0
T158	51429	0	0	0
T159	33616	0	0	0
T160	72843	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16397969	0	0
T1	10588	4251	0	0
T2	3556	42	0	0
T3	10486	348	0	0
T4	9793	3206	0	0
T5	53718	1011	0	0
T6	79384	507	0	0
T9	7620	90	0	0
T10	10700	3968	0	0
T11	93479	3509	0	0
T12	20957	13134	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16397969	0	0
T1	10588	4251	0	0
T2	3556	42	0	0
T3	10486	348	0	0
T4	9793	3206	0	0
T5	53718	1011	0	0
T6	79384	507	0	0
T9	7620	90	0	0
T10	10700	3968	0	0
T11	93479	3509	0	0
T12	20957	13134	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	18146709	0	0
T5	53718	29921	0	0
T6	79384	34857	0	0
T7	158618	139042	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	3322	0	0
T12	20957	0	0	0
T26	0	3929	0	0
T27	0	4911	0	0
T28	24798	0	0	0
T47	0	4121	0	0
T71	160353	0	0	0
T72	16431	0	0	0
T110	0	1438	0	0
T117	0	7714	0	0
T118	0	3341	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	6164	0	0
T5	53718	5	0	0
T6	79384	2	0	0
T7	158618	11	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	0	0	0
T12	20957	12	0	0
T20	0	8	0	0
T26	0	7	0	0
T28	24798	0	0	0
T47	0	7	0	0
T71	160353	4	0	0
T72	16431	0	0	0
T117	0	6	0	0
T119	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	2723139	0	0
T7	158618	0	0	0
T8	0	3044	0	0
T11	93479	12754	0	0
T12	20957	0	0	0
T20	102358	0	0	0
T26	50215	0	0	0
T28	24798	0	0	0
T40	0	2602	0	0
T71	160353	0	0	0
T72	16431	0	0	0
T104	0	2781	0	0
T105	0	21646	0	0
T106	0	85353	0	0
T107	0	738	0	0
T113	0	3259	0	0
T117	14998	0	0	0
T124	0	2303	0	0
T131	4407	0	0	0
T135	0	4609	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	31832252	0	0
T4	9793	2142	0	0
T5	53718	39817	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T9	7620	0	0	0
T10	10700	2980	0	0
T11	93479	77787	0	0
T12	20957	0	0	0
T26	0	41896	0	0
T27	0	68688	0	0
T28	24798	0	0	0
T40	0	63866	0	0
T71	0	127494	0	0
T72	16431	3392	0	0
T110	0	2699	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T72,T142

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T47,T40,T106

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T141
1	Covered	T77,T141

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T1,T12,T72

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T12
1	1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T4,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T5
ReadWaitSt	252	Covered	T1,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T12,T72
IdleSt->ReadSt	236	Covered	T1,T4,T5
InitSt->ErrorSt	315	Covered	T110,T8,T175
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T4,T10,T161
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T4,T5
ReadWaitSt->ErrorSt	276	Covered	T169,T176,T177
ReadWaitSt->IdleSt	270	Covered	T1,T4,T5
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T77,T141
FsmStateError	289	Covered	T1,T12,T72
MacroEccCorrError	221	Covered	T1,T72,T47
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T38,T114,T116
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T141
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T12,T72
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T72,T142
MacroEccCorrError->NoError	235	Covered	T47,T40,T106
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T77,T141
NoError->FsmStateError	289	Covered	T12,T71,T117
NoError->MacroEccCorrError	221	Covered	T1,T72,T47

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T72,T142
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T10,T161
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T26,T104,T107
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T47,T40,T106
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T169,T176,T177
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T141
1	0	Covered	T77,T141
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T12,T72
1	0	Covered	T1,T4,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	94449309	93573084	0	0
DigestKnown_A	94449309	93573084	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	94449309	6722	0	0
ErrorKnown_A	94449309	93573084	0	0
FsmStateKnown_A	94449309	93573084	0	0
InitDoneKnown_A	94449309	93573084	0	0
InitReadLocksPartition_A	94449309	16580978	0	0
InitWriteLocksPartition_A	94449309	16580978	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	94449309	93573084	0	0
OtpCmdKnown_A	94449309	93573084	0	0
OtpErrorState_A	94449309	64	0	0
OtpReqKnown_A	94449309	93573084	0	0
OtpSizeKnown_A	94449309	93573084	0	0
OtpWdataKnown_A	94449309	93573084	0	0
ReadLockPropagation_A	94449309	17363114	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	94449309	93573084	0	0
TlulRdataKnown_A	94449309	93573084	0	0
TlulReadOnReadLock_A	94449309	6463	0	0
TlulRerrorKnown_A	94449309	93573084	0	0
TlulRvalidKnown_A	94449309	93573084	0	0
WriteLockPropagation_A	94449309	3152833	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	94449309	32237695	0	0
u_state_regs_A	94449309	93573084	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	6722	0	0
T14	77070	0	0	0
T77	12285	3237	0	0
T82	11550	0	0	0
T140	14623	0	0	0
T141	0	3485	0	0
T147	14044	0	0	0
T148	9553	0	0	0
T149	10504	0	0	0
T150	57194	0	0	0
T151	23481	0	0	0
T152	15236	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16580978	0	0
T1	10588	4285	0	0
T2	3556	59	0	0
T3	10486	399	0	0
T4	9793	3247	0	0
T5	53718	1130	0	0
T6	79384	609	0	0
T9	7620	107	0	0
T10	10700	4009	0	0
T11	93479	3730	0	0
T12	20957	13185	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16580978	0	0
T1	10588	4285	0	0
T2	3556	59	0	0
T3	10486	399	0	0
T4	9793	3247	0	0
T5	53718	1130	0	0
T6	79384	609	0	0
T9	7620	107	0	0
T10	10700	4009	0	0
T11	93479	3730	0	0
T12	20957	13185	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	64	0	0
T4	9793	1	0	0
T5	53718	0	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T9	7620	0	0	0
T10	10700	1	0	0
T11	93479	0	0	0
T12	20957	0	0	0
T28	24798	0	0	0
T72	16431	0	0	0
T156	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	17363114	0	0
T5	53718	12635	0	0
T6	79384	34046	0	0
T7	158618	135415	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	3567	0	0
T12	20957	0	0	0
T26	0	3766	0	0
T27	0	8477	0	0
T28	24798	0	0	0
T47	0	11939	0	0
T71	160353	0	0	0
T72	16431	0	0	0
T110	0	2017	0	0
T117	0	7712	0	0
T118	0	3339	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	6463	0	0
T5	53718	2	0	0
T6	79384	3	0	0
T7	158618	14	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	0	0	0
T12	20957	10	0	0
T20	0	56	0	0
T26	0	8	0	0
T28	24798	0	0	0
T47	0	6	0	0
T71	160353	11	0	0
T72	16431	0	0	0
T117	0	2	0	0
T119	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	3152833	0	0
T7	158618	0	0	0
T8	0	22612	0	0
T11	93479	20024	0	0
T12	20957	0	0	0
T20	102358	0	0	0
T26	50215	3278	0	0
T27	0	10580	0	0
T28	24798	0	0	0
T71	160353	10149	0	0
T72	16431	0	0	0
T104	0	5999	0	0
T105	0	6849	0	0
T106	0	89859	0	0
T108	0	53114	0	0
T113	0	2987	0	0
T117	14998	0	0	0
T131	4407	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	32237695	0	0
T4	9793	2137	0	0
T5	53718	39715	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T9	7620	0	0	0
T10	10700	2975	0	0
T11	93479	77600	0	0
T12	20957	0	0	0
T26	0	41692	0	0
T27	0	68416	0	0
T28	24798	0	0	0
T40	0	63679	0	0
T71	0	127847	0	0
T72	16431	0	0	0
T110	0	2682	0	0
T112	0	3053	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T111,T140,T49

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T71,T47,T40

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77
1	Covered	T77

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T1,T4,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T12
1	1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T71

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T71

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T5
ReadWaitSt	252	Covered	T1,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T12,T72
IdleSt->ReadSt	236	Covered	T1,T4,T5
InitSt->ErrorSt	315	Covered	T110,T8,T175
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T4,T10,T120
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T4,T5
ReadWaitSt->ErrorSt	276	Covered	T71,T143,T144
ReadWaitSt->IdleSt	270	Covered	T1,T4,T5
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Covered	T77
FsmStateError	289	Covered	T1,T4,T10
MacroEccCorrError	221	Covered	T71,T47,T40
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T70,T38
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T111,T140
MacroEccCorrError->NoError	235	Covered	T47,T40,T106
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Covered	T77
NoError->FsmStateError	289	Covered	T1,T4,T10
NoError->MacroEccCorrError	221	Covered	T71,T47,T40

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T71
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T111,T140,T49
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T120,T148,T152
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T26,T27,T104
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T71,T47,T40
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T71,T143,T144
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77
1	0	Covered	T77
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T10
1	0	Covered	T1,T4,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	94449309	93573084	0	0
DigestKnown_A	94449309	93573084	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	94449309	3237	0	0
ErrorKnown_A	94449309	93573084	0	0
FsmStateKnown_A	94449309	93573084	0	0
InitDoneKnown_A	94449309	93573084	0	0
InitReadLocksPartition_A	94449309	16762869	0	0
InitWriteLocksPartition_A	94449309	16762869	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	94449309	93573084	0	0
OtpCmdKnown_A	94449309	93573084	0	0
OtpErrorState_A	94449309	55	0	0
OtpReqKnown_A	94449309	93573084	0	0
OtpSizeKnown_A	94449309	93573084	0	0
OtpWdataKnown_A	94449309	93573084	0	0
ReadLockPropagation_A	94449309	17716901	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	94449309	93573084	0	0
TlulRdataKnown_A	94449309	93573084	0	0
TlulReadOnReadLock_A	94449309	6652	0	0
TlulRerrorKnown_A	94449309	93573084	0	0
TlulRvalidKnown_A	94449309	93573084	0	0
WriteLockPropagation_A	94449309	1842673	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	94449309	21363303	0	0
u_state_regs_A	94449309	93573084	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	3237	0	0
T14	77070	0	0	0
T77	12285	3237	0	0
T82	11550	0	0	0
T140	14623	0	0	0
T147	14044	0	0	0
T148	9553	0	0	0
T149	10504	0	0	0
T150	57194	0	0	0
T151	23481	0	0	0
T152	15236	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16762869	0	0
T1	10588	4319	0	0
T2	3556	76	0	0
T3	10486	450	0	0
T4	9793	3281	0	0
T5	53718	1249	0	0
T6	79384	711	0	0
T9	7620	124	0	0
T10	10700	4043	0	0
T11	93479	3951	0	0
T12	20957	13236	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16762869	0	0
T1	10588	4319	0	0
T2	3556	76	0	0
T3	10486	450	0	0
T4	9793	3281	0	0
T5	53718	1249	0	0
T6	79384	711	0	0
T9	7620	124	0	0
T10	10700	4043	0	0
T11	93479	3951	0	0
T12	20957	13236	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	55	0	0
T20	102358	0	0	0
T26	50215	0	0	0
T27	80997	0	0	0
T47	68433	0	0	0
T71	160353	1	0	0
T117	14998	0	0	0
T118	14814	0	0	0
T119	9625	0	0	0
T120	9642	1	0	0
T131	4407	0	0	0
T143	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0
T155	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	17716901	0	0
T5	53718	13452	0	0
T6	79384	34846	0	0
T7	158618	136283	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	1987	0	0
T12	20957	0	0	0
T26	0	2625	0	0
T27	0	8679	0	0
T28	24798	0	0	0
T47	0	10718	0	0
T71	160353	8348	0	0
T72	16431	0	0	0
T117	0	7710	0	0
T118	0	3337	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	6652	0	0
T5	53718	3	0	0
T6	79384	3	0	0
T7	158618	13	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	0	0	0
T12	20957	14	0	0
T20	0	105	0	0
T26	0	1	0	0
T28	24798	0	0	0
T47	0	9	0	0
T71	160353	8	0	0
T72	16431	0	0	0
T117	0	4	0	0
T119	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	1842673	0	0
T5	53718	8715	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T8	0	7189	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	12919	0	0
T12	20957	0	0	0
T28	24798	0	0	0
T40	0	11866	0	0
T71	160353	0	0	0
T72	16431	0	0	0
T105	0	20308	0	0
T107	0	3804	0	0
T108	0	33783	0	0
T109	0	1241	0	0
T113	0	3610	0	0
T114	0	4730	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	21363303	0	0
T5	53718	39613	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T8	0	77224	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	77413	0	0
T12	20957	0	0	0
T26	0	41488	0	0
T28	24798	0	0	0
T40	0	63492	0	0
T71	160353	127837	0	0
T72	16431	0	0	0
T110	0	2665	0	0
T113	0	81768	0	0
T117	0	3367	0	0
T120	0	2334	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0