Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.12	96.70	93.94		83.33	95.45	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.27	97.83	93.94	98.55	83.33	94.74	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T82,T140,T79

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T71,T47,T40

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T141
1	Covered	T78,T141

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T1,T4,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T12
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T71

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T71

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T12,T72
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T4,T10,T110
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T120,T111,T142
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T11,T7
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T178,T179,T180
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T11,T7
CheckFailError	317	Covered	T78,T141
FsmStateError	289	Covered	T1,T4,T10
MacroEccCorrError	221	Covered	T71,T47,T40
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T145,T38
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T11,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T141
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T82,T140
MacroEccCorrError->NoError	235	Covered	T47,T40,T106
NoError->AccessError	256	Covered	T5,T11,T7
NoError->CheckFailError	317	Covered	T78,T141
NoError->FsmStateError	289	Covered	T1,T4,T10
NoError->MacroEccCorrError	221	Covered	T71,T47,T40

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T71
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T82,T140,T79
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T111,T142,T181
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T26,T27,T104
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T11,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T71,T47,T40
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T178,T179,T180
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T141
1	0	Covered	T78,T141
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T10
1	0	Covered	T1,T4,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	94449309	93573084	0	0
DigestKnown_A	94449309	93573084	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	94449309	5684	0	0
ErrorKnown_A	94449309	93573084	0	0
FsmStateKnown_A	94449309	93573084	0	0
InitDoneKnown_A	94449309	93573084	0	0
InitReadLocksPartition_A	94449309	16943950	0	0
InitWriteLocksPartition_A	94449309	16943950	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	94449309	93573084	0	0
OtpCmdKnown_A	94449309	93573084	0	0
OtpErrorState_A	94449309	35	0	0
OtpReqKnown_A	94449309	93573084	0	0
OtpSizeKnown_A	94449309	93573084	0	0
OtpWdataKnown_A	94449309	93573084	0	0
ReadLockPropagation_A	94449309	17847721	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	94449309	93573084	0	0
TlulRdataKnown_A	94449309	93573084	0	0
TlulReadOnReadLock_A	94449309	6451	0	0
TlulRerrorKnown_A	94449309	93573084	0	0
TlulRvalidKnown_A	94449309	93573084	0	0
WriteLockPropagation_A	94449309	3118230	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	94449309	31720252	0	0
u_state_regs_A	94449309	93573084	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	5684	0	0
T78	14230	2199	0	0
T141	0	3485	0	0
T143	636928	0	0	0
T153	4750	0	0	0
T154	47890	0	0	0
T155	12559	0	0	0
T156	10765	0	0	0
T157	22654	0	0	0
T158	51429	0	0	0
T159	33616	0	0	0
T160	72843	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16943950	0	0
T1	10588	4353	0	0
T2	3556	93	0	0
T3	10486	501	0	0
T4	9793	3315	0	0
T5	53718	1368	0	0
T6	79384	813	0	0
T9	7620	141	0	0
T10	10700	4077	0	0
T11	93479	4172	0	0
T12	20957	13287	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	16943950	0	0
T1	10588	4353	0	0
T2	3556	93	0	0
T3	10486	501	0	0
T4	9793	3315	0	0
T5	53718	1368	0	0
T6	79384	813	0	0
T9	7620	141	0	0
T10	10700	4077	0	0
T11	93479	4172	0	0
T12	20957	13287	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	35	0	0
T8	285572	0	0	0
T53	14734	0	0	0
T67	16597	0	0	0
T104	61611	0	0	0
T105	117085	0	0	0
T111	9996	1	0	0
T112	66682	0	0	0
T113	98927	0	0	0
T142	15326	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	12126	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	17847721	0	0
T5	53718	21039	0	0
T6	79384	34842	0	0
T7	158618	135253	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	5875	0	0
T12	20957	0	0	0
T26	0	4172	0	0
T27	0	7533	0	0
T28	24798	0	0	0
T47	0	9830	0	0
T71	160353	8337	0	0
T72	16431	0	0	0
T110	0	3163	0	0
T117	0	7708	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	6451	0	0
T5	53718	1	0	0
T6	79384	0	0	0
T7	158618	8	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	1	0	0
T12	20957	9	0	0
T20	0	69	0	0
T26	0	3	0	0
T28	24798	0	0	0
T71	160353	10	0	0
T72	16431	0	0	0
T117	0	7	0	0
T118	0	6	0	0
T119	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	3118230	0	0
T5	53718	8715	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T8	0	3156	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	6307	0	0
T12	20957	0	0	0
T26	0	3278	0	0
T27	0	5908	0	0
T28	24798	0	0	0
T40	0	4901	0	0
T71	160353	10149	0	0
T72	16431	0	0	0
T104	0	6048	0	0
T105	0	13242	0	0
T113	0	6666	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	31720252	0	0
T5	53718	39511	0	0
T6	79384	0	0	0
T7	158618	0	0	0
T8	0	122617	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	32595	0	0
T12	20957	0	0	0
T26	0	41284	0	0
T27	0	67872	0	0
T28	24798	0	0	0
T40	0	63305	0	0
T71	160353	127469	0	0
T72	16431	0	0	0
T104	0	50813	0	0
T110	0	2648	0	0
T111	0	2016	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	88	96.70
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	65	95.59
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	31	93.94
Logical	33	31	93.94
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T128,T129

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T71,T47,T40

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T10
1	Covered	T1,T4,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T12
1	1	Covered	T1,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T4,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T72,T27,T112

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T72,T27,T112

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T4,T5
ReadWaitSt	252	Covered	T1,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T12,T71
IdleSt->ReadSt	236	Covered	T1,T4,T5
InitSt->ErrorSt	315	Covered	T4,T10,T120
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T72,T111,T142
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T6,T7
ReadSt->ReadWaitSt	252	Covered	T1,T4,T5
ReadWaitSt->ErrorSt	276	Covered	T180,T187,T188
ReadWaitSt->IdleSt	270	Covered	T1,T4,T5
ResetSt->ErrorSt	315	Covered	T76,T77,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	8	72.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T6,T7
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T1,T4,T10
MacroEccCorrError	221	Covered	T71,T47,T40
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T117,T145,T38
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T169,T178
MacroEccCorrError->NoError	235	Covered	T47,T40,T135
NoError->AccessError	256	Covered	T5,T6,T7
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T1,T4,T10
NoError->MacroEccCorrError	221	Covered	T71,T47,T40

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	42	95.45
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T72,T27,T112
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T35,T128,T129
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T72,T140,T174
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T26,T27,T104
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T71,T47,T40
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T180,T187,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T71,T117
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T10
1	0	Covered	T1,T4,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	94449309	93573084	0	0
DigestKnown_A	94449309	93573084	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	94449309	0	0	0
ErrorKnown_A	94449309	93573084	0	0
FsmStateKnown_A	94449309	93573084	0	0
InitDoneKnown_A	94449309	93573084	0	0
InitReadLocksPartition_A	94449309	17124337	0	0
InitWriteLocksPartition_A	94449309	17124337	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	94449309	93573084	0	0
OtpCmdKnown_A	94449309	93573084	0	0
OtpErrorState_A	94449309	36	0	0
OtpReqKnown_A	94449309	93573084	0	0
OtpSizeKnown_A	94449309	93573084	0	0
OtpWdataKnown_A	94449309	93573084	0	0
ReadLockPropagation_A	94449309	17673123	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	94449309	93573084	0	0
TlulRdataKnown_A	94449309	93573084	0	0
TlulReadOnReadLock_A	94449309	6424	0	0
TlulRerrorKnown_A	94449309	93573084	0	0
TlulRvalidKnown_A	94449309	93573084	0	0
WriteLockPropagation_A	94449309	1030932	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	94449309	12003124	0	0
u_state_regs_A	94449309	93573084	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	17124337	0	0
T1	10588	4387	0	0
T2	3556	110	0	0
T3	10486	552	0	0
T4	9793	3349	0	0
T5	53718	1487	0	0
T6	79384	915	0	0
T9	7620	158	0	0
T10	10700	4111	0	0
T11	93479	4393	0	0
T12	20957	13338	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	17124337	0	0
T1	10588	4387	0	0
T2	3556	110	0	0
T3	10486	552	0	0
T4	9793	3349	0	0
T5	53718	1487	0	0
T6	79384	915	0	0
T9	7620	158	0	0
T10	10700	4111	0	0
T11	93479	4393	0	0
T12	20957	13338	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	36	0	0
T20	102358	0	0	0
T26	50215	0	0	0
T47	68433	0	0	0
T71	160353	0	0	0
T72	16431	1	0	0
T117	14998	0	0	0
T118	14814	0	0	0
T119	9625	0	0	0
T120	9642	0	0	0
T131	4407	0	0	0
T140	0	1	0	0
T174	0	1	0	0
T180	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	17673123	0	0
T5	53718	18206	0	0
T6	79384	34833	0	0
T7	158618	138028	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	2042	0	0
T12	20957	0	0	0
T26	0	4893	0	0
T27	0	8509	0	0
T28	24798	0	0	0
T47	0	5713	0	0
T71	160353	8334	0	0
T72	16431	0	0	0
T110	0	3161	0	0
T117	0	7706	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	6424	0	0
T5	53718	4	0	0
T6	79384	1	0	0
T7	158618	12	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	0	0	0
T12	20957	18	0	0
T20	0	6	0	0
T26	0	7	0	0
T28	24798	0	0	0
T71	160353	10	0	0
T72	16431	0	0	0
T117	0	5	0	0
T118	0	3	0	0
T119	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	1030932	0	0
T8	285572	3294	0	0
T27	80997	3675	0	0
T29	0	6041	0	0
T40	71998	0	0	0
T53	14734	0	0	0
T67	16597	0	0	0
T70	0	110821	0	0
T104	61611	0	0	0
T109	0	2476	0	0
T110	19802	0	0	0
T111	9996	0	0	0
T112	66682	0	0	0
T113	98927	0	0	0
T116	0	6134	0	0
T126	0	4106	0	0
T172	0	13548	0	0
T173	0	7897	0	0
T195	0	4410	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	12003124	0	0
T8	0	45529	0	0
T20	102358	0	0	0
T26	50215	0	0	0
T27	0	67600	0	0
T47	68433	0	0	0
T71	160353	0	0	0
T72	16431	3336	0	0
T104	0	50575	0	0
T112	0	2951	0	0
T117	14998	0	0	0
T118	14814	0	0	0
T119	9625	0	0	0
T120	9642	0	0	0
T124	0	51931	0	0
T131	4407	0	0	0
T140	0	3932	0	0
T145	0	2501	0	0
T174	0	2437	0	0
T196	0	15508	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94449309	93573084	0	0
T1	10588	10323	0	0
T2	3556	3496	0	0
T3	10486	10260	0	0
T4	9793	9493	0	0
T5	53718	53095	0	0
T6	79384	79295	0	0
T9	7620	7562	0	0
T10	10700	10432	0	0
T11	93479	92623	0	0
T12	20957	20664	0	0