Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5405712

1

T1

512

T2

35966

T3

4497

full_word

2586076

1

T1

231

T2

16864

T3

580

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7991498	1			T1	743		T2	52830		T3	5077
auto[TlIntgErrCmd]	107	1			T272	4		T273	9		T340	2
auto[TlIntgErrData]	82	1			T271	4		T272	3		T273	3
auto[TlIntgErrBoth]	101	1			T271	6		T272	3		T273	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5897963

1

T1

470

T2

47673

T3

4756

auto[1]

2093825

1

T1

273

T2

5157

T3

321

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3911032	1			T1	353		T2	32647		T3	4328
auto[TlIntgErrNone]	partial	auto[1]	1494418	1			T1	159		T2	3319		T3	169
auto[TlIntgErrNone]	full_word	auto[0]	1986799	1			T1	117		T2	15026		T3	428
auto[TlIntgErrNone]	full_word	auto[1]	599249	1			T1	114		T2	1838		T3	152
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T272	1		T273	4		T340	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T272	3		T273	5		T340	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T339	1		T278	1		T344	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T343	1		T342	1		T339	1
auto[TlIntgErrData]	partial	auto[0]	31	1			T271	1		T272	2		T340	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T271	3		T272	1		T273	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T338	1		T343	1		T345	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T340	1		T343	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T271	1		T272	2		T273	5
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T271	5		T272	1		T273	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T341	1		T277	1		T346	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T273	1		T338	1		T343	1