Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	93094658	329955	0	0
check_regwen_rd_A	93094658	1698	0	0
check_timeout_rd_A	93094658	1045	0	0
check_trigger_regwen_rd_A	93094658	1809	0	0
consistency_check_period_rd_A	93094658	1656	0	0
creator_sw_cfg_read_lock_rd_A	93094658	911	0	0
direct_access_address_rd_A	93094658	431	0	0
direct_access_wdata_0_rd_A	93094658	83	0	0
direct_access_wdata_1_rd_A	93094658	53	0	0
integrity_check_period_rd_A	93094658	1723	0	0
intr_enable_rd_A	93094658	2285	0	0
owner_sw_cfg_read_lock_rd_A	93094658	965	0	0
rot_creator_auth_codesign_read_lock_rd_A	93094658	1110	0	0
rot_creator_auth_state_read_lock_rd_A	93094658	984	0	0
vendor_test_read_lock_rd_A	93094658	1098	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	329955	0	0
T7	67435	1078	0	0
T14	0	1336	0	0
T15	0	2312	0	0
T19	0	1480	0	0
T20	0	12972	0	0
T21	0	4901	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T150	18713	0	0	0
T160	0	8499	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T246	0	1503	0	0
T273	0	5915	0	0
T274	0	5446	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1698	0	0
T7	67435	2	0	0
T14	0	9	0	0
T15	0	14	0	0
T21	0	13	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	14	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	44	0	0
T313	0	63	0	0
T314	0	59	0	0
T315	0	16	0	0
T316	0	29	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1045	0	0
T7	67435	20	0	0
T14	0	5	0	0
T15	0	14	0	0
T21	0	3	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	27	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	50	0	0
T313	0	55	0	0
T314	0	40	0	0
T315	0	31	0	0
T316	0	20	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1809	0	0
T7	67435	20	0	0
T14	0	5	0	0
T15	0	24	0	0
T21	0	23	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	47	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	49	0	0
T313	0	40	0	0
T314	0	51	0	0
T315	0	23	0	0
T316	0	20	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1656	0	0
T7	67435	2	0	0
T14	0	9	0	0
T15	0	17	0	0
T21	0	1	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	26	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	60	0	0
T313	0	36	0	0
T314	0	21	0	0
T315	0	17	0	0
T316	0	16	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	911	0	0
T14	83661	5	0	0
T15	142241	33	0	0
T16	217163	0	0	0
T21	0	8	0	0
T55	15205	0	0	0
T113	33723	0	0	0
T114	67419	0	0	0
T143	0	7	0	0
T172	83404	0	0	0
T238	33166	0	0	0
T312	0	53	0	0
T313	0	28	0	0
T314	0	41	0	0
T315	0	18	0	0
T316	0	17	0	0
T317	0	6	0	0
T318	15424	0	0	0
T319	15125	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	431	0	0
T7	67435	9	0	0
T14	0	12	0	0
T15	0	23	0	0
T21	0	11	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	24	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	24	0	0
T313	0	39	0	0
T314	0	45	0	0
T315	0	4	0	0
T316	0	40	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	83	0	0
T14	83661	4	0	0
T15	142241	9	0	0
T16	217163	0	0	0
T21	0	5	0	0
T23	0	26	0	0
T55	15205	0	0	0
T113	33723	0	0	0
T114	67419	0	0	0
T143	0	3	0	0
T172	83404	0	0	0
T238	33166	0	0	0
T312	0	13	0	0
T313	0	7	0	0
T314	0	2	0	0
T315	0	3	0	0
T318	15424	0	0	0
T319	15125	0	0	0
T320	0	7	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	53	0	0
T23	0	5	0	0
T28	10551	0	0	0
T46	16773	0	0	0
T68	112153	0	0	0
T157	11745	0	0	0
T255	398698	0	0	0
T285	103618	0	0	0
T312	376395	7	0	0
T313	0	5	0	0
T321	0	5	0	0
T322	0	31	0	0
T323	25678	0	0	0
T324	11674	0	0	0
T325	11722	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1723	0	0
T7	67435	28	0	0
T14	0	13	0	0
T15	0	20	0	0
T21	0	4	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	28	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	53	0	0
T313	0	42	0	0
T314	0	26	0	0
T315	0	19	0	0
T316	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	2285	0	0
T6	110641	14	0	0
T7	0	50	0	0
T14	0	25	0	0
T15	0	31	0	0
T17	65626	0	0	0
T21	0	6	0	0
T36	13602	0	0	0
T60	15976	0	0	0
T72	138714	0	0	0
T76	16024	0	0	0
T103	24082	0	0	0
T104	118163	0	0	0
T105	77343	0	0	0
T116	21672	0	0	0
T128	0	18	0	0
T154	0	1	0	0
T312	0	88	0	0
T313	0	54	0	0
T314	0	51	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	965	0	0
T7	67435	17	0	0
T14	0	5	0	0
T15	0	38	0	0
T21	0	3	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	14	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	41	0	0
T313	0	64	0	0
T314	0	57	0	0
T315	0	6	0	0
T316	0	19	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1110	0	0
T7	67435	15	0	0
T14	0	4	0	0
T15	0	18	0	0
T21	0	13	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	10	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	55	0	0
T313	0	30	0	0
T314	0	31	0	0
T315	0	24	0	0
T316	0	14	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	984	0	0
T7	67435	13	0	0
T14	0	20	0	0
T15	0	40	0	0
T21	0	7	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	22	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	31	0	0
T313	0	66	0	0
T314	0	44	0	0
T315	0	27	0	0
T316	0	24	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93094658	1098	0	0
T7	67435	3	0	0
T14	0	6	0	0
T15	0	18	0	0
T21	0	5	0	0
T106	117717	0	0	0
T107	128075	0	0	0
T108	237208	0	0	0
T143	0	43	0	0
T150	18713	0	0	0
T171	92664	0	0	0
T176	13735	0	0	0
T177	12639	0	0	0
T193	13404	0	0	0
T224	48580	0	0	0
T312	0	51	0	0
T313	0	48	0	0
T314	0	27	0	0
T315	0	16	0	0
T316	0	22	0	0