Unified Coverage Report

Go previous page

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.core_tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1299	1299	0	0
tb.dut.core_tlul_assert_device.gen_device.aDataKnown_M	0	0	90407437	3383322	0	0
tb.dut.core_tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	90406517	321639	0	0
tb.dut.core_tlul_assert_device.gen_device.contigMask_M	0	0	90407437	5263299	0	0
tb.dut.core_tlul_assert_device.gen_device.dDataKnown_A	0	0	90407437	8691977	0	0
tb.dut.core_tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	90406517	337269	0	0
tb.dut.core_tlul_assert_device.gen_device.legalAParam_M	0	0	90407437	9496604	0	0
tb.dut.core_tlul_assert_device.gen_device.legalDParam_A	0	0	90407437	13405354	0	0
tb.dut.core_tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	90407437	9496604	0	0
tb.dut.core_tlul_assert_device.gen_device.respMustHaveReq_A	0	0	90407437	13405354	0	0
tb.dut.core_tlul_assert_device.gen_device.respOpcode_A	0	0	90407437	13405354	0	0
tb.dut.core_tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	90407437	13405354	0	0
tb.dut.core_tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	90406517	232949	0	0
tb.dut.core_tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	90406517	238780	0	0
tb.dut.core_tlul_assert_device.p_dbw.TlDbw_A	0	0	1299	1299	0	0
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	0	0	87543204	50	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.AccessKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.DigestKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.EccErrorState_A	0	0	87543204	13221	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.ErrorKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.FsmStateKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitDoneKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A	0	0	87543204	16662526	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A	0	0	87543204	16662526	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpReqKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A	0	0	87543204	16998882	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulGntKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A	0	0	87543204	5956	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A	0	0	87543204	2056035	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	87543204	25824328	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs.AssertConnected_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	0	0	87543204	50	0	0
tb.dut.gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	0	0	87543204	50	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.AccessKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.CnstyChkAckKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DigestKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.DigestOffsetMustBeRepresentable_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ErrorKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitDoneKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitReadLocksPartition_A	0	0	87543204	23556343	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.InitWriteLocksPartition_A	0	0	87543204	23556343	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.IntegChkAckKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OffsetMustBeBlockAligned_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpAddrKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpCmdKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpErrorState_A	0	0	87543204	13	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpPartBufSize_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpReqKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpSizeKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.OtpWdataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ReadLockPropagation_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblCmdKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblDataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblModeKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblMtxReqKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblSelKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrmblValidKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.SizeMustBeBlockAligned_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.WriteLockPropagation_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.EccErrKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.EccKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.RDataOutKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.WidthMustBe64bit_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs.AssertConnected_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	0	0	87543204	50	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.AccessKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.DigestKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.DigestOffsetMustBeRepresentable_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.EccErrorState_A	0	0	87543204	11553	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.ErrorKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.FsmStateKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitDoneKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitReadLocksPartition_A	0	0	87543204	16839238	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.InitWriteLocksPartition_A	0	0	87543204	16839238	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OffsetMustBeBlockAligned_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpAddrKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpCmdKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpErrorState_A	0	0	87543204	76	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpReqKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpSizeKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.OtpWdataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.ReadLockPropagation_A	0	0	87543204	16862595	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.SizeMustBeBlockAligned_A	0	0	1124	1124	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulGntKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRdataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulReadOnReadLock_A	0	0	87543204	6235	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRerrorKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.TlulRvalidKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.WriteLockPropagation_A	0	0	87543204	2056471	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.DigestWriteLocksPartition_A	0	0	87543204	25985981	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock.OutputsKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataKnown_A	0	0	87543204	86701732	0	0
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.DataOutKnown_A	0	0	87543204	86701732	0	0

Go next page

	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Category 0	1457	0	20

	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Severity 0	1457	0	20

	NUMBER	PERCENT
Total Number	1457	100.00
Uncovered	54	3.71
Success	1403	96.29
Failure	0	0.00
Incomplete	11	0.75
Without Attempts	5	0.34

	NUMBER	PERCENT
Total Number	20	100.00
Uncovered	0	0.00
All Matches	20	100.00
First Matches	20	100.00