Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149                         assign otp_err = otp_err_e'(otp_err_i);
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153        1/1                if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
           Tests:       T1 T2 T3 
154        1/1                  otp_err = NoError;
           Tests:       T4 T98 T99 
155                           end else begin
156        1/1                  otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                   ==>  MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        excluded                   error_d = MacroEccCorrError;
Exclude Annotation: VC_COV_UNR
222                                 end
                        MISSING_ELSE
223                               end else begin
224        excluded                 state_d = ErrorSt;
Exclude Annotation: VC_COV_UNR
225        excluded                 error_d = otp_err;
Exclude Annotation: VC_COV_UNR
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T3 T4 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T3 T4 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T3 T4 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T4 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T3 T4 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T3 T4 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T3 T4 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T3 T4 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T3 T4 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T6 T7 T129 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T6 T7 T129 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T6 T7 T129 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T6 T7 T129 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T4 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T3 T4 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T3 T4 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T3 T4 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T3 T4 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T3 T4 
273        excluded                   error_d = MacroEccCorrError;
Exclude Annotation: VC_COV_UNR
274                                 end
                        MISSING_ELSE
275                               end else begin
276        excluded                 state_d = ErrorSt;
Exclude Annotation: VC_COV_UNR
277        excluded                 error_d = otp_err;
Exclude Annotation: VC_COV_UNR
278                                 // This causes the TL-UL adapter to return a bus error.
279        excluded                 tlul_rerror_o = 2'b11;
Exclude Annotation: VC_COV_UNR
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T4 T6 
289        1/1                    error_d = FsmStateError;
           Tests:       T22 T23 T24 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T4 T6 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T12 T94 T100 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T12 T94 T100 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T4 T6 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T12 T94 T100 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T12 T94 T100 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T109 T179 T180 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T109 T179 T180 
317        1/1                  error_d = CheckFailError;
           Tests:       T109 T179 T180 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T4 T6 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T4 T6 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T4 T6 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T4 T6 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339        1/1              assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
           Tests:       T1 T2 T3 
340                     
341                       end else begin : gen_nonzero_offset
342                         assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T109,T179,T180
1	Covered	T109,T179,T180

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T2,T4,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T12
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T4,T6
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T235,T236,T237
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T7,T129
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T107,T108,T109
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T6,T7,T129
CheckFailError	317	Covered	T109,T179,T180
FsmStateError	289	Covered	T2,T4,T6
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T155,T167
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T6,T7,T129
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T109,T179,T180
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T4,T6
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T6,T7,T129
NoError->CheckFailError	317	Covered	T109,T179,T180
NoError->FsmStateError	289	Covered	T2,T4,T6
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==> (Excluded)
Exclude Annotation: VC_COV_UNR
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==> (Excluded)
Exclude Annotation: VC_COV_UNR
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T119,T202
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T7,T129
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T94,T100
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T94,T100
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T109,T179,T180
1	0	Covered	T109,T179,T180
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

153              if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
                 -1-  
154                otp_err = NoError;
                   ==>
155              end else begin
156                otp_err = otp_err_e'(otp_err_i);
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T98,T99
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	87543204	86701732	0	0
DigestKnown_A	87543204	86701732	0	0
DigestOffsetMustBeRepresentable_A	1124	1124	0	0
EccErrorState_A	87543204	13221	0	0
ErrorKnown_A	87543204	86701732	0	0
FsmStateKnown_A	87543204	86701732	0	0
InitDoneKnown_A	87543204	86701732	0	0
InitReadLocksPartition_A	87543204	16662526	0	0
InitWriteLocksPartition_A	87543204	16662526	0	0
OffsetMustBeBlockAligned_A	1124	1124	0	0
OtpAddrKnown_A	87543204	86701732	0	0
OtpCmdKnown_A	87543204	86701732	0	0
OtpErrorState_A	87543204	0	0	0
OtpReqKnown_A	87543204	86701732	0	0
OtpSizeKnown_A	87543204	86701732	0	0
OtpWdataKnown_A	87543204	86701732	0	0
ReadLockPropagation_A	87543204	16998882	0	0
SizeMustBeBlockAligned_A	1124	1124	0	0
TlulGntKnown_A	87543204	86701732	0	0
TlulRdataKnown_A	87543204	86701732	0	0
TlulReadOnReadLock_A	87543204	5956	0	0
TlulRerrorKnown_A	87543204	86701732	0	0
TlulRvalidKnown_A	87543204	86701732	0	0
WriteLockPropagation_A	87543204	2056035	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	87543204	25824328	0	0
u_state_regs_A	87543204	86701732	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	13221	0	0
T53	14280	0	0	0
T90	199068	0	0	0
T109	12310	3714	0	0
T179	0	2285	0	0
T180	0	2343	0	0
T203	0	2727	0	0
T204	0	2152	0	0
T213	126074	0	0	0
T214	27747	0	0	0
T215	44955	0	0	0
T216	927760	0	0	0
T217	21044	0	0	0
T218	17105	0	0	0
T219	36953	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16662526	0	0
T1	5432	67	0	0
T2	10698	4205	0	0
T3	25481	849	0	0
T4	10281	4908	0	0
T5	4680	57	0	0
T6	40011	1421	0	0
T7	36446	598	0	0
T11	6282	38	0	0
T12	98597	83445	0	0
T13	28315	341	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16662526	0	0
T1	5432	67	0	0
T2	10698	4205	0	0
T3	25481	849	0	0
T4	10281	4908	0	0
T5	4680	57	0	0
T6	40011	1421	0	0
T7	36446	598	0	0
T11	6282	38	0	0
T12	98597	83445	0	0
T13	28315	341	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16998882	0	0
T6	40011	368	0	0
T7	36446	972	0	0
T11	6282	0	0	0
T12	98597	85625	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T18	0	12305	0	0
T92	0	4265	0	0
T94	25265	14535	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T101	0	9190	0	0
T111	0	146	0	0
T125	0	2334	0	0
T129	0	13508	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	5956	0	0
T6	40011	1	0	0
T7	36446	2	0	0
T11	6282	0	0	0
T12	98597	18	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T18	0	10	0	0
T92	0	6	0	0
T94	25265	5	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	2	0	0
T125	0	3	0	0
T128	0	6	0	0
T129	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	2056035	0	0
T7	36446	759	0	0
T11	6282	0	0	0
T12	98597	0	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T55	0	3093	0	0
T92	0	1484	0	0
T93	20991	0	0	0
T94	25265	0	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T114	0	9992	0	0
T117	0	1643	0	0
T118	0	1145	0	0
T119	0	4217	0	0
T120	0	12961	0	0
T125	0	3335	0	0
T141	0	15358	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	25824328	0	0
T6	40011	18309	0	0
T7	36446	30124	0	0
T11	6282	0	0	0
T12	98597	2497	0	0
T13	28315	0	0	0
T17	23919	16799	0	0
T19	0	17781	0	0
T82	0	2973	0	0
T92	0	20928	0	0
T94	25265	2942	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T125	0	21762	0	0
T129	0	14584	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T133 T181 T182 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T99 T183 T184 
225        1/1                      error_d = otp_err;
           Tests:       T99 T183 T184 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T3 T7 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T3 T7 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T3 T7 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T7 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T3 T7 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T3 T7 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T3 T7 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T3 T7 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T3 T7 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T12 T129 T18 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T12 T129 T18 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T12 T129 T18 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T12 T129 T18 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T7 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T3 T7 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T3 T7 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T3 T7 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T3 T7 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T3 T7 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T96 T55 T146 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T168 T185 T186 
277        1/1                      error_d = otp_err;
           Tests:       T168 T185 T186 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T168 T185 T186 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T4 T6 
289        1/1                    error_d = FsmStateError;
           Tests:       T22 T23 T24 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T4 T6 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T12 T94 T100 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T12 T94 T100 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T4 T6 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T12 T94 T100 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T12 T94 T100 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T109 T180 T187 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T109 T180 T187 
317        1/1                  error_d = CheckFailError;
           Tests:       T109 T180 T187 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T4 T6 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T4 T6 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T4 T6 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T4 T6 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T7 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T133,T181,T182

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T96,T55,T146

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T109,T180,T187
1	Covered	T109,T180,T187

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T2,T4,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T94,T100
1	1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T7

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T17,T99

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T17,T99

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T7
ReadWaitSt	252	Covered	T2,T3,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T4,T6
IdleSt->ReadSt	236	Covered	T2,T3,T7
InitSt->ErrorSt	315	Covered	T235,T236,T237
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T99,T183,T184
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T12,T129,T18
ReadSt->ReadWaitSt	252	Covered	T2,T3,T7
ReadWaitSt->ErrorSt	276	Covered	T168,T185,T186
ReadWaitSt->IdleSt	270	Covered	T2,T3,T7
ResetSt->ErrorSt	315	Covered	T107,T108,T109
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T12,T129,T18
CheckFailError	317	Covered	T109,T180,T187
FsmStateError	289	Covered	T2,T4,T6
MacroEccCorrError	221	Covered	T96,T133,T55
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T12,T155,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T129,T18,T92
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T109,T180,T187
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T4,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T133,T146,T174
MacroEccCorrError->NoError	235	Covered	T96,T55,T174
NoError->AccessError	256	Covered	T12,T129,T18
NoError->CheckFailError	317	Covered	T109,T180,T187
NoError->FsmStateError	289	Covered	T2,T4,T6
NoError->MacroEccCorrError	221	Covered	T96,T133,T55

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T17,T99
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T133,T181,T182
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T99,T183,T184
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T125,T119
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T12,T129,T18
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T96,T55,T146
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T168,T185,T186
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T94,T100
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T94,T100
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T109,T180,T187
1	0	Covered	T109,T180,T187
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	87543204	86701732	0	0
DigestKnown_A	87543204	86701732	0	0
DigestOffsetMustBeRepresentable_A	1124	1124	0	0
EccErrorState_A	87543204	11553	0	0
ErrorKnown_A	87543204	86701732	0	0
FsmStateKnown_A	87543204	86701732	0	0
InitDoneKnown_A	87543204	86701732	0	0
InitReadLocksPartition_A	87543204	16839238	0	0
InitWriteLocksPartition_A	87543204	16839238	0	0
OffsetMustBeBlockAligned_A	1124	1124	0	0
OtpAddrKnown_A	87543204	86701732	0	0
OtpCmdKnown_A	87543204	86701732	0	0
OtpErrorState_A	87543204	76	0	0
OtpReqKnown_A	87543204	86701732	0	0
OtpSizeKnown_A	87543204	86701732	0	0
OtpWdataKnown_A	87543204	86701732	0	0
ReadLockPropagation_A	87543204	16862595	0	0
SizeMustBeBlockAligned_A	1124	1124	0	0
TlulGntKnown_A	87543204	86701732	0	0
TlulRdataKnown_A	87543204	86701732	0	0
TlulReadOnReadLock_A	87543204	6235	0	0
TlulRerrorKnown_A	87543204	86701732	0	0
TlulRvalidKnown_A	87543204	86701732	0	0
WriteLockPropagation_A	87543204	2056471	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	87543204	25985981	0	0
u_state_regs_A	87543204	86701732	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	11553	0	0
T53	14280	0	0	0
T90	199068	0	0	0
T109	12310	3714	0	0
T180	0	2343	0	0
T187	0	2769	0	0
T203	0	2727	0	0
T213	126074	0	0	0
T214	27747	0	0	0
T215	44955	0	0	0
T216	927760	0	0	0
T217	21044	0	0	0
T218	17105	0	0	0
T219	36953	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16839238	0	0
T1	5432	84	0	0
T2	10698	4256	0	0
T3	25481	934	0	0
T4	10281	4951	0	0
T5	4680	74	0	0
T6	40011	1574	0	0
T7	36446	785	0	0
T11	6282	55	0	0
T12	98597	83479	0	0
T13	28315	426	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16839238	0	0
T1	5432	84	0	0
T2	10698	4256	0	0
T3	25481	934	0	0
T4	10281	4951	0	0
T5	4680	74	0	0
T6	40011	1574	0	0
T7	36446	785	0	0
T11	6282	55	0	0
T12	98597	83479	0	0
T13	28315	426	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	76	0	0
T18	36744	0	0	0
T93	20991	0	0	0
T99	12694	1	0	0
T123	22097	0	0	0
T124	6631	0	0	0
T125	28455	0	0	0
T126	26866	0	0	0
T127	23093	0	0	0
T129	28242	0	0	0
T130	25055	0	0	0
T168	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T220	0	1	0	0
T223	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16862595	0	0
T12	98597	90707	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T18	0	10462	0	0
T92	0	7643	0	0
T93	20991	0	0	0
T94	25265	14522	0	0
T95	0	9784	0	0
T97	0	1849	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T101	0	10136	0	0
T111	0	2191	0	0
T125	0	738	0	0
T129	28242	11992	0	0
T130	25055	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	6235	0	0
T12	98597	22	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T18	0	8	0	0
T92	0	3	0	0
T93	20991	0	0	0
T94	25265	7	0	0
T95	0	1	0	0
T97	0	5	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	4	0	0
T101	0	2	0	0
T128	0	3	0	0
T129	28242	1	0	0
T130	25055	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	2056471	0	0
T18	36744	2606	0	0
T19	58862	0	0	0
T55	0	3903	0	0
T82	14502	0	0	0
T92	31578	0	0	0
T101	0	2624	0	0
T106	0	777	0	0
T116	0	4642	0	0
T117	0	1162	0	0
T118	0	2033	0	0
T120	0	13676	0	0
T121	0	2259	0	0
T123	22097	0	0	0
T124	6631	0	0	0
T125	28455	0	0	0
T126	26866	0	0	0
T127	23093	0	0	0
T128	36425	0	0	0
T232	0	7103	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	25985981	0	0
T12	98597	2480	0	0
T13	28315	0	0	0
T17	23919	16765	0	0
T18	0	20738	0	0
T92	0	20826	0	0
T93	20991	0	0	0
T94	25265	0	0	0
T95	0	35191	0	0
T98	13843	0	0	0
T99	12694	2645	0	0
T100	28622	0	0	0
T101	0	47317	0	0
T111	0	30836	0	0
T125	0	21677	0	0
T129	28242	14533	0	0
T130	25055	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T52 T25 T188 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T98 T133 T189 
225        1/1                      error_d = otp_err;
           Tests:       T98 T133 T189 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T3 T4 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T3 T4 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T3 T4 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T4 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T3 T4 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T3 T4 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T3 T4 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T3 T4 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T3 T4 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T7 T12 T129 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T7 T12 T129 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T7 T12 T129 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T7 T12 T129 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T4 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T3 T4 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T3 T4 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T3 T4 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T3 T4 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T3 T4 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T168 T56 T190 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T191 T192 T193 
277        1/1                      error_d = otp_err;
           Tests:       T191 T192 T193 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T191 T192 T193 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T4 T6 
289        1/1                    error_d = FsmStateError;
           Tests:       T22 T23 T24 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T4 T6 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T12 T94 T100 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T12 T94 T100 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T4 T6 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T12 T94 T100 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T12 T94 T100 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T107 T109 T180 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T107 T109 T180 
317        1/1                  error_d = CheckFailError;
           Tests:       T107 T109 T180 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T4 T6 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T4 T6 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T4 T6 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T4 T6 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T52,T25,T188

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T168,T56,T190

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T107,T109,T180
1	Covered	T107,T109,T180

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T2,T4,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T12,T94
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T17,T94

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T17,T94

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T4,T6
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T238,T235,T236
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T98,T99,T133
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T7,T12,T129
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T191,T192,T193
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T107,T108,T109
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T7,T12,T129
CheckFailError	317	Covered	T107,T109,T180
FsmStateError	289	Covered	T2,T4,T6
MacroEccCorrError	221	Covered	T168,T56,T190
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T12,T155,T172
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T7,T12,T129
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T107,T109,T180
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T4,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T168,T190,T186
MacroEccCorrError->NoError	235	Covered	T56,T76,T77
NoError->AccessError	256	Covered	T7,T12,T129
NoError->CheckFailError	317	Covered	T107,T109,T180
NoError->FsmStateError	289	Covered	T2,T4,T6
NoError->MacroEccCorrError	221	Covered	T168,T56,T190

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T17,T94
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T52,T25,T188
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T98,T133,T189
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T92,T119,T202
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T12,T129
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T168,T56,T190
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T191,T192,T193
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T12,T94,T100
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T12,T94,T100
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T107,T109,T180
1	0	Covered	T107,T109,T180
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	87543204	86701732	0	0
DigestKnown_A	87543204	86701732	0	0
DigestOffsetMustBeRepresentable_A	1124	1124	0	0
EccErrorState_A	87543204	15837	0	0
ErrorKnown_A	87543204	86701732	0	0
FsmStateKnown_A	87543204	86701732	0	0
InitDoneKnown_A	87543204	86701732	0	0
InitReadLocksPartition_A	87543204	17014652	0	0
InitWriteLocksPartition_A	87543204	17014652	0	0
OffsetMustBeBlockAligned_A	1124	1124	0	0
OtpAddrKnown_A	87543204	86701732	0	0
OtpCmdKnown_A	87543204	86701732	0	0
OtpErrorState_A	87543204	50	0	0
OtpReqKnown_A	87543204	86701732	0	0
OtpSizeKnown_A	87543204	86701732	0	0
OtpWdataKnown_A	87543204	86701732	0	0
ReadLockPropagation_A	87543204	16740408	0	0
SizeMustBeBlockAligned_A	1124	1124	0	0
TlulGntKnown_A	87543204	86701732	0	0
TlulRdataKnown_A	87543204	86701732	0	0
TlulReadOnReadLock_A	87543204	6660	0	0
TlulRerrorKnown_A	87543204	86701732	0	0
TlulRvalidKnown_A	87543204	86701732	0	0
WriteLockPropagation_A	87543204	1446381	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	87543204	18194364	0	0
u_state_regs_A	87543204	86701732	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	15837	0	0
T107	15114	2132	0	0
T109	0	3714	0	0
T180	0	2343	0	0
T186	217653	0	0	0
T187	0	2769	0	0
T203	0	2727	0	0
T204	0	2152	0	0
T205	16879	0	0	0
T206	39809	0	0	0
T207	145314	0	0	0
T208	32536	0	0	0
T209	88818	0	0	0
T210	24666	0	0	0
T211	34590	0	0	0
T212	78744	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	17014652	0	0
T1	5432	101	0	0
T2	10698	4307	0	0
T3	25481	1019	0	0
T4	10281	4985	0	0
T5	4680	91	0	0
T6	40011	1727	0	0
T7	36446	972	0	0
T11	6282	72	0	0
T12	98597	83513	0	0
T13	28315	511	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	17014652	0	0
T1	5432	101	0	0
T2	10698	4307	0	0
T3	25481	1019	0	0
T4	10281	4985	0	0
T5	4680	91	0	0
T6	40011	1727	0	0
T7	36446	972	0	0
T11	6282	72	0	0
T12	98597	83513	0	0
T13	28315	511	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	50	0	0
T18	36744	0	0	0
T93	20991	0	0	0
T98	13843	1	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T123	22097	0	0	0
T124	6631	0	0	0
T125	28455	0	0	0
T129	28242	0	0	0
T130	25055	0	0	0
T133	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	16740408	0	0
T6	40011	134	0	0
T7	36446	1211	0	0
T11	6282	0	0	0
T12	98597	90699	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T18	0	11813	0	0
T92	0	6929	0	0
T94	25265	0	0	0
T95	0	5506	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T101	0	9903	0	0
T111	0	2842	0	0
T125	0	1561	0	0
T129	0	12556	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124	1124	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	6660	0	0
T7	36446	1	0	0
T11	6282	0	0	0
T12	98597	25	0	0
T13	28315	0	0	0
T17	23919	0	0	0
T18	0	9	0	0
T92	0	3	0	0
T93	20991	0	0	0
T94	25265	5	0	0
T98	13843	0	0	0
T99	12694	0	0	0
T100	28622	4	0	0
T101	0	6	0	0
T125	0	1	0	0
T128	0	4	0	0
T129	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	1446381	0	0
T19	58862	2093	0	0
T82	14502	0	0	0
T95	48656	0	0	0
T97	15972	0	0	0
T101	56454	0	0	0
T111	52584	0	0	0
T112	19181	0	0	0
T113	5081	0	0	0
T114	95066	0	0	0
T115	61114	12451	0	0
T117	0	6443	0	0
T120	0	53169	0	0
T121	0	8648	0	0
T141	0	6237	0	0
T142	0	7635	0	0
T202	0	11109	0	0
T233	0	18846	0	0
T239	0	7381	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	18194364	0	0
T12	98597	2463	0	0
T13	28315	0	0	0
T17	23919	16731	0	0
T18	0	26229	0	0
T19	0	17645	0	0
T93	20991	0	0	0
T94	25265	2908	0	0
T95	0	35157	0	0
T98	13843	3001	0	0
T99	12694	0	0	0
T100	28622	0	0	0
T111	0	30666	0	0
T114	0	68580	0	0
T129	28242	14482	0	0
T130	25055	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87543204	86701732	0	0
T1	5432	5382	0	0
T2	10698	10452	0	0
T3	25481	25010	0	0
T4	10281	10014	0	0
T5	4680	4619	0	0
T6	40011	39222	0	0
T7	36446	35679	0	0
T11	6282	6220	0	0
T12	98597	98413	0	0
T13	28315	27844	0	0