Unified Coverage Report :: Assertions

Assertions

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Assertions by Category

	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Category 0	1457	0	20

Assertions by Severity

	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Severity 0	1457	0	20

Summary for Assertions

	NUMBER	PERCENT
Total Number	1457	100.00
Uncovered	54	3.71
Success	1403	96.29
Failure	0	0.00
Incomplete	11	0.75
Without Attempts	5	0.34

Summary for Cover Sequences

	NUMBER	PERCENT
Total Number	20	100.00
Uncovered	0	0.00
All Matches	20	100.00
First Matches	20	100.00

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COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	90407437	6	6	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	90407437	6	6	2
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	90407437	945	945	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	90407437	1937	1937	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	90407437	57079	57079	53