Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1457020
Category 01457020


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1457020
Severity 01457020


Summary for Assertions
NUMBERPERCENT
Total Number1457100.00
Uncovered543.71
Success140396.29
Failure00.00
Incomplete110.75
Without Attempts50.34


Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A 00875432048670173200
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A 00875432048670173200
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A 001124112400
tb.dut.u_otp_ctrl_dai.u_state_regs_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A 001124112400
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A 001124112400
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A 001124112400
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A 001124112400
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A 001124112400
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A 001124112400
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A 001124112400
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A 001124112400
tb.dut.u_otp_ctrl_kdi.NonceWidth_A 001124112400
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A 001124112400
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A 00875432043105900
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A 00875432043105900
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A 00875432043105900
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A 00875432042525455800
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A 00875432046141389100
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A 00875432043105900
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A 00875432043105900
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A 00875432042528784100
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M 00875432042525455800
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A 00875432043105900
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A 001124112400
tb.dut.u_otp_ctrl_kdi.u_state_regs_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.ErrorKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.LcAckKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.LcErrKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A 001124112400
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A 001124112400
tb.dut.u_otp_ctrl_lci.u_state_regs_A 00875432048670173200
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A 001124112400
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A 001124112400
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A 001124112400
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A 00875432048670173200
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A 008754320423739800
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A 008754320412039100
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A 008754320425215000
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A 00875432048670173200
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A 001124112400
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A 00875432048670173200
tb.dut.u_otp_rsp_fifo.DataKnown_A 00875432041473115100
tb.dut.u_otp_rsp_fifo.DepthKnown_A 00875432048670173200
tb.dut.u_otp_rsp_fifo.RvalidKnown_A 00875432048670173200
tb.dut.u_otp_rsp_fifo.WreadyKnown_A 00875432048670173200
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00875432041473115100
tb.dut.u_part_sel_idx.CheckHotOne_A 00875432048670173200
tb.dut.u_part_sel_idx.CheckNGreaterZero_A 001124112400
tb.dut.u_part_sel_idx.GrantKnown_A 00875432048670173200
tb.dut.u_part_sel_idx.IdxKnown_A 00875432048670173200
tb.dut.u_part_sel_idx.Priority_A 00875432048670173200
tb.dut.u_part_sel_idx.ReqImpliesValid_A 00875432048670173200
tb.dut.u_part_sel_idx.ValidKnown_A 00875432048670173200
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A 00875432043677195800
tb.dut.u_prim_edn_req.DataOutputValid_A 008754320419583000
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 008754320439223400
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 008754320439214900
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 0024243634039245200
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 008754320419559900
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A 00875432048670173200
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A 00875432048670173200
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A 00875432048670173200
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A 00875432048670173200
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A 00875432048670173200
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A 00875432048670173200
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_reg_core.en2addrHit 0090406517654582800
tb.dut.u_reg_core.reAfterRv 0090406517654582800
tb.dut.u_reg_core.rePulse 0090406517566588000
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001299129900
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001299129900
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001299129900
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001299129900
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001299129900
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001299129900
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001299129900
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001299129900
tb.dut.u_reg_core.u_socket.NotOverflowed_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 0090406517949660400
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001299129900
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 00904065171340535400
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001299129900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 0090406517139437200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001299129900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 0090406517115296400
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001299129900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 0090406517751582500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001299129900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00904065171225239000
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 00904065178951266800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001299129900
tb.dut.u_reg_core.u_socket.maxN 001299129900
tb.dut.u_reg_core.wePulse 009040651787994800
tb.dut.u_scrmbl_mtx.CheckHotOne_A 00875432048670173200
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A 001124112400
tb.dut.u_scrmbl_mtx.GrantKnown_A 00875432048670173200
tb.dut.u_scrmbl_mtx.IdxKnown_A 00875432048670173200
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A 00875432044894386400
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A 00875432043775786800
tb.dut.u_scrmbl_mtx.ValidKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A 001124112400
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A 001124112400
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A 001124112400
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.WeOutKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite 001124112400
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty 00875432047543000
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull 00875432047543000
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A 001124112400
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A 0087543204153445000
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0087543204153445000
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A 001124112400
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck 001124112400
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A 008754320417285200
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 008754320417285200
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg 001124112400
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A 008754320447459500
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A 00875432048670173200
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 008754320447459500
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001124112400
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A 00875432048670173200
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 00875432048670173200
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A 001124112400
tb.dut.u_tlul_lc_gate.u_state_regs_A 00875432048670173200
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001124112400
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001124112400

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_arb.RoundRobin_A 0087543204001114
tb.dut.u_otp_arb.RoundRobin_A 0087543204001114
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A 0087543204001114
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 0087543204001114
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 00875432048666244503342
tb.dut.u_scrmbl_mtx.RoundRobin_A 0087543204001114

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A 000000


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00904074379069060
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00904074371621620
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00904074371621620
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00904074371121120
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 009040743726260
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 009040743796960
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 009040743799990
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0090407437305730570
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 0090407437534153410
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 0090407437332167533216751213
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00904074372162160
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 009040743714142
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 009040743714142
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0090407437992
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0090407437112
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0090407437662
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0090407437662
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00904074379459450
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 0090407437193719370
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 0090407437570795707953

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00904074379069060
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00904074371621620
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00904074371621620
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00904074371121120
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 009040743726260
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 009040743796960
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 009040743799990
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0090407437305730570
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 0090407437534153410
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 0090407437332167533216751213
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00904074372162160
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 009040743714142
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 009040743714142
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0090407437992
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0090407437112
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