Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5276926

1

T1

33

T2

943

T3

1848

full_word

2538774

1

T1

15

T2

151

T3

695

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7815400	1			T1	48		T2	1094		T3	2543
auto[TlIntgErrCmd]	100	1			T298	1		T299	3		T300	4
auto[TlIntgErrData]	113	1			T298	4		T299	4		T300	12
auto[TlIntgErrBoth]	87	1			T298	5		T299	3		T300	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5863180

1

T1

1

T2

931

T3

2344

auto[1]

1952520

1

T1

47

T2

163

T3

199

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3898617	1			T2	855		T3	1731		T5	1
auto[TlIntgErrNone]	partial	auto[1]	1378032	1			T1	33		T2	88		T3	117
auto[TlIntgErrNone]	full_word	auto[0]	1964432	1			T1	1		T2	76		T3	613
auto[TlIntgErrNone]	full_word	auto[1]	574319	1			T1	14		T2	75		T3	82
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T299	1		T300	2		T309	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T298	1		T299	1		T300	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T392	1		T393	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T299	1		T394	1		T392	2
auto[TlIntgErrData]	partial	auto[0]	59	1			T298	3		T299	1		T300	7
auto[TlIntgErrData]	partial	auto[1]	47	1			T299	3		T300	3		T389	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T298	1		T393	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T300	2		T309	1		T384	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T298	1		T300	2		T389	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T298	4		T299	2		T300	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T388	1		T394	1		T395	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T299	1		T396	1		T397	1