Module Definition
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Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.64 100.00 94.55 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700

701 // In this case we pass everything just through. 702 1/1 assign tl_sram_o = tl_i; Tests: T1 T2 T3  703 1/1 assign tl_o = tl_sram_i; Tests: T1 T2 T3  704 1/1 assign error_o = error_i; Tests: T1 T2 T3  705 assign alert_o = 1'b0; 706 assign compound_txn_in_progress_o = 1'b0; 707 708 // Signal only used in readback mode. 709 mubi4_t unused_readback_en; 710 unreachable assign unused_readback_en = readback_en_i; 711 712 end 713 714 // Signals only used for SVA. 715 logic unused_write_pending, unused_wr_collision; 716 unreachable assign unused_write_pending = write_pending_i; 717 unreachable assign unused_wr_collision = wr_collision_i;

Assert Coverage for Module : tlul_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 1124 1124 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124 1124 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0