Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T18 T19 T145
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T145 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T145 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T19,T145 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T18 T19 T145
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T145 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T145 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T19,T145 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T18 T19 T145
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T145 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T145 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T19,T145 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T18 T19 T145
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T145 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T145 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T19,T145 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T17 T18 T19
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T2 T5 T4
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T17,T18,T19 |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T18,T19 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 5 | 83.33 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 excluded q <= wr_data;
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
| Total | Covered | Percent |
|---|
| Conditions | 1 | 1 | 100.00 |
| Logical | 1 | 1 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
| Line No. | Total | Covered | Percent |
| Branches |
|
3 |
3 |
100.00 |
| TERNARY |
64 |
1 |
1 |
100.00 |
| IF |
56 |
2 |
2 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|