Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	44104	1			T101	19		T102	51		T37	30
access_err	51198	1			T4	2		T12	6		T17	41
write_blank_err	396	1			T129	1		T121	5		T7	2
ecc_uncorr_err	53912	1			T5	30		T129	614		T118	20
ecc_corr_err	1459	1			T5	3		T102	7		T37	6
no_err	74026	1			T3	33		T4	28		T5	5

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	611	1			T7	2		T8	8		T9	2
secret2	19485	1			T3	10		T6	5		T12	1
secret1	25931	1			T3	4		T4	1		T5	16
secret0	28927	1			T3	2		T4	1		T5	15
hw_cfg1	29590	1			T3	3		T4	8		T5	2
hw_cfg0	23379	1			T3	2		T4	2		T6	6
rot_creator_auth_state	17456	1			T4	4		T6	10		T17	14
rot_creator_auth_codesign	18053	1			T3	4		T4	4		T5	3
owner_sw_cfg	16475	1			T3	3		T4	3		T6	7
creator_sw_cfg	17689	1			T3	4		T4	3		T6	6
vendor_test	27499	1			T3	1		T4	4		T5	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2289	1			T235	77		T343	290		T270	128
fsm_err	secret1	3035	1			T349	184		T199	249		T350	47
fsm_err	secret0	4999	1			T351	381		T21	127		T352	32
fsm_err	hw_cfg1	2539	1			T353	248		T354	232		T355	99
fsm_err	hw_cfg0	7792	1			T197	258		T16	103		T260	574
fsm_err	rot_creator_auth_state	2132	1			T170	138		T171	26		T172	65
fsm_err	rot_creator_auth_codesign	3285	1			T169	52		T261	550		T356	122
fsm_err	owner_sw_cfg	1559	1			T157	38		T162	11		T252	62
fsm_err	creator_sw_cfg	3102	1			T155	26		T156	65		T243	251
fsm_err	vendor_test	13372	1			T101	19		T102	51		T37	30
access_err	life_cycle	611	1			T7	2		T8	8		T9	2
access_err	secret2	8800	1			T12	1		T17	6		T98	5
access_err	secret1	5567	1			T12	3		T17	4		T98	2
access_err	secret0	4165	1			T12	2		T98	2		T93	10
access_err	hw_cfg1	1113	1			T17	8		T98	4		T93	2
access_err	hw_cfg0	2012	1			T17	5		T105	3		T96	4
access_err	rot_creator_auth_state	4286	1			T17	7		T93	4		T102	1
access_err	rot_creator_auth_codesign	6476	1			T17	5		T93	10		T102	3
access_err	owner_sw_cfg	5967	1			T4	2		T101	1		T93	1
access_err	creator_sw_cfg	6360	1			T17	3		T102	5		T105	2
access_err	vendor_test	5841	1			T17	3		T93	2		T102	7
write_blank_err	secret2	8	1			T8	1		T106	1		T357	1
write_blank_err	secret1	25	1			T121	1		T9	1		T190	1
write_blank_err	secret0	40	1			T243	1		T358	1		T254	1
write_blank_err	hw_cfg1	60	1			T129	1		T7	1		T9	1
write_blank_err	hw_cfg0	14	1			T190	1		T15	1		T239	1
write_blank_err	rot_creator_auth_state	143	1			T7	1		T190	2		T357	2
write_blank_err	rot_creator_auth_codesign	49	1			T121	4		T358	1		T342	2
write_blank_err	owner_sw_cfg	16	1			T240	1		T359	3		T211	1
write_blank_err	creator_sw_cfg	20	1			T358	1		T213	1		T360	10
write_blank_err	vendor_test	21	1			T8	1		T361	2		T360	4
ecc_uncorr_err	secret2	3776	1			T155	12		T8	228		T170	74
ecc_uncorr_err	secret1	10531	1			T5	15		T121	740		T155	26
ecc_uncorr_err	secret0	12904	1			T5	15		T156	60		T171	51
ecc_uncorr_err	hw_cfg1	16924	1			T129	614		T7	370		T156	69
ecc_uncorr_err	hw_cfg0	3406	1			T155	21		T170	135		T156	68
ecc_uncorr_err	rot_creator_auth_state	3527	1			T155	44		T170	144		T156	68
ecc_uncorr_err	rot_creator_auth_codesign	774	1			T118	8		T155	51		T170	54
ecc_uncorr_err	owner_sw_cfg	959	1			T118	6		T155	18		T157	78
ecc_uncorr_err	creator_sw_cfg	1111	1			T118	6		T155	18		T171	56
ecc_corr_err	secret2	96	1			T91	1		T170	1		T136	1
ecc_corr_err	secret1	117	1			T118	1		T155	3		T91	3
ecc_corr_err	secret0	174	1			T40	3		T91	19		T52	2
ecc_corr_err	hw_cfg1	275	1			T5	2		T102	4		T40	1
ecc_corr_err	hw_cfg0	229	1			T102	2		T40	1		T91	8
ecc_corr_err	rot_creator_auth_state	149	1			T37	4		T155	3		T91	2
ecc_corr_err	rot_creator_auth_codesign	137	1			T5	1		T40	5		T156	1
ecc_corr_err	owner_sw_cfg	160	1			T37	1		T40	5		T91	2
ecc_corr_err	creator_sw_cfg	122	1			T102	1		T37	1		T40	1
no_err	secret2	4516	1			T3	10		T6	5		T13	1
no_err	secret1	6656	1			T3	4		T4	1		T5	1
no_err	secret0	6645	1			T3	2		T4	1		T6	9
no_err	hw_cfg1	8679	1			T3	3		T4	8		T6	7
no_err	hw_cfg0	9926	1			T3	2		T4	2		T6	6
no_err	rot_creator_auth_state	7219	1			T4	4		T6	10		T17	7
no_err	rot_creator_auth_codesign	7332	1			T3	4		T4	4		T5	2
no_err	owner_sw_cfg	7814	1			T3	3		T4	1		T6	7
no_err	creator_sw_cfg	6974	1			T3	4		T4	3		T6	6
no_err	vendor_test	8265	1			T3	1		T4	4		T5	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded