Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.LcSeedHwRdEnStable2_A	0	0	88289748	0	0	0
tb.dut.LcSeedHwRdEnStable3_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.OtpErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.BypassEnable0_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.BypassEnable1_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.EccErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ReadLockImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.ScrambledImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.WriteLockImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.BypassEnable0_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.EccErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.BypassEnable0_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.EccErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ReadLockPropagation_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.ScrambledImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.WriteLockImpliesDigest_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.EccErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.EccErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.EccErrorState_A	0	0	88289748	0	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.u_edn_arb.RoundRobin_A	0	0	88289748	0	0	1117
tb.dut.u_otp_arb.RoundRobin_A	0	0	88289748	0	0	1117
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GntImpliesReady_A	0	0	88289748	0	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GntImpliesValid_A	0	0	88289748	0	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IndexIsCorrect_A	0	0	88289748	0	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.NoReadyValidNoGrant_A	0	0	88289748	0	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReadyAndValidImplyGrant_A	0	0	88289748	0	0	0
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqAndReadyImplyGrant_A	0	0	88289748	0	0	0
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	88289748	0	0	1117
tb.dut.u_part_sel_idx.GntImpliesReady_A	0	0	88289748	0	0	0
tb.dut.u_part_sel_idx.GntImpliesValid_A	0	0	88289748	0	0	0
tb.dut.u_part_sel_idx.IndexIsCorrect_A	0	0	88289748	0	0	0
tb.dut.u_part_sel_idx.NoReadyValidNoGrant_A	0	0	88289748	0	0	0
tb.dut.u_part_sel_idx.ReadyAndValidImplyGrant_A	0	0	88289748	0	0	0
tb.dut.u_part_sel_idx.ReqAndReadyImplyGrant_A	0	0	88289748	0	0	0
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	88289748	0	0	1117
tb.dut.u_prim_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.GntImpliesReady_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.GntImpliesValid_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.IndexIsCorrect_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.LockArbDecision_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.ReadyAndValidImplyGrant_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.ReqAndReadyImplyGrant_A	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.ReqStaysHighUntilGranted0_M	0	0	88289748	0	0	0
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	88289748	0	0	1117
tb.dut.u_scrmbl_mtx.gen_data_port_assertion.DataFlow_A	0	0	88289748	0	0	0
tb.dut.u_tlul_lc_gate.OutStandingOvfl_A	0	0	88289748	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertTxKnown_A	0	0	88289748	87463934	0	0
tb.dut.CoreTlOutKnown_A	0	0	88289748	87463934	0	0
tb.dut.CreatorRootKeyShare0Size_A	0	0	1126	1126	0	0
tb.dut.CreatorRootKeyShare1Size_A	0	0	1126	1126	0	0
tb.dut.ErrorCodeWidth_A	0	0	1126	1126	0	0
tb.dut.FlashAddrKeySeedSize_A	0	0	1126	1126	0	0
tb.dut.FlashDataKeySeedSize_A	0	0	1126	1126	0	0
tb.dut.FlashOtpKeyRspKnown_A	0	0	88289748	87463934	0	0
tb.dut.FpvSecCmCntCnstyCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCntDaiCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCntIntegCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCntKdiEntropyCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCntKdiSeedCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCntLciCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCntScrmblCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCtrlDaiFsmCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCtrlKdiFsmCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCtrlLciFsmCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCtrlLfsrTimerFsmCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmCtrlScrambleFsmCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmDoubleLfsrCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	88289748	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	88289748	50	0	0
tb.dut.IntrOtpErrorKnown_A	0	0	88289748	87463934	0	0
tb.dut.IntrOtpOperationDoneKnown_A	0	0	88289748	87463934	0	0
tb.dut.LcOtpProgramRspKnown_A	0	0	88289748	87463934	0	0
tb.dut.LcSeedHwRdEnStable0_A	0	0	88289748	2149	0	0
tb.dut.LcSeedHwRdEnStable1_A	0	0	88289748	2149	0	0
tb.dut.LcStateSize_A	0	0	1126	1126	0	0
tb.dut.LcTransitionCntSize_A	0	0	1126	1126	0	0
tb.dut.OtpAstPwrSeqKnown_A	0	0	88289748	87463934	0	0
tb.dut.OtpBroadcastKnown_A	0	0	88289748	87463934	0	0
tb.dut.OtpErrorCode0_A	0	0	1126	1126	0	0
tb.dut.OtpErrorCode1_A	0	0	1126	1126	0	0
tb.dut.OtpErrorCode2_A	0	0	1126	1126	0	0
tb.dut.OtpErrorCode3_A	0	0	1126	1126	0	0
tb.dut.OtpErrorCode4_A	0	0	1126	1126	0	0
tb.dut.OtpIfWidth_A	0	0	1126	1126	0	0
tb.dut.OtpKeymgrKeyKnown_A	0	0	88289748	87463934	0	0
tb.dut.OtpLcDataKnown_A	0	0	88289748	87463934	0	0
tb.dut.OtpOtgnKeyKnown_A	0	0	88289748	87463934	0	0
tb.dut.OtpRespFifoUnderflow_A	0	0	88289748	1267878	0	0
tb.dut.OtpSramKeyKnown_A	0	0	88289748	87463934	0	0
tb.dut.PartSelMustBeOnehot_A	0	0	88289748	87463934	0	0
tb.dut.PrimTlOutKnown_A	0	0	88289748	87463934	0	0
tb.dut.PwrOtpInitRspKnown_A	0	0	88289748	87463934	0	0
tb.dut.RmaTokenSize_A	0	0	1126	1126	0	0
tb.dut.SramDataKeySeedSize_A	0	0	1126	1126	0	0
tb.dut.TestExitTokenSize_A	0	0	1126	1126	0	0
tb.dut.TestUnlockTokenSize_A	0	0	1126	1126	0	0
tb.dut.core_tlul_assert_device.aKnown_A	0	0	91185948	9344675	0	0
tb.dut.core_tlul_assert_device.aKnown_AKnownEnable	0	0	91185948	90307929	0	0
tb.dut.core_tlul_assert_device.aReadyKnown_A	0	0	91185948	90307929	0	0
tb.dut.core_tlul_assert_device.dKnown_A	0	0	91185948	12804941	0	0
tb.dut.core_tlul_assert_device.dKnown_AKnownEnable	0	0	91185948	90307929	0	0
tb.dut.core_tlul_assert_device.dReadyKnown_A	0	0	91185948	90307929	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
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tb.dut.core_tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0
tb.dut.core_tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	1301	1301	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Category 0	1457	0	20

	ASSERT	PROPERTIES	SEQUENCES
Total	1457	0	20
Severity 0	1457	0	20

	NUMBER	PERCENT
Total Number	1457	100.00
Uncovered	54	3.71
Success	1403	96.29
Failure	0	0.00
Incomplete	11	0.75
Without Attempts	5	0.34

	NUMBER	PERCENT
Total Number	20	100.00
Uncovered	0	0.00
All Matches	20	100.00
First Matches	20	100.00