Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4702220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2556372

1

T1

4

T2

1145

T3

262

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6135004	1			T1	4		T2	2554		T3	975
values[0x0]	529707	1			T1	9		T2	147		T3	141
values[0x1]	593881	1			T1	6		T2	161		T3	146

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3458323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3800269

1

T1

8

T2

1566

T3

561

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31487	1			T3	4		T6	9		T5	26
valid_sources[0x01]	23279	1			T6	34		T5	20		T4	4
valid_sources[0x02]	38606	1			T2	71		T3	5		T6	33
valid_sources[0x03]	24308	1			T3	7		T6	32		T5	22
valid_sources[0x04]	24834	1			T2	87		T3	6		T6	30
valid_sources[0x05]	22702	1			T3	4		T6	31		T5	18
valid_sources[0x06]	30419	1			T3	6		T6	3		T5	4
valid_sources[0x07]	23197	1			T3	2		T6	6		T5	19
valid_sources[0x08]	28812	1			T3	3		T6	25		T5	23
valid_sources[0x09]	23738	1			T3	4		T6	40		T5	23
valid_sources[0x0a]	27283	1			T3	6		T6	2		T5	26
valid_sources[0x0b]	25655	1			T3	13		T6	51		T5	32
valid_sources[0x0c]	23519	1			T3	4		T6	17		T5	16
valid_sources[0x0d]	23337	1			T3	7		T6	17		T5	14
valid_sources[0x0e]	22692	1			T3	2		T6	9		T5	16
valid_sources[0x0f]	23195	1			T3	1		T5	19		T4	7
valid_sources[0x10]	22351	1			T3	7		T6	10		T5	21
valid_sources[0x11]	33541	1			T3	5		T6	41		T5	28
valid_sources[0x12]	26518	1			T2	324		T3	6		T5	20
valid_sources[0x13]	27881	1			T3	10		T6	6		T5	22
valid_sources[0x14]	24210	1			T3	9		T6	10		T5	35
valid_sources[0x15]	22872	1			T3	8		T6	18		T5	25
valid_sources[0x16]	22810	1			T3	4		T6	16		T5	24
valid_sources[0x17]	28475	1			T2	93		T3	7		T6	24
valid_sources[0x18]	25719	1			T3	7		T6	31		T5	30
valid_sources[0x19]	25756	1			T2	135		T3	13		T6	4
valid_sources[0x1a]	33384	1			T3	8		T6	73		T5	18
valid_sources[0x1b]	24307	1			T3	1		T6	26		T5	28
valid_sources[0x1c]	27790	1			T2	109		T3	3		T6	29
valid_sources[0x1d]	25041	1			T3	8		T6	11		T5	33
valid_sources[0x1e]	24212	1			T3	2		T6	8		T5	31
valid_sources[0x1f]	27933	1			T3	4		T6	29		T5	23
valid_sources[0x20]	22899	1			T3	7		T6	7		T5	22
valid_sources[0x21]	24459	1			T3	2		T6	12		T5	24
valid_sources[0x22]	24617	1			T2	35		T3	2		T6	9
valid_sources[0x23]	26460	1			T3	6		T6	17		T5	23
valid_sources[0x24]	24325	1			T3	6		T6	27		T5	31
valid_sources[0x25]	24859	1			T3	6		T6	37		T5	19
valid_sources[0x26]	23514	1			T3	7		T6	13		T5	34
valid_sources[0x27]	23825	1			T3	5		T6	11		T5	19
valid_sources[0x28]	30088	1			T3	8		T6	27		T5	22
valid_sources[0x29]	25390	1			T3	6		T6	11		T5	18
valid_sources[0x2a]	24549	1			T3	5		T6	47		T5	22
valid_sources[0x2b]	36016	1			T3	6		T6	37		T5	26
valid_sources[0x2c]	24699	1			T3	2		T6	16		T5	18
valid_sources[0x2d]	26478	1			T2	41		T3	2		T6	50
valid_sources[0x2e]	23308	1			T3	5		T6	18		T5	26
valid_sources[0x2f]	36591	1			T3	3		T6	29		T5	28
valid_sources[0x30]	28488	1			T3	5		T6	67		T5	20
valid_sources[0x31]	39530	1			T3	9		T6	3		T5	16
valid_sources[0x32]	23302	1			T3	5		T6	27		T5	14
valid_sources[0x33]	103959	1			T3	7		T6	11		T5	21
valid_sources[0x34]	24342	1			T3	1		T6	6		T5	20
valid_sources[0x35]	24210	1			T3	10		T6	6		T5	19
valid_sources[0x36]	33574	1			T3	4		T6	30		T5	25
valid_sources[0x37]	30450	1			T3	11		T6	37		T5	26
valid_sources[0x38]	23476	1			T3	10		T6	12		T5	24
valid_sources[0x39]	25887	1			T3	4		T6	14		T5	20
valid_sources[0x3a]	23063	1			T3	3		T6	5		T5	18
valid_sources[0x3b]	25203	1			T3	5		T6	39		T5	21
valid_sources[0x3c]	25595	1			T3	4		T6	29		T5	22
valid_sources[0x3d]	22446	1			T2	168		T3	7		T6	3
valid_sources[0x3e]	36693	1			T2	71		T3	2		T6	11
valid_sources[0x3f]	26628	1			T3	2		T6	12		T5	37
valid_sources[0x40]	27829	1			T3	6		T6	24		T5	26
valid_sources[0x41]	22386	1			T3	8		T6	45		T5	13
valid_sources[0x42]	22365	1			T3	5		T6	21		T5	22
valid_sources[0x43]	22067	1			T2	46		T3	4		T6	7
valid_sources[0x44]	22860	1			T3	2		T6	6		T5	29
valid_sources[0x45]	37360	1			T3	11		T6	36		T5	33
valid_sources[0x46]	24833	1			T3	1		T6	65		T5	21
valid_sources[0x47]	24721	1			T3	4		T6	17		T5	17
valid_sources[0x48]	22572	1			T3	3		T6	23		T5	25
valid_sources[0x49]	22341	1			T3	13		T6	36		T5	28
valid_sources[0x4a]	33086	1			T3	3		T6	14		T5	21
valid_sources[0x4b]	24588	1			T3	1		T6	39		T5	11
valid_sources[0x4c]	22951	1			T3	3		T6	27		T5	20
valid_sources[0x4d]	23243	1			T3	3		T6	49		T5	29
valid_sources[0x4e]	23351	1			T3	7		T6	12		T5	20
valid_sources[0x4f]	24324	1			T3	1		T6	22		T5	18
valid_sources[0x50]	26724	1			T3	1		T6	20		T5	37
valid_sources[0x51]	25441	1			T3	4		T6	19		T5	18
valid_sources[0x52]	23209	1			T3	1		T6	26		T5	25
valid_sources[0x53]	24435	1			T3	5		T6	5		T5	21
valid_sources[0x54]	23209	1			T3	4		T6	11		T5	19
valid_sources[0x55]	22514	1			T3	4		T6	63		T5	20
valid_sources[0x56]	23981	1			T2	359		T3	9		T6	29
valid_sources[0x57]	25442	1			T3	9		T6	24		T5	29
valid_sources[0x58]	33752	1			T3	7		T6	25		T5	19
valid_sources[0x59]	97604	1			T3	2		T6	17		T5	15
valid_sources[0x5a]	52603	1			T3	3		T6	41		T5	35
valid_sources[0x5b]	24787	1			T3	4		T6	46		T5	14
valid_sources[0x5c]	22692	1			T3	6		T6	26		T5	18
valid_sources[0x5d]	23658	1			T3	3		T6	30		T5	32
valid_sources[0x5e]	22823	1			T3	2		T6	14		T5	22
valid_sources[0x5f]	23188	1			T3	5		T6	51		T5	19
valid_sources[0x60]	25086	1			T3	7		T6	60		T5	20
valid_sources[0x61]	27206	1			T3	3		T6	37		T5	21
valid_sources[0x62]	28875	1			T3	4		T6	23		T5	21
valid_sources[0x63]	22827	1			T3	4		T6	1		T5	23
valid_sources[0x64]	25563	1			T6	16		T5	24		T4	1
valid_sources[0x65]	24090	1			T3	3		T6	8		T5	21
valid_sources[0x66]	26235	1			T3	3		T6	68		T5	20
valid_sources[0x67]	24062	1			T6	52		T5	19		T4	8
valid_sources[0x68]	28892	1			T6	57		T5	21		T4	7
valid_sources[0x69]	22851	1			T3	2		T6	13		T5	20
valid_sources[0x6a]	23974	1			T3	3		T6	18		T5	19
valid_sources[0x6b]	22686	1			T3	3		T6	12		T5	24
valid_sources[0x6c]	24131	1			T3	2		T6	32		T5	26
valid_sources[0x6d]	22941	1			T3	8		T6	41		T5	19
valid_sources[0x6e]	24981	1			T3	5		T6	29		T5	31
valid_sources[0x6f]	28677	1			T6	40		T5	18		T4	4
valid_sources[0x70]	23689	1			T3	6		T6	67		T5	19
valid_sources[0x71]	23692	1			T3	12		T6	34		T5	19
valid_sources[0x72]	23310	1			T3	5		T6	16		T5	27
valid_sources[0x73]	25723	1			T3	4		T6	52		T5	25
valid_sources[0x74]	33961	1			T2	104		T3	3		T6	24
valid_sources[0x75]	26004	1			T2	187		T6	7		T5	14
valid_sources[0x76]	22885	1			T3	3		T6	59		T5	20
valid_sources[0x77]	24311	1			T2	5		T3	4		T6	40
valid_sources[0x78]	25939	1			T3	2		T6	8		T5	23
valid_sources[0x79]	27138	1			T3	6		T6	48		T5	26
valid_sources[0x7a]	34915	1			T3	7		T6	1		T5	30
valid_sources[0x7b]	24503	1			T2	218		T3	5		T6	4
valid_sources[0x7c]	23837	1			T3	7		T6	68		T5	18
valid_sources[0x7d]	26710	1			T2	2		T6	13		T5	20
valid_sources[0x7e]	24125	1			T2	334		T3	3		T6	49
valid_sources[0x7f]	22967	1			T2	2		T6	44		T5	25
valid_sources[0x80]	24485	1			T3	5		T6	44		T5	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2034992

1

T2

1019

T3

129

T6

1078

values[0x0]

all_enables

biggest_size

294041

1

T1

4

T2

77

T3

80

values[0x1]

all_enables

biggest_size

227339

1

T2

49

T3

53

T6

541

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26108	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

527750

1

T2

40

T4

20

T7

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	176784	1			T2	20		T4	10		T7	90
values[0x0]	183829	1			T2	5		T4	3		T7	43
values[0x1]	193245	1			T2	15		T4	7		T7	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

539592

1

T2

40

T4

20

T7

180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2370	1			T4	2		T129	1		T14	9
valid_sources[0x01]	2443	1			T122	9		T204	1		T156	1
valid_sources[0x02]	1776	1			T94	1		T95	1		T121	1
valid_sources[0x03]	2282	1			T7	3		T203	1		T124	1
valid_sources[0x04]	2284	1			T98	2		T122	8		T19	3
valid_sources[0x05]	2481	1			T94	2		T121	4		T204	2
valid_sources[0x06]	1888	1			T7	1		T126	2		T19	1
valid_sources[0x07]	1913	1			T7	2		T125	3		T95	1
valid_sources[0x08]	1898	1			T7	1		T98	1		T155	1
valid_sources[0x09]	2162	1			T7	2		T19	2		T104	3
valid_sources[0x0a]	2015	1			T7	1		T98	1		T121	2
valid_sources[0x0b]	1957	1			T4	2		T204	1		T142	3
valid_sources[0x0c]	2359	1			T126	1		T19	1		T104	7
valid_sources[0x0d]	1851	1			T7	2		T94	1		T288	1
valid_sources[0x0e]	2581	1			T4	1		T94	1		T122	2
valid_sources[0x0f]	1778	1			T94	1		T9	1		T95	1
valid_sources[0x10]	1986	1			T2	2		T7	1		T19	5
valid_sources[0x11]	1832	1			T94	1		T98	1		T122	1
valid_sources[0x12]	2100	1			T94	1		T126	1		T121	1
valid_sources[0x13]	2409	1			T2	1		T155	1		T205	1
valid_sources[0x14]	2459	1			T98	1		T121	2		T104	4
valid_sources[0x15]	2668	1			T7	1		T98	4		T81	1
valid_sources[0x16]	2466	1			T7	1		T9	1		T205	1
valid_sources[0x17]	2089	1			T9	1		T19	4		T288	2
valid_sources[0x18]	1807	1			T2	1		T7	1		T19	9
valid_sources[0x19]	2152	1			T7	2		T122	5		T187	2
valid_sources[0x1a]	1851	1			T7	1		T121	1		T81	2
valid_sources[0x1b]	2128	1			T98	4		T9	1		T122	12
valid_sources[0x1c]	1845	1			T4	1		T7	3		T94	2
valid_sources[0x1d]	2113	1			T7	1		T98	1		T95	1
valid_sources[0x1e]	2217	1			T203	1		T104	3		T146	2
valid_sources[0x1f]	2030	1			T81	1		T155	1		T156	1
valid_sources[0x20]	2103	1			T95	10		T128	1		T121	1
valid_sources[0x21]	2370	1			T94	1		T121	1		T18	2
valid_sources[0x22]	2239	1			T7	1		T127	1		T203	1
valid_sources[0x23]	1911	1			T7	1		T98	1		T122	1
valid_sources[0x24]	2380	1			T94	1		T98	3		T19	3
valid_sources[0x25]	2379	1			T125	15		T95	6		T18	2
valid_sources[0x26]	2220	1			T7	1		T19	1		T288	1
valid_sources[0x27]	2183	1			T7	2		T98	1		T121	1
valid_sources[0x28]	1771	1			T7	1		T94	1		T98	1
valid_sources[0x29]	1866	1			T7	1		T9	1		T203	5
valid_sources[0x2a]	2163	1			T7	1		T98	1		T121	1
valid_sources[0x2b]	2116	1			T14	13		T170	1		T200	1
valid_sources[0x2c]	1999	1			T4	1		T7	1		T81	2
valid_sources[0x2d]	2775	1			T7	2		T9	1		T95	1
valid_sources[0x2e]	1811	1			T7	2		T128	1		T129	1
valid_sources[0x2f]	1813	1			T121	1		T122	12		T19	1
valid_sources[0x30]	1844	1			T7	1		T94	1		T98	1
valid_sources[0x31]	2201	1			T7	1		T94	3		T98	1
valid_sources[0x32]	2589	1			T94	1		T98	1		T19	1
valid_sources[0x33]	1879	1			T2	1		T4	2		T98	1
valid_sources[0x34]	2617	1			T2	1		T19	3		T81	1
valid_sources[0x35]	4102	1			T2	2		T7	1		T19	1
valid_sources[0x36]	2036	1			T98	1		T125	5		T121	1
valid_sources[0x37]	2424	1			T94	1		T126	1		T104	1
valid_sources[0x38]	1918	1			T7	1		T9	1		T81	1
valid_sources[0x39]	1983	1			T204	3		T142	7		T97	11
valid_sources[0x3a]	1793	1			T2	2		T7	1		T19	1
valid_sources[0x3b]	2013	1			T94	1		T81	1		T203	1
valid_sources[0x3c]	2172	1			T7	1		T155	1		T156	1
valid_sources[0x3d]	2025	1			T2	1		T94	3		T122	7
valid_sources[0x3e]	1940	1			T2	1		T7	2		T95	1
valid_sources[0x3f]	2269	1			T7	2		T94	1		T98	1
valid_sources[0x40]	2230	1			T7	2		T126	8		T203	2
valid_sources[0x41]	2275	1			T98	2		T129	1		T288	1
valid_sources[0x42]	1958	1			T104	2		T204	2		T142	3
valid_sources[0x43]	1890	1			T7	1		T98	1		T95	9
valid_sources[0x44]	1912	1			T7	1		T121	1		T19	8
valid_sources[0x45]	1902	1			T98	1		T19	2		T156	1
valid_sources[0x46]	1910	1			T7	1		T128	1		T19	1
valid_sources[0x47]	3167	1			T2	1		T7	1		T94	2
valid_sources[0x48]	2339	1			T81	2		T204	1		T205	1
valid_sources[0x49]	2186	1			T98	1		T19	2		T81	1
valid_sources[0x4a]	1903	1			T7	2		T94	1		T98	1
valid_sources[0x4b]	2425	1			T7	2		T94	4		T95	6
valid_sources[0x4c]	1953	1			T98	1		T9	1		T95	3
valid_sources[0x4d]	2093	1			T94	1		T98	1		T126	4
valid_sources[0x4e]	2281	1			T94	2		T125	5		T19	1
valid_sources[0x4f]	1809	1			T95	3		T121	1		T127	6
valid_sources[0x50]	1978	1			T98	1		T122	2		T81	2
valid_sources[0x51]	1939	1			T7	1		T98	1		T126	2
valid_sources[0x52]	2536	1			T4	1		T7	1		T98	1
valid_sources[0x53]	2725	1			T7	1		T94	2		T126	6
valid_sources[0x54]	2317	1			T4	1		T8	15		T122	6
valid_sources[0x55]	2227	1			T7	1		T94	1		T203	3
valid_sources[0x56]	2143	1			T7	1		T9	1		T128	1
valid_sources[0x57]	2155	1			T98	1		T95	1		T121	1
valid_sources[0x58]	1907	1			T2	1		T7	2		T94	1
valid_sources[0x59]	2097	1			T7	1		T98	1		T203	4
valid_sources[0x5a]	1832	1			T7	1		T98	1		T18	3
valid_sources[0x5b]	2013	1			T7	2		T94	2		T121	1
valid_sources[0x5c]	2410	1			T2	1		T12	120		T98	2
valid_sources[0x5d]	2118	1			T7	1		T128	1		T104	1
valid_sources[0x5e]	2256	1			T94	1		T121	2		T122	6
valid_sources[0x5f]	1706	1			T98	1		T95	1		T81	2
valid_sources[0x60]	1905	1			T7	2		T94	1		T98	1
valid_sources[0x61]	2898	1			T121	1		T122	1		T81	1
valid_sources[0x62]	2271	1			T98	1		T128	1		T203	5
valid_sources[0x63]	2924	1			T94	1		T127	1		T162	1
valid_sources[0x64]	2320	1			T98	1		T95	3		T122	21
valid_sources[0x65]	2247	1			T7	1		T94	3		T126	3
valid_sources[0x66]	2084	1			T4	1		T7	2		T81	1
valid_sources[0x67]	1685	1			T98	1		T128	1		T122	3
valid_sources[0x68]	1893	1			T94	1		T98	2		T148	2
valid_sources[0x69]	1862	1			T7	2		T94	2		T121	2
valid_sources[0x6a]	1923	1			T98	1		T122	1		T124	1
valid_sources[0x6b]	3125	1			T2	1		T94	1		T288	3
valid_sources[0x6c]	1939	1			T2	1		T94	3		T18	8
valid_sources[0x6d]	1876	1			T7	1		T128	1		T18	4
valid_sources[0x6e]	2249	1			T2	4		T94	1		T98	1
valid_sources[0x6f]	2625	1			T94	2		T126	1		T124	1
valid_sources[0x70]	2200	1			T94	2		T126	2		T19	1
valid_sources[0x71]	1850	1			T19	2		T127	1		T155	2
valid_sources[0x72]	3131	1			T98	1		T155	2		T146	1
valid_sources[0x73]	2352	1			T94	1		T98	1		T148	17
valid_sources[0x74]	1929	1			T7	2		T19	1		T155	1
valid_sources[0x75]	1826	1			T8	4		T155	3		T193	22
valid_sources[0x76]	1896	1			T4	2		T9	1		T156	1
valid_sources[0x77]	2025	1			T7	4		T94	1		T95	5
valid_sources[0x78]	1786	1			T121	1		T81	1		T203	1
valid_sources[0x79]	2161	1			T8	14		T94	1		T9	1
valid_sources[0x7a]	2148	1			T7	2		T94	1		T98	2
valid_sources[0x7b]	2252	1			T7	1		T129	2		T19	3
valid_sources[0x7c]	2287	1			T7	1		T81	1		T156	1
valid_sources[0x7d]	2343	1			T155	1		T104	5		T206	1
valid_sources[0x7e]	2251	1			T19	2		T204	5		T156	1
valid_sources[0x7f]	2319	1			T2	1		T98	1		T121	1
valid_sources[0x80]	1878	1			T95	1		T81	2		T142	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

163811

1

T2

20

T4

10

T7

90

values[0x0]

all_enables

biggest_size

182408

1

T2

5

T4

3

T7

43

values[0x1]

all_enables

biggest_size

181531

1

T2

15

T4

7

T7

47