Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5491981

1

T1

15

T2

1717

T3

1000

full_word

2603334

1

T1

4

T2

1145

T3

262

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8095005	1			T1	19		T2	2862		T3	1262
auto[TlIntgErrCmd]	94	1			T274	4		T275	3		T276	3
auto[TlIntgErrData]	115	1			T274	8		T275	4		T276	4
auto[TlIntgErrBoth]	101	1			T274	8		T275	3		T276	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6192378

1

T1

4

T2

2554

T3

975

auto[1]

1902937

1

T1

15

T2

308

T3

287

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4151560	1			T1	4		T2	1535		T3	846
auto[TlIntgErrNone]	partial	auto[1]	1340136	1			T1	11		T2	182		T3	154
auto[TlIntgErrNone]	full_word	auto[0]	2040663	1			T2	1019		T3	129		T6	1078
auto[TlIntgErrNone]	full_word	auto[1]	562646	1			T1	4		T2	126		T3	133
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T275	1		T276	2		T284	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T274	3		T275	2		T276	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T373	1		T374	1		T375	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T274	1		T372	1		T374	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T274	5		T275	2		T276	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T274	2		T275	2		T284	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T274	1		T284	1		T376	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T276	1		T376	1		T377	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T274	3		T275	1		T276	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T274	3		T275	2		T276	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T371	1		T377	1		T378	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T274	2		T376	1		T374	1