Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	92428645	354290	0	0
check_regwen_rd_A	92428645	3243	0	0
check_timeout_rd_A	92428645	2000	0	0
check_trigger_regwen_rd_A	92428645	3200	0	0
consistency_check_period_rd_A	92428645	3189	0	0
creator_sw_cfg_read_lock_rd_A	92428645	2147	0	0
direct_access_address_rd_A	92428645	573	0	0
direct_access_wdata_0_rd_A	92428645	96	0	0
direct_access_wdata_1_rd_A	92428645	106	0	0
integrity_check_period_rd_A	92428645	2977	0	0
intr_enable_rd_A	92428645	3688	0	0
owner_sw_cfg_read_lock_rd_A	92428645	2285	0	0
rot_creator_auth_codesign_read_lock_rd_A	92428645	2173	0	0
rot_creator_auth_state_read_lock_rd_A	92428645	2240	0	0
vendor_test_read_lock_rd_A	92428645	2081	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	354290	0	0
T14	129089	2464	0	0
T15	0	3347	0	0
T16	0	10725	0	0
T21	0	2844	0	0
T61	77556	0	0	0
T89	0	8360	0	0
T90	0	4670	0	0
T92	0	7327	0	0
T111	64393	0	0	0
T112	21649	0	0	0
T113	27508	0	0	0
T114	6396	0	0	0
T170	22590	0	0	0
T191	177958	0	0	0
T192	68919	0	0	0
T234	169001	0	0	0
T263	0	3301	0	0
T264	0	2839	0	0
T289	0	7196	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	3243	0	0
T27	941849	0	0	0
T92	0	47	0	0
T154	14387	0	0	0
T263	174554	15	0	0
T264	149276	29	0	0
T320	0	29	0	0
T321	0	16	0	0
T322	0	27	0	0
T323	0	31	0	0
T324	0	17	0	0
T325	0	7	0	0
T326	0	19	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2000	0	0
T27	941849	0	0	0
T92	0	32	0	0
T154	14387	0	0	0
T263	174554	6	0	0
T264	149276	20	0	0
T320	0	27	0	0
T321	0	9	0	0
T322	0	21	0	0
T323	0	39	0	0
T324	0	21	0	0
T325	0	19	0	0
T326	0	17	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	3200	0	0
T27	941849	0	0	0
T92	0	46	0	0
T154	14387	0	0	0
T263	174554	18	0	0
T264	149276	20	0	0
T320	0	21	0	0
T321	0	14	0	0
T322	0	12	0	0
T323	0	36	0	0
T324	0	18	0	0
T325	0	29	0	0
T326	0	24	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	3189	0	0
T27	941849	0	0	0
T92	0	42	0	0
T154	14387	0	0	0
T263	174554	8	0	0
T264	149276	21	0	0
T320	0	32	0	0
T321	0	30	0	0
T322	0	19	0	0
T323	0	45	0	0
T324	0	42	0	0
T325	0	14	0	0
T326	0	29	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2147	0	0
T27	941849	0	0	0
T92	0	35	0	0
T154	14387	0	0	0
T263	174554	13	0	0
T264	149276	18	0	0
T320	0	22	0	0
T321	0	24	0	0
T322	0	19	0	0
T323	0	26	0	0
T324	0	12	0	0
T325	0	9	0	0
T326	0	15	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	573	0	0
T27	941849	0	0	0
T92	0	47	0	0
T154	14387	0	0	0
T263	174554	15	0	0
T264	149276	27	0	0
T320	0	25	0	0
T321	0	34	0	0
T322	0	18	0	0
T323	0	28	0	0
T324	0	22	0	0
T325	0	23	0	0
T326	0	15	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	96	0	0
T92	398933	1	0	0
T320	0	3	0	0
T321	0	13	0	0
T322	0	19	0	0
T323	0	7	0	0
T324	0	8	0	0
T326	0	2	0	0
T333	0	5	0	0
T334	0	6	0	0
T335	0	2	0	0
T336	8119	0	0	0
T337	60127	0	0	0
T338	20940	0	0	0
T339	9393	0	0	0
T340	73553	0	0	0
T341	89735	0	0	0
T342	31264	0	0	0
T343	12115	0	0	0
T344	8313	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	106	0	0
T92	398933	11	0	0
T320	0	7	0	0
T321	0	4	0	0
T322	0	7	0	0
T325	0	8	0	0
T333	0	15	0	0
T334	0	10	0	0
T335	0	6	0	0
T336	8119	0	0	0
T337	60127	0	0	0
T338	20940	0	0	0
T339	9393	0	0	0
T340	73553	0	0	0
T341	89735	0	0	0
T342	31264	0	0	0
T343	12115	0	0	0
T344	8313	0	0	0
T345	0	11	0	0
T346	0	14	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2977	0	0
T27	941849	0	0	0
T92	0	34	0	0
T154	14387	0	0	0
T263	174554	18	0	0
T264	149276	14	0	0
T320	0	14	0	0
T321	0	17	0	0
T322	0	15	0	0
T323	0	60	0	0
T324	0	12	0	0
T325	0	17	0	0
T326	0	21	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	3688	0	0
T27	941849	0	0	0
T92	0	60	0	0
T154	14387	0	0	0
T213	0	30	0	0
T263	174554	11	0	0
T264	149276	19	0	0
T320	0	48	0	0
T321	0	26	0	0
T322	0	13	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0
T347	0	25	0	0
T348	0	6	0	0
T349	0	52	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2285	0	0
T27	941849	0	0	0
T92	0	49	0	0
T154	14387	0	0	0
T263	174554	4	0	0
T264	149276	23	0	0
T320	0	19	0	0
T321	0	39	0	0
T322	0	19	0	0
T323	0	28	0	0
T324	0	9	0	0
T325	0	28	0	0
T326	0	14	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2173	0	0
T27	941849	0	0	0
T92	0	50	0	0
T154	14387	0	0	0
T262	68709	0	0	0
T264	149276	27	0	0
T320	0	26	0	0
T321	0	24	0	0
T322	0	15	0	0
T323	0	45	0	0
T324	0	30	0	0
T325	0	8	0	0
T326	0	18	0	0
T332	28173	0	0	0
T345	0	19	0	0
T350	23310	0	0	0
T351	155389	0	0	0
T352	58320	0	0	0
T353	73579	0	0	0
T354	52525	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2240	0	0
T27	941849	0	0	0
T92	0	45	0	0
T154	14387	0	0	0
T263	174554	11	0	0
T264	149276	23	0	0
T320	0	19	0	0
T321	0	41	0	0
T322	0	18	0	0
T323	0	34	0	0
T324	0	8	0	0
T325	0	27	0	0
T326	0	27	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92428645	2081	0	0
T27	941849	0	0	0
T92	0	40	0	0
T154	14387	0	0	0
T263	174554	8	0	0
T264	149276	23	0	0
T320	0	20	0	0
T321	0	20	0	0
T322	0	22	0	0
T323	0	32	0	0
T324	0	16	0	0
T325	0	12	0	0
T326	0	20	0	0
T327	62237	0	0	0
T328	41736	0	0	0
T329	67177	0	0	0
T330	86193	0	0	0
T331	9960	0	0	0
T332	28173	0	0	0