Module Definition
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Module : prim_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.u_state_flop
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_tlul_lc_gate.u_state_regs.u_state_flop
tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs.u_state_flop
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.u_state_flop
tb.dut.u_otp_init_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_otp_init_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_otp_ctrl_dai.u_state_regs.u_state_flop
tb.dut.u_otp_ctrl_lci.u_state_regs.u_state_flop
tb.dut.u_otp_ctrl_kdi.u_key_out_anchor.u_secure_anchor_flop
tb.dut.u_otp_ctrl_kdi.u_state_regs.u_state_flop
tb.dut.u_prim_lc_sender_otp_broadcast_valid.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_keygmr_key_valid
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs.u_state_flop
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs.u_state_flop
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs.u_state_flop
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs.u_state_flop
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs.u_state_flop
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs.u_state_flop



Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_init_sync.gen_generic.u_impl_generic.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_init_sync.gen_generic.u_impl_generic.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_dai.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_lci.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_kdi.u_key_out_anchor.u_secure_anchor_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_key_out_anchor


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_kdi.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_keygmr_key_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.94 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs.u_state_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00