Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	77.94			77.94
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	79.41			79.41
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	79.41			79.41
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	80.88			80.88
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	82.35			82.35
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.41			79.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.41			79.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.41			79.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.41			79.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.88			80.88

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.88			80.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T7,T8,T95	Yes	T7,T8,T95	INPUT
data_o[63:0]	Yes	Yes	T7,T8,T95	Yes	T7,T8,T95	OUTPUT
syndrome_o[2:0]	Yes	Yes	T105,T165,T157	Yes	T105,T165,T157	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T105,*T165,*T157	Yes	T105,T165,T157	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[5]	No	No		No		INPUT
data_i[8:6]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[15:13]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	INPUT
data_i[18:16]	No	No		No		INPUT
data_i[30:19]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[35:31]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T12,T120,T121	Yes	T8,T12,T120	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T12,*T120,*T121	Yes	T8,T12,T120	INPUT
data_i[40]	No	No		No		INPUT
data_i[51:41]	Yes	Yes	*T12,*T120,*T121	Yes	T8,T12,T120	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[55]	No	No		No		INPUT
data_i[59:56]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[60]	No	No		No		INPUT
data_i[61]	Yes	Yes	*T122,*T96,*T81	Yes	T121,T122,T96	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[1:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[8:6]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[15:13]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	OUTPUT
data_o[18:16]	No	No		No		OUTPUT
data_o[30:19]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[35:31]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T12,T120,T121	Yes	T8,T12,T120	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T12,*T120,*T121	Yes	T8,T12,T120	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[51:41]	Yes	Yes	*T12,*T120,*T121	Yes	T8,T12,T120	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[59:56]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[61]	Yes	Yes	*T122,*T96,*T81	Yes	T121,T122,T96	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[1]	No	No		No		INPUT
data_i[5:2]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[14:8]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[15]	No	No		No		INPUT
data_i[17:16]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[20:18]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[23]	No	No		No		INPUT
data_i[26:24]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[27]	No	No		No		INPUT
data_i[29:28]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[30]	No	No		No		INPUT
data_i[33:31]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[34]	No	No		No		INPUT
data_i[37:35]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[38]	No	No		No		INPUT
data_i[44:39]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[45]	No	No		No		INPUT
data_i[46]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[49]	No	No		No		INPUT
data_i[52:50]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[54:53]	No	No		No		INPUT
data_i[57:55]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[58]	No	No		No		INPUT
data_i[71:59]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[5:2]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[14:8]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[17:16]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[20:18]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[26:24]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[29:28]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[33:31]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[37:35]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[44:39]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[52:50]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[54:53]	No	No		No		OUTPUT
data_o[57:55]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[4:3]	No	No		No		INPUT
data_i[7:5]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[15:13]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[18]	No	No		No		INPUT
data_i[21:19]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[25]	No	No		No		INPUT
data_i[26]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[27]	No	No		No		INPUT
data_i[33:28]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[34]	No	No		No		INPUT
data_i[37:35]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[39:38]	No	No		No		INPUT
data_i[43:40]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[44]	No	No		No		INPUT
data_i[51:45]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[53]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[54]	No	No		No		INPUT
data_i[59:55]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[2:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[4:3]	No	No		No		OUTPUT
data_o[7:5]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[15:13]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[21:19]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[26]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[33:28]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[37:35]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[39:38]	No	No		No		OUTPUT
data_o[43:40]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[51:45]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[59:55]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[7]	No	No		No		INPUT
data_i[9:8]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[10]	No	No		No		INPUT
data_i[16:11]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[17]	No	No		No		INPUT
data_i[24:18]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[25]	No	No		No		INPUT
data_i[28:26]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[29]	No	No		No		INPUT
data_i[36:30]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[37]	No	No		No		INPUT
data_i[39:38]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[40]	No	No		No		INPUT
data_i[42:41]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[43]	No	No		No		INPUT
data_i[44]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[46:45]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[51]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[55]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[58:57]	No	No		No		INPUT
data_i[62:59]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T95,T155,T61	Yes	T95,T155,T61	INPUT
data_o[1:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[9:8]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[16:11]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[24:18]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[28:26]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[36:30]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[39:38]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[42:41]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[44]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[46:45]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[58:57]	No	No		No		OUTPUT
data_o[62:59]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[3]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[6]	No	No		No		INPUT
data_i[14:7]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[24:21]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[25]	No	No		No		INPUT
data_i[26]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[27]	No	No		No		INPUT
data_i[28]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[29]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[34:33]	No	No		No		INPUT
data_i[39:35]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	INPUT
data_i[40]	No	No		No		INPUT
data_i[44:41]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[46:45]	No	No		No		INPUT
data_i[54:47]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	INPUT
data_o[2:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[14:7]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[24:21]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[26]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[28]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[34:33]	No	No		No		OUTPUT
data_o[39:35]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[44:41]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[46:45]	No	No		No		OUTPUT
data_o[54:47]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	*T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[3]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[11]	No	No		No		INPUT
data_i[12]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[13]	No	No		No		INPUT
data_i[16:14]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[17]	No	No		No		INPUT
data_i[20:18]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	INPUT
data_i[21]	No	No		No		INPUT
data_i[26:22]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	INPUT
data_i[27]	No	No		No		INPUT
data_i[28]	Yes	Yes	*T8,*T12,*T95	Yes	T8,T12,T95	INPUT
data_i[29]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[34:33]	No	No		No		INPUT
data_i[35]	Yes	Yes	*T8,*T12,*T95	Yes	T8,T12,T95	INPUT
data_i[37:36]	No	No		No		INPUT
data_i[43:38]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[45:44]	No	No		No		INPUT
data_i[52:46]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[53]	No	No		No		INPUT
data_i[56:54]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[57]	No	No		No		INPUT
data_i[61:58]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	INPUT
data_o[2:0]	Yes	Yes	*T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[12]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[16:14]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[20:18]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	OUTPUT
data_o[21]	No	No		No		OUTPUT
data_o[26:22]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[28]	Yes	Yes	*T8,*T12,*T95	Yes	T8,T12,T95	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[34:33]	No	No		No		OUTPUT
data_o[35]	Yes	Yes	*T8,*T12,*T95	Yes	T8,T12,T95	OUTPUT
data_o[37:36]	No	No		No		OUTPUT
data_o[43:38]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[52:46]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[56:54]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[61:58]	Yes	Yes	*T2,*T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T8,T12,T95	Yes	T8,T12,T95	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	212	77.94
Total Bits 0->1	136	106	77.94
Total Bits 1->0	136	106	77.94

Ports	2	0	0.00
Port Bits	272	212	77.94
Port Bits 0->1	136	106	77.94
Port Bits 1->0	136	106	77.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T2,*T7,*T12	Yes	T2,T7,T8	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T2,*T7,*T12	Yes	T2,T7,T8	INPUT
data_i[5]	No	No		No		INPUT
data_i[22:6]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[23]	No	No		No		INPUT
data_i[26:24]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[28:27]	No	No		No		INPUT
data_i[31:29]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[32]	No	No		No		INPUT
data_i[44:33]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	INPUT
data_i[47:45]	No	No		No		INPUT
data_i[52:48]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[53]	No	No		No		INPUT
data_i[57:54]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[62:61]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T2,*T7,*T12	Yes	T2,T7,T8	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T2,*T7,*T12	Yes	T2,T7,T8	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[22:6]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[26:24]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[28:27]	No	No		No		OUTPUT
data_o[31:29]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[44:33]	Yes	Yes	*T2,T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[47:45]	No	No		No		OUTPUT
data_o[52:48]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[57:54]	Yes	Yes	T7,T12,T94	Yes	T7,T12,T94	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[62:61]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	216	79.41
Total Bits 0->1	136	108	79.41
Total Bits 1->0	136	108	79.41

Ports	2	0	0.00
Port Bits	272	216	79.41
Port Bits 0->1	136	108	79.41
Port Bits 1->0	136	108	79.41

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[3]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[6:5]	No	No		No		INPUT
data_i[12:7]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[13]	No	No		No		INPUT
data_i[16:14]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[17]	No	No		No		INPUT
data_i[19:18]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[33:25]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[34]	No	No		No		INPUT
data_i[37:35]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[38]	No	No		No		INPUT
data_i[42:39]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[58:53]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[59]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[2:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[6:5]	No	No		No		OUTPUT
data_o[12:7]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[16:14]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[19:18]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[33:25]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[37:35]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[42:39]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[58:53]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	216	79.41
Total Bits 0->1	136	108	79.41
Total Bits 1->0	136	108	79.41

Ports	2	0	0.00
Port Bits	272	216	79.41
Port Bits 0->1	136	108	79.41
Port Bits 1->0	136	108	79.41

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[4:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[5]	No	No		No		INPUT
data_i[10:6]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[11]	No	No		No		INPUT
data_i[15:12]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[22]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[25]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[35:30]	Yes	Yes	*T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[36]	No	No		No		INPUT
data_i[37]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T7,*T8,*T12	Yes	T7,T8,T12	INPUT
data_i[42]	No	No		No		INPUT
data_i[46:43]	Yes	Yes	*T7,*T8,*T12	Yes	T7,T8,T12	INPUT
data_i[47]	No	No		No		INPUT
data_i[71:48]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[4:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[10:6]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[15:12]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[22]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[35:30]	Yes	Yes	*T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[37]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T7,*T8,*T12	Yes	T7,T8,T12	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[46:43]	Yes	Yes	*T7,*T8,*T12	Yes	T7,T8,T12	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[63:48]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	220	80.88
Total Bits 0->1	136	110	80.88
Total Bits 1->0	136	110	80.88

Ports	2	0	0.00
Port Bits	272	220	80.88
Port Bits 0->1	136	110	80.88
Port Bits 1->0	136	110	80.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[1]	No	No		No		INPUT
data_i[8:2]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[10:9]	No	No		No		INPUT
data_i[17:11]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[18]	No	No		No		INPUT
data_i[25:19]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[36:28]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[37]	No	No		No		INPUT
data_i[39:38]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[40]	No	No		No		INPUT
data_i[43:41]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_i[44]	No	No		No		INPUT
data_i[52:45]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[55:53]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[57]	No	No		No		INPUT
data_i[71:58]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	INPUT
data_o[0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[8:2]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[10:9]	No	No		No		OUTPUT
data_o[17:11]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[25:19]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[36:28]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[39:38]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[43:41]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[52:45]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[55:53]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[63:58]	Yes	Yes	T7,T8,T12	Yes	T7,T8,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	224	82.35
Total Bits 0->1	136	112	82.35
Total Bits 1->0	136	112	82.35

Ports	2	0	0.00
Port Bits	272	224	82.35
Port Bits 0->1	136	112	82.35
Port Bits 1->0	136	112	82.35

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
data_i[1]	No	No		No		INPUT
data_i[9:2]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[12:10]	No	No		No		INPUT
data_i[15:13]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[16]	No	No		No		INPUT
data_i[22:17]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[23]	No	No		No		INPUT
data_i[29:24]	Yes	Yes	*T77,*T2,*T7	Yes	T77,T2,T7	INPUT
data_i[30]	No	No		No		INPUT
data_i[32:31]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[37:36]	No	No		No		INPUT
data_i[39:38]	Yes	Yes	*T77,*T2,*T7	Yes	T77,T2,T7	INPUT
data_i[40]	No	No		No		INPUT
data_i[49:41]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_i[50]	No	No		No		INPUT
data_i[71:51]	Yes	Yes	T77,T2,T7	Yes	T77,T2,T7	INPUT
data_o[0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[9:2]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[12:10]	No	No		No		OUTPUT
data_o[15:13]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[22:17]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[29:24]	Yes	Yes	*T77,*T2,*T7	Yes	T77,T2,T7	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[32:31]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[37:36]	No	No		No		OUTPUT
data_o[39:38]	Yes	Yes	*T77,*T2,*T7	Yes	T77,T2,T7	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[49:41]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[63:51]	Yes	Yes	T77,T2,T7	Yes	T77,T2,T7	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T95,T120	Yes	T7,T95,T120	INPUT
data_o[63:0]	Yes	Yes	T7,T95,T120	Yes	T7,T95,T120	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T8,T95,T120	Yes	T8,T95,T120	INPUT
data_o[63:0]	Yes	Yes	T8,T95,T120	Yes	T8,T95,T120	OUTPUT
syndrome_o[2:0]	Yes	Yes	T105	Yes	T105	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T105	Yes	T105	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T18,T127,T104	Yes	T18,T127,T104	INPUT
data_o[63:0]	Yes	Yes	T18,T127,T104	Yes	T18,T127,T104	OUTPUT
syndrome_o[2:0]	Yes	Yes	T105,T157,T158	Yes	T105,T157,T158	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T105,*T157,*T158	Yes	T105,T157,T158	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T19,T81,T127	Yes	T19,T81,T127	INPUT
data_o[63:0]	Yes	Yes	T19,T81,T127	Yes	T19,T81,T127	OUTPUT
syndrome_o[2:0]	Yes	Yes	T105,T165,T166	Yes	T105,T165,T166	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T105,*T165,*T166	Yes	T105,T165,T166	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T121,T19	Yes	T12,T121,T19	INPUT
data_o[63:0]	Yes	Yes	T12,T121,T19	Yes	T12,T121,T19	OUTPUT
syndrome_o[2:0]	Yes	Yes	T105,T165,T157	Yes	T105,T165,T157	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T105,*T165,*T157	Yes	T105,T165,T157	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T96,T193	Yes	T94,T96,T193	INPUT
data_o[63:0]	Yes	Yes	T94,T96,T193	Yes	T94,T96,T193	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T20,T234,T82	Yes	T20,T234,T82	INPUT
data_o[63:0]	Yes	Yes	T20,T234,T82	Yes	T20,T234,T82	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T189,T113,T116	Yes	T126,T189,T112	INPUT
data_o[63:0]	Yes	Yes	T189,T113,T116	Yes	T126,T189,T112	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T124,T61,T238	Yes	T156,T124,T61	INPUT
data_o[63:0]	Yes	Yes	T124,T61,T238	Yes	T156,T124,T61	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T265,T141,T64	Yes	T265,T141,T64	INPUT
data_o[63:0]	Yes	Yes	T265,T141,T64	Yes	T265,T141,T64	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T126,T96,T71	Yes	T126,T96,T71	INPUT
data_o[63:0]	Yes	Yes	T126,T96,T71	Yes	T126,T96,T71	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T266,T243,T267	Yes	T266,T268,T243	INPUT
data_o[63:0]	Yes	Yes	T266,T243,T267	Yes	T266,T268,T243	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T20,T71,T101	Yes	T20,T71,T229	INPUT
data_o[63:0]	Yes	Yes	T20,T71,T101	Yes	T20,T71,T229	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T120,T18	Yes	T91,T94,T126	INPUT
data_o[63:0]	Yes	Yes	T94,T120,T18	Yes	T91,T94,T126	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T4,T91	Yes	T2,T4,T91	INPUT
data_o[63:0]	Yes	Yes	T2,T4,T91	Yes	T2,T4,T91	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
data_o[63:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T126,T95	Yes	T2,T126,T95	INPUT
data_o[63:0]	Yes	Yes	T2,T126,T95	Yes	T2,T126,T95	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T91,T94	Yes	T2,T91,T94	INPUT
data_o[63:0]	Yes	Yes	T2,T91,T94	Yes	T2,T91,T94	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T19,T81	Yes	T12,T19,T81	INPUT
data_o[63:0]	Yes	Yes	T12,T19,T81	Yes	T12,T19,T81	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T91,T95,T96	Yes	T91,T126,T95	INPUT
data_o[63:0]	Yes	Yes	T91,T95,T96	Yes	T91,T126,T95	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T12,T95,T96	Yes	T12,T95,T96	INPUT
data_o[63:0]	Yes	Yes	T12,T95,T96	Yes	T12,T95,T96	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T121,T96,T19	Yes	T121,T96,T19	INPUT
data_o[63:0]	Yes	Yes	T121,T96,T19	Yes	T121,T96,T19	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T91,T94,T122	Yes	T91,T94,T126	INPUT
data_o[63:0]	Yes	Yes	T91,T94,T122	Yes	T91,T94,T126	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T94,T120	Yes	T2,T94,T120	INPUT
data_o[63:0]	Yes	Yes	T2,T94,T120	Yes	T2,T94,T120	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T129,T234,T82	Yes	T129,T269,T237	INPUT
data_o[63:0]	Yes	Yes	T129,T234,T82	Yes	T129,T269,T237	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T120,T155	Yes	T94,T120,T155	INPUT
data_o[63:0]	Yes	Yes	T94,T120,T155	Yes	T94,T120,T155	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T126,T96	Yes	T2,T126,T96	INPUT
data_o[63:0]	Yes	Yes	T2,T126,T96	Yes	T2,T126,T96	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T18,T96,T234	Yes	T18,T96,T234	INPUT
data_o[63:0]	Yes	Yes	T18,T96,T234	Yes	T18,T96,T234	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T19,T156	Yes	T94,T19,T156	INPUT
data_o[63:0]	Yes	Yes	T94,T19,T156	Yes	T94,T19,T156	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T142,T188,T234	Yes	T142,T188,T234	INPUT
data_o[63:0]	Yes	Yes	T142,T188,T234	Yes	T142,T188,T234	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T94,T20,T234	Yes	T94,T20,T234	INPUT
data_o[63:0]	Yes	Yes	T94,T20,T234	Yes	T94,T20,T234	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T123,T229,T192	Yes	T123,T237,T229	INPUT
data_o[63:0]	Yes	Yes	T123,T229,T192	Yes	T123,T237,T229	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T121,T129,T19	Yes	T2,T126,T121	INPUT
data_o[63:0]	Yes	Yes	T121,T129,T19	Yes	T2,T126,T121	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR