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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.76 93.74 96.13 95.93 91.17 96.96 96.28 93.14


Total test records in report: 1296
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T1064 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.256460705 Aug 25 02:11:05 PM UTC 24 Aug 25 02:11:17 PM UTC 24 268103193 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.331822882 Aug 25 02:11:12 PM UTC 24 Aug 25 02:11:17 PM UTC 24 439718210 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3193015949 Aug 25 02:11:06 PM UTC 24 Aug 25 02:11:17 PM UTC 24 427552539 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3827776876 Aug 25 02:11:05 PM UTC 24 Aug 25 02:11:17 PM UTC 24 191263948 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3465035132 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:18 PM UTC 24 403450842 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.2146550787 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:18 PM UTC 24 316838753 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.1611583877 Aug 25 02:11:05 PM UTC 24 Aug 25 02:11:19 PM UTC 24 618421609 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.3083446707 Aug 25 02:11:12 PM UTC 24 Aug 25 02:11:19 PM UTC 24 269647454 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.2056215313 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:19 PM UTC 24 158418319 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2784825517 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:19 PM UTC 24 289714317 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2164366629 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:19 PM UTC 24 288473453 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1799452307 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:19 PM UTC 24 2600578407 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2937993865 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:20 PM UTC 24 547383126 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2758162515 Aug 25 02:11:12 PM UTC 24 Aug 25 02:11:20 PM UTC 24 386141148 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2794450933 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:20 PM UTC 24 235025386 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2726055919 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:20 PM UTC 24 169811885 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.3328947829 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:20 PM UTC 24 1905213206 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1048953934 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:20 PM UTC 24 227269034 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1088967658 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:20 PM UTC 24 385104875 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3419446210 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:21 PM UTC 24 655870971 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1012198716 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:21 PM UTC 24 147868523 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.3159636889 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:21 PM UTC 24 175299296 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2518900651 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:21 PM UTC 24 132123195 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.1415810946 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:21 PM UTC 24 163117883 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2591888539 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:21 PM UTC 24 343920980 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1016345999 Aug 25 02:11:05 PM UTC 24 Aug 25 02:11:22 PM UTC 24 1610307314 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3844296227 Aug 25 02:11:14 PM UTC 24 Aug 25 02:11:23 PM UTC 24 2705071256 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.1906213524 Aug 25 02:11:05 PM UTC 24 Aug 25 02:11:24 PM UTC 24 924485009 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.1321035950 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:26 PM UTC 24 470137636 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.4027006959 Aug 25 02:10:54 PM UTC 24 Aug 25 02:11:26 PM UTC 24 866135311 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.1659673257 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:27 PM UTC 24 97541847 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.1452613265 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:28 PM UTC 24 132749728 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1311543850 Aug 25 02:11:05 PM UTC 24 Aug 25 02:11:28 PM UTC 24 2560822979 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1687271047 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:28 PM UTC 24 408320107 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.4234078336 Aug 25 02:11:23 PM UTC 24 Aug 25 02:11:28 PM UTC 24 122938761 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.4013023069 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:28 PM UTC 24 1753937288 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3041887301 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:28 PM UTC 24 333115381 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.4231071028 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:28 PM UTC 24 1266869748 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.3660664062 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:28 PM UTC 24 299462376 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.3587634546 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:28 PM UTC 24 250154840 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2532872947 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:29 PM UTC 24 151936363 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.2503608232 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 150047736 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3843533270 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 182556964 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3498318620 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 156526600 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.481088123 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 156857702 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2130120330 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 320388109 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.3257067250 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 426074119 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2859885011 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 158889511 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2182631646 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:29 PM UTC 24 729046693 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.857340051 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:29 PM UTC 24 2073017545 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.2700992078 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:29 PM UTC 24 546070227 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1570436058 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:29 PM UTC 24 476013964 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.3473640624 Aug 25 02:11:23 PM UTC 24 Aug 25 02:11:30 PM UTC 24 279870345 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.863804376 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:30 PM UTC 24 2837797093 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3797173662 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:30 PM UTC 24 194179662 ps
T1111 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.4208385008 Aug 25 02:11:23 PM UTC 24 Aug 25 02:11:30 PM UTC 24 415187060 ps
T1112 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.2620244071 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:30 PM UTC 24 2092438926 ps
T1113 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.1433726200 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:30 PM UTC 24 547218008 ps
T1114 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1039287926 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:30 PM UTC 24 2157830188 ps
T1115 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.1498481584 Aug 25 02:08:08 PM UTC 24 Aug 25 02:11:31 PM UTC 24 4569892462 ps
T1116 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.4260424258 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:31 PM UTC 24 416669299 ps
T1117 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.2198689020 Aug 25 02:11:21 PM UTC 24 Aug 25 02:11:31 PM UTC 24 2239465589 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1182049610 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:31 PM UTC 24 113767663 ps
T1118 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.2450117510 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:31 PM UTC 24 559584923 ps
T1119 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.3786809754 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:31 PM UTC 24 198380044 ps
T1120 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.707042042 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:31 PM UTC 24 138861340 ps
T1121 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.4107444726 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:32 PM UTC 24 155061856 ps
T1122 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.841107282 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:32 PM UTC 24 194941256 ps
T1123 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1185016553 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:32 PM UTC 24 1645329475 ps
T1124 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2830088486 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:32 PM UTC 24 1922998635 ps
T1125 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.3543157951 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:32 PM UTC 24 1664788044 ps
T1126 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2483726182 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:32 PM UTC 24 154909169 ps
T1127 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.383030633 Aug 25 02:11:27 PM UTC 24 Aug 25 02:11:33 PM UTC 24 180055583 ps
T1128 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.2645160556 Aug 25 02:11:27 PM UTC 24 Aug 25 02:11:33 PM UTC 24 191130079 ps
T1129 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.312710899 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 189815472 ps
T1130 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.1466071194 Aug 25 02:11:22 PM UTC 24 Aug 25 02:11:33 PM UTC 24 1996522151 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.106752785 Aug 25 02:11:06 PM UTC 24 Aug 25 02:11:34 PM UTC 24 2732549668 ps
T1131 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.2677672540 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:35 PM UTC 24 292003102 ps
T1132 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.1535133278 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:35 PM UTC 24 119063975 ps
T1133 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.211529575 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:35 PM UTC 24 479588141 ps
T1134 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.251470284 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:35 PM UTC 24 147256457 ps
T1135 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.2281362618 Aug 25 02:06:05 PM UTC 24 Aug 25 02:11:35 PM UTC 24 59721466055 ps
T1136 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.1615639420 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:35 PM UTC 24 208608787 ps
T1137 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3982155085 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:35 PM UTC 24 98235717 ps
T1138 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.2316344177 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:36 PM UTC 24 280172958 ps
T1139 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.923994187 Aug 25 02:11:25 PM UTC 24 Aug 25 02:11:36 PM UTC 24 2587951938 ps
T1140 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.1607728795 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:36 PM UTC 24 137368260 ps
T1141 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.3141588113 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:36 PM UTC 24 343904924 ps
T1142 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3729813355 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:36 PM UTC 24 585374093 ps
T1143 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3120422040 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:36 PM UTC 24 432542926 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2923974238 Aug 25 02:08:05 PM UTC 24 Aug 25 02:11:37 PM UTC 24 29757066231 ps
T1144 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3446820297 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:37 PM UTC 24 164310966 ps
T1145 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.3069618870 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:37 PM UTC 24 1622281842 ps
T1146 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3802856106 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:38 PM UTC 24 2143783560 ps
T1147 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3596234287 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:39 PM UTC 24 1972645645 ps
T1148 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.920161342 Aug 25 02:11:30 PM UTC 24 Aug 25 02:11:41 PM UTC 24 2315041407 ps
T1149 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1017398414 Aug 25 02:09:26 PM UTC 24 Aug 25 02:11:41 PM UTC 24 56746264973 ps
T1150 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.3912370086 Aug 25 02:11:11 PM UTC 24 Aug 25 02:11:42 PM UTC 24 1043078675 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.346686617 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:43 PM UTC 24 119104937 ps
T1151 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.914378591 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:43 PM UTC 24 179333125 ps
T1152 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2823206833 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:43 PM UTC 24 135455315 ps
T1153 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.2578380451 Aug 25 02:11:37 PM UTC 24 Aug 25 02:11:44 PM UTC 24 243972076 ps
T1154 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.3667609340 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:44 PM UTC 24 157885539 ps
T1155 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3951942601 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:44 PM UTC 24 120980693 ps
T1156 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1108167507 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:44 PM UTC 24 1336081934 ps
T1157 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.631357563 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:44 PM UTC 24 110113934 ps
T1158 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3572129798 Aug 25 02:11:37 PM UTC 24 Aug 25 02:11:44 PM UTC 24 160635875 ps
T1159 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1324288592 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 1745679604 ps
T1160 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.305040426 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 143097902 ps
T1161 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2942019259 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 236799826 ps
T1162 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3064543524 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 277307103 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.1479242503 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 533033786 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.302132409 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 328292705 ps
T1163 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2503089437 Aug 25 02:08:56 PM UTC 24 Aug 25 02:11:49 PM UTC 24 3675582458 ps
T1164 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3808115962 Aug 25 02:06:29 PM UTC 24 Aug 25 02:11:51 PM UTC 24 36572133754 ps
T1165 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.1423555785 Aug 25 02:06:38 PM UTC 24 Aug 25 02:11:57 PM UTC 24 34169244352 ps
T1166 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3090807167 Aug 25 02:11:05 PM UTC 24 Aug 25 02:12:03 PM UTC 24 16425083249 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1626726580 Aug 25 02:09:14 PM UTC 24 Aug 25 02:12:37 PM UTC 24 29981304841 ps
T1167 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.369745429 Aug 25 02:07:58 PM UTC 24 Aug 25 02:12:58 PM UTC 24 51979478470 ps
T1168 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.864282571 Aug 25 02:09:11 PM UTC 24 Aug 25 02:14:06 PM UTC 24 20496866049 ps
T1169 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.179148961 Aug 25 02:07:20 PM UTC 24 Aug 25 02:18:01 PM UTC 24 27987481965 ps
T1170 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2688532702 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:41 PM UTC 24 149800898 ps
T1171 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1598093143 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:42 PM UTC 24 145310990 ps
T1172 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.816609465 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:42 PM UTC 24 74389426 ps
T1173 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2944899004 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:42 PM UTC 24 75937922 ps
T1174 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2113217864 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:42 PM UTC 24 38857859 ps
T1175 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4060857890 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:42 PM UTC 24 73177816 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1794181946 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:42 PM UTC 24 601810833 ps
T1176 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.805815617 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:42 PM UTC 24 37322241 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3065334477 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:42 PM UTC 24 122869405 ps
T1177 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2535387882 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:43 PM UTC 24 38459593 ps
T1178 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.462110970 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:43 PM UTC 24 146765009 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1768596141 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:43 PM UTC 24 70037007 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2996563226 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:43 PM UTC 24 106440452 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2093117662 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:43 PM UTC 24 605602946 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3965536317 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:43 PM UTC 24 1148149330 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3681128865 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:43 PM UTC 24 1053270418 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1472868614 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:44 PM UTC 24 1060915061 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1559335974 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:44 PM UTC 24 121666941 ps
T1179 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1541409026 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:45 PM UTC 24 143922916 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.888480287 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:45 PM UTC 24 234184153 ps
T1180 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2511514749 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:45 PM UTC 24 80442423 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.21301089 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:46 PM UTC 24 381112928 ps
T1181 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2952713746 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:46 PM UTC 24 1201199307 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.873981603 Aug 25 02:11:38 PM UTC 24 Aug 25 02:11:48 PM UTC 24 3027523114 ps
T1182 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.1087835223 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:55 PM UTC 24 83122947 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1054017766 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:48 PM UTC 24 190452566 ps
T1183 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3579157277 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:48 PM UTC 24 1615872294 ps
T1184 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.382803640 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:49 PM UTC 24 93429937 ps
T1185 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.3817433736 Aug 25 02:11:46 PM UTC 24 Aug 25 02:11:49 PM UTC 24 41545155 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3263587579 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:56 PM UTC 24 613547102 ps
T1186 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2580492118 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:50 PM UTC 24 68724652 ps
T1187 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.149293737 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:50 PM UTC 24 72384378 ps
T1188 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2258336418 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:50 PM UTC 24 67863425 ps
T1189 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1703431575 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:50 PM UTC 24 105979338 ps
T1190 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2690338587 Aug 25 02:11:46 PM UTC 24 Aug 25 02:11:50 PM UTC 24 123128322 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4112836632 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:50 PM UTC 24 155518678 ps
T1191 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3268377972 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:51 PM UTC 24 66956871 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.170756116 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:51 PM UTC 24 541168982 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2106734116 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:51 PM UTC 24 43625484 ps
T1192 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1396298128 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:51 PM UTC 24 42584795 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.4122082811 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:51 PM UTC 24 357468262 ps
T1193 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1283371929 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:51 PM UTC 24 144443169 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1966581720 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:51 PM UTC 24 117386951 ps
T1194 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.4181229374 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:51 PM UTC 24 47403825 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.965868217 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:51 PM UTC 24 124646162 ps
T1195 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.398933415 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:52 PM UTC 24 77587588 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2548940023 Aug 25 02:11:46 PM UTC 24 Aug 25 02:11:52 PM UTC 24 160435958 ps
T1196 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3471074272 Aug 25 02:11:46 PM UTC 24 Aug 25 02:11:52 PM UTC 24 58810191 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3410778171 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:52 PM UTC 24 245920043 ps
T1197 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1883147298 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:52 PM UTC 24 111540635 ps
T1198 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1095354897 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:52 PM UTC 24 279967797 ps
T1199 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.4178870747 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:52 PM UTC 24 92264804 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1820338840 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:52 PM UTC 24 223772886 ps
T1200 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1667864639 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:52 PM UTC 24 62960146 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.72119447 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:52 PM UTC 24 211883405 ps
T1201 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1464758034 Aug 25 02:11:49 PM UTC 24 Aug 25 02:11:53 PM UTC 24 124923816 ps
T1202 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.4061298631 Aug 25 02:11:49 PM UTC 24 Aug 25 02:11:53 PM UTC 24 157338313 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2697766621 Aug 25 02:11:49 PM UTC 24 Aug 25 02:11:53 PM UTC 24 45743902 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.145489723 Aug 25 02:11:46 PM UTC 24 Aug 25 02:11:54 PM UTC 24 315593165 ps
T1203 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1451704367 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:54 PM UTC 24 398420720 ps
T1204 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.805509316 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:54 PM UTC 24 209389572 ps
T1205 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3568295831 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:54 PM UTC 24 59971600 ps
T1206 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3575103382 Aug 25 02:11:49 PM UTC 24 Aug 25 02:11:54 PM UTC 24 215487333 ps
T1207 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1939221691 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:54 PM UTC 24 132636770 ps
T1208 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.842442256 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:55 PM UTC 24 139141177 ps
T1209 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3746050691 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:55 PM UTC 24 126944022 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4125379038 Aug 25 02:11:47 PM UTC 24 Aug 25 02:11:55 PM UTC 24 235305444 ps
T1210 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.786459205 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:55 PM UTC 24 142358701 ps
T1211 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2767107389 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:56 PM UTC 24 1602023137 ps
T1212 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2136223179 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:56 PM UTC 24 493575429 ps
T1213 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.582296853 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:56 PM UTC 24 169513997 ps
T1214 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1008683994 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:56 PM UTC 24 87619198 ps
T1215 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3825707507 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:56 PM UTC 24 47613503 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2390779256 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:56 PM UTC 24 146099466 ps
T1216 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2611032752 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:56 PM UTC 24 1685250077 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.409474530 Aug 25 02:11:46 PM UTC 24 Aug 25 02:11:56 PM UTC 24 384807083 ps
T1217 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2127426196 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:56 PM UTC 24 136112660 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3674735419 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:57 PM UTC 24 625287547 ps
T1218 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1584437370 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:58 PM UTC 24 161298406 ps
T1219 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3296040704 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:58 PM UTC 24 231564532 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.435676893 Aug 25 02:11:39 PM UTC 24 Aug 25 02:11:59 PM UTC 24 4566722524 ps
T1220 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1638119513 Aug 25 02:11:52 PM UTC 24 Aug 25 02:11:59 PM UTC 24 298882543 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.373883380 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:59 PM UTC 24 640457202 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3963316711 Aug 25 02:11:48 PM UTC 24 Aug 25 02:11:59 PM UTC 24 1019442485 ps
T1221 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.562729469 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:00 PM UTC 24 138359665 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3581430379 Aug 25 02:11:39 PM UTC 24 Aug 25 02:12:00 PM UTC 24 4579368537 ps
T1222 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.966468518 Aug 25 02:11:52 PM UTC 24 Aug 25 02:12:01 PM UTC 24 1410733343 ps
T1223 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2718146127 Aug 25 02:11:47 PM UTC 24 Aug 25 02:12:01 PM UTC 24 493428216 ps
T1224 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2045572970 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:01 PM UTC 24 261369268 ps
T1225 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1813009359 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:01 PM UTC 24 42237839 ps
T1226 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2168708456 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:01 PM UTC 24 615874832 ps
T1227 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.4272556167 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:01 PM UTC 24 164333814 ps
T1228 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.109295063 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:02 PM UTC 24 566150736 ps
T1229 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.3829868563 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 146482389 ps
T1230 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3571623425 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:02 PM UTC 24 143205018 ps
T1231 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3776452153 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 37046425 ps
T1232 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3205731406 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 83415162 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.611794093 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 90615577 ps
T1233 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2417558806 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 73134074 ps
T1234 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3042593283 Aug 25 02:11:59 PM UTC 24 Aug 25 02:12:02 PM UTC 24 43183969 ps
T1235 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3879934791 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 54327632 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1369577247 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:02 PM UTC 24 567426881 ps
T1236 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.2170600146 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:03 PM UTC 24 518313107 ps
T1237 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.717532783 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:03 PM UTC 24 1115622687 ps
T1238 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2248239882 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:03 PM UTC 24 79041490 ps
T1239 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.881607268 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:03 PM UTC 24 344571423 ps
T1240 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1765999107 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:03 PM UTC 24 1095102157 ps
T1241 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1118795619 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:03 PM UTC 24 66136850 ps
T1242 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3291967989 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:04 PM UTC 24 320302708 ps
T1243 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2344319978 Aug 25 02:11:59 PM UTC 24 Aug 25 02:12:04 PM UTC 24 105745531 ps
T1244 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.393064173 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:04 PM UTC 24 1506093497 ps
T1245 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3044689250 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:05 PM UTC 24 151864633 ps
T1246 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1778670768 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:05 PM UTC 24 337664929 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3303574879 Aug 25 02:11:47 PM UTC 24 Aug 25 02:12:05 PM UTC 24 2089947205 ps
T1247 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3063543857 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:05 PM UTC 24 177887452 ps
T1248 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.483076766 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:05 PM UTC 24 1558042424 ps
T1249 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.349748116 Aug 25 02:11:57 PM UTC 24 Aug 25 02:12:06 PM UTC 24 810506568 ps
T1250 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3681390876 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:06 PM UTC 24 452360740 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1371987888 Aug 25 02:11:52 PM UTC 24 Aug 25 02:12:06 PM UTC 24 2535621161 ps
T1251 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2805439190 Aug 25 02:12:04 PM UTC 24 Aug 25 02:12:08 PM UTC 24 142676459 ps
T1252 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2410221857 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:08 PM UTC 24 521793245 ps
T1253 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.991317454 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:08 PM UTC 24 39455877 ps
T1254 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3310108560 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:09 PM UTC 24 75309243 ps
T1255 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.4237131597 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:09 PM UTC 24 39247244 ps
T1256 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2199775368 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:09 PM UTC 24 40644597 ps
T1257 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.43160737 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:09 PM UTC 24 72657279 ps
T1258 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.854238959 Aug 25 02:12:04 PM UTC 24 Aug 25 02:12:09 PM UTC 24 139505307 ps
T1259 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1053641889 Aug 25 02:12:05 PM UTC 24 Aug 25 02:12:09 PM UTC 24 75229945 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3050070190 Aug 25 02:11:58 PM UTC 24 Aug 25 02:12:09 PM UTC 24 188505681 ps
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