| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.76 | 93.74 | 96.13 | 95.93 | 91.17 | 96.96 | 96.28 | 93.14 |
| T1261 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.4085166020 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 37801907 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3300657724 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 78276616 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1159603431 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 36917112 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.252167437 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 42107584 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2303417545 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 48663660 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.342607860 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:11 PM UTC 24 | 57082813 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.327630267 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 580240745 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2121102668 | Aug 25 02:12:06 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 44202414 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3597507346 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 141398090 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.4152758895 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 80945496 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2285528686 | Aug 25 02:12:06 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 39742527 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3107517629 | Aug 25 02:12:04 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 68422330 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2985505762 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 547857225 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.1983954989 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 39104574 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.2337207399 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 152659598 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2851637945 | Aug 25 02:12:06 PM UTC 24 | Aug 25 02:12:09 PM UTC 24 | 75340246 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3270891607 | Aug 25 02:12:06 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 151000303 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3363180796 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 528074282 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1882388160 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 92737639 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2163374025 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 544511453 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.104465914 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 52372408 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4183565014 | Aug 25 02:12:04 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 205080276 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.408512884 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 45629304 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.861907491 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 71742430 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.806069938 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 75621460 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1359623488 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 50489551 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2544217435 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 113558507 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.126711547 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:10 PM UTC 24 | 61024985 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3389330447 | Aug 25 02:12:07 PM UTC 24 | Aug 25 02:12:11 PM UTC 24 | 146489121 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.2913640099 | Aug 25 02:12:06 PM UTC 24 | Aug 25 02:12:11 PM UTC 24 | 544930331 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.65051917 | Aug 25 02:12:04 PM UTC 24 | Aug 25 02:12:11 PM UTC 24 | 96065426 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4186374980 | Aug 25 02:11:47 PM UTC 24 | Aug 25 02:12:11 PM UTC 24 | 3012060341 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.366487179 | Aug 25 02:11:58 PM UTC 24 | Aug 25 02:12:13 PM UTC 24 | 715718871 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3493722449 | Aug 25 02:11:38 PM UTC 24 | Aug 25 02:12:13 PM UTC 24 | 20314610112 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1049219063 | Aug 25 02:12:04 PM UTC 24 | Aug 25 02:12:13 PM UTC 24 | 1674037657 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.639191640 | Aug 25 02:11:46 PM UTC 24 | Aug 25 02:12:14 PM UTC 24 | 5643237489 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.43895526 | Aug 25 02:11:52 PM UTC 24 | Aug 25 02:12:15 PM UTC 24 | 10395941579 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.331898242 | Aug 25 02:11:57 PM UTC 24 | Aug 25 02:12:17 PM UTC 24 | 2609768758 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.457767409 | Aug 25 02:11:52 PM UTC 24 | Aug 25 02:12:18 PM UTC 24 | 2316878325 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3723888399 | Aug 25 02:11:58 PM UTC 24 | Aug 25 02:12:20 PM UTC 24 | 10349596812 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3018736418 | Aug 25 02:11:57 PM UTC 24 | Aug 25 02:12:23 PM UTC 24 | 1242541247 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3543567647 | Aug 25 02:11:58 PM UTC 24 | Aug 25 02:12:25 PM UTC 24 | 1288195732 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1602200167 | Aug 25 02:11:58 PM UTC 24 | Aug 25 02:12:26 PM UTC 24 | 5366362150 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2323765222 | Aug 25 02:12:04 PM UTC 24 | Aug 25 02:12:36 PM UTC 24 | 10289348005 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3510383490 | Aug 25 02:11:49 PM UTC 24 | Aug 25 02:12:37 PM UTC 24 | 19063339659 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1115060984 | Aug 25 02:12:05 PM UTC 24 | Aug 25 02:12:46 PM UTC 24 | 4821560698 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.1579789894 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15256588165 ps |
| CPU time | 34.16 seconds |
| Started | Aug 25 01:53:39 PM UTC 24 |
| Finished | Aug 25 01:54:15 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579789894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.1579789894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.2023851405 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1158406272 ps |
| CPU time | 36.7 seconds |
| Started | Aug 25 01:54:01 PM UTC 24 |
| Finished | Aug 25 01:54:40 PM UTC 24 |
| Peak memory | 253560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023851405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2023851405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1838069212 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 21515269392 ps |
| CPU time | 67.32 seconds |
| Started | Aug 25 01:55:44 PM UTC 24 |
| Finished | Aug 25 01:56:53 PM UTC 24 |
| Peak memory | 268124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1838069212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.otp_ctrl_stress_all_with_rand_reset.1838069212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.87546115 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6953527395 ps |
| CPU time | 156.47 seconds |
| Started | Aug 25 01:55:50 PM UTC 24 |
| Finished | Aug 25 01:58:30 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87546115 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.87546115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.1889381887 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2944763100 ps |
| CPU time | 62.19 seconds |
| Started | Aug 25 01:54:18 PM UTC 24 |
| Finished | Aug 25 01:55:22 PM UTC 24 |
| Peak memory | 257904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889381887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1889381887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.1634252854 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 70181395319 ps |
| CPU time | 250.31 seconds |
| Started | Aug 25 01:54:58 PM UTC 24 |
| Finished | Aug 25 01:59:13 PM UTC 24 |
| Peak memory | 290324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634252854 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.1634252854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.62083169 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 205651247 ps |
| CPU time | 6.32 seconds |
| Started | Aug 25 02:04:36 PM UTC 24 |
| Finished | Aug 25 02:04:44 PM UTC 24 |
| Peak memory | 250980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62083169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.62083169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.977497024 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12612729015 ps |
| CPU time | 278.23 seconds |
| Started | Aug 25 01:54:58 PM UTC 24 |
| Finished | Aug 25 01:59:41 PM UTC 24 |
| Peak memory | 285884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977497024 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.977497024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2440735376 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 11589614367 ps |
| CPU time | 165.84 seconds |
| Started | Aug 25 01:57:57 PM UTC 24 |
| Finished | Aug 25 02:00:47 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440735376 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.2440735376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.3852686460 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2296352092 ps |
| CPU time | 35.84 seconds |
| Started | Aug 25 01:54:05 PM UTC 24 |
| Finished | Aug 25 01:54:42 PM UTC 24 |
| Peak memory | 268128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852686460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3852686460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.2658264408 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 225929389 ps |
| CPU time | 10.39 seconds |
| Started | Aug 25 01:56:46 PM UTC 24 |
| Finished | Aug 25 01:56:57 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658264408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2658264408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.2832606616 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 8680378291 ps |
| CPU time | 94.11 seconds |
| Started | Aug 25 01:55:24 PM UTC 24 |
| Finished | Aug 25 01:57:01 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832606616 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.2832606616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.2998707946 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1461548326 ps |
| CPU time | 27.57 seconds |
| Started | Aug 25 01:55:31 PM UTC 24 |
| Finished | Aug 25 01:56:01 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998707946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2998707946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1181887472 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 8779680353 ps |
| CPU time | 212.9 seconds |
| Started | Aug 25 02:00:54 PM UTC 24 |
| Finished | Aug 25 02:04:30 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1181887472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.otp_ctrl_stress_all_with_rand_reset.1181887472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.2283665690 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1491990771 ps |
| CPU time | 40.86 seconds |
| Started | Aug 25 01:56:49 PM UTC 24 |
| Finished | Aug 25 01:57:31 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283665690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2283665690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.3220801416 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 132655475 ps |
| CPU time | 5.51 seconds |
| Started | Aug 25 02:07:48 PM UTC 24 |
| Finished | Aug 25 02:07:54 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220801416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3220801416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.435676893 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4566722524 ps |
| CPU time | 18.98 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:59 PM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435676893 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.435676893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.3978311430 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 116779801638 ps |
| CPU time | 295.78 seconds |
| Started | Aug 25 01:59:01 PM UTC 24 |
| Finished | Aug 25 02:04:02 PM UTC 24 |
| Peak memory | 286424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978311430 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.3978311430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.675101898 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 912597579 ps |
| CPU time | 43.74 seconds |
| Started | Aug 25 01:54:34 PM UTC 24 |
| Finished | Aug 25 01:55:19 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675101898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.675101898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1986838102 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 567023390 ps |
| CPU time | 7.69 seconds |
| Started | Aug 25 01:58:49 PM UTC 24 |
| Finished | Aug 25 01:58:58 PM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986838102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1986838102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1928126737 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1745572396 ps |
| CPU time | 70.73 seconds |
| Started | Aug 25 01:59:14 PM UTC 24 |
| Finished | Aug 25 02:00:27 PM UTC 24 |
| Peak memory | 267736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1928126737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.1928126737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.2531568451 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 768241439 ps |
| CPU time | 25.26 seconds |
| Started | Aug 25 02:00:38 PM UTC 24 |
| Finished | Aug 25 02:01:05 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531568451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.2531568451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.2642912628 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 850339649 ps |
| CPU time | 23.41 seconds |
| Started | Aug 25 02:03:24 PM UTC 24 |
| Finished | Aug 25 02:03:49 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642912628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2642912628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1054017766 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 190452566 ps |
| CPU time | 7.94 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:48 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054017766 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.1054017766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.696762039 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3413982995 ps |
| CPU time | 105.14 seconds |
| Started | Aug 25 01:57:34 PM UTC 24 |
| Finished | Aug 25 01:59:22 PM UTC 24 |
| Peak memory | 255572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696762039 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.696762039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.427151250 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 314364604 ps |
| CPU time | 4.51 seconds |
| Started | Aug 25 02:00:57 PM UTC 24 |
| Finished | Aug 25 02:01:03 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427151250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.427151250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.3991481471 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2324246346 ps |
| CPU time | 8.73 seconds |
| Started | Aug 25 01:59:42 PM UTC 24 |
| Finished | Aug 25 01:59:52 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991481471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3991481471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.565915537 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 177667178 ps |
| CPU time | 3.22 seconds |
| Started | Aug 25 01:54:24 PM UTC 24 |
| Finished | Aug 25 01:54:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565915537 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.565915537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.828466408 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 20767940717 ps |
| CPU time | 225 seconds |
| Started | Aug 25 01:54:57 PM UTC 24 |
| Finished | Aug 25 01:58:46 PM UTC 24 |
| Peak memory | 268212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=828466408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.828466408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.354563932 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 163330196 ps |
| CPU time | 6.51 seconds |
| Started | Aug 25 01:55:02 PM UTC 24 |
| Finished | Aug 25 01:55:09 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354563932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.354563932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.877685118 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 268112067 ps |
| CPU time | 6.39 seconds |
| Started | Aug 25 02:02:03 PM UTC 24 |
| Finished | Aug 25 02:02:10 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877685118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.877685118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.2231972880 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7847781955 ps |
| CPU time | 141.33 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:10:33 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2231972880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.2231972880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.3739181318 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 15003769594 ps |
| CPU time | 284.74 seconds |
| Started | Aug 25 01:58:42 PM UTC 24 |
| Finished | Aug 25 02:03:33 PM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739181318 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.3739181318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.863804376 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2837797093 ps |
| CPU time | 6.78 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863804376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.863804376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.414808948 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2587094020 ps |
| CPU time | 62.89 seconds |
| Started | Aug 25 01:56:54 PM UTC 24 |
| Finished | Aug 25 01:57:59 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414808948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.414808948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.3282465102 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 250388420 ps |
| CPU time | 11.68 seconds |
| Started | Aug 25 02:00:13 PM UTC 24 |
| Finished | Aug 25 02:00:26 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282465102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3282465102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.1075076119 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 225696757 ps |
| CPU time | 7.01 seconds |
| Started | Aug 25 02:09:58 PM UTC 24 |
| Finished | Aug 25 02:10:06 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075076119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1075076119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1194314167 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 127832340 ps |
| CPU time | 7.07 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 250928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194314167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1194314167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.304510068 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 207980248 ps |
| CPU time | 5.73 seconds |
| Started | Aug 25 01:58:23 PM UTC 24 |
| Finished | Aug 25 01:58:30 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304510068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.304510068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.1910646469 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6591034301 ps |
| CPU time | 75.44 seconds |
| Started | Aug 25 01:55:40 PM UTC 24 |
| Finished | Aug 25 01:56:58 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910646469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1910646469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.546483963 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1607116925 ps |
| CPU time | 27.47 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:30 PM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546483963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.546483963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.2551824372 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 10313852784 ps |
| CPU time | 193.54 seconds |
| Started | Aug 25 02:05:01 PM UTC 24 |
| Finished | Aug 25 02:08:18 PM UTC 24 |
| Peak memory | 257728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551824372 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.2551824372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.1750320095 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 44053189638 ps |
| CPU time | 163.95 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:08:52 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750320095 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.1750320095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.3126520044 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4232141613 ps |
| CPU time | 10.43 seconds |
| Started | Aug 25 02:02:05 PM UTC 24 |
| Finished | Aug 25 02:02:17 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126520044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3126520044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.2619220482 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 107972426767 ps |
| CPU time | 372.33 seconds |
| Started | Aug 25 02:04:35 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 270236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619220482 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.2619220482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3519835299 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 57792159706 ps |
| CPU time | 411.97 seconds |
| Started | Aug 25 02:00:27 PM UTC 24 |
| Finished | Aug 25 02:07:26 PM UTC 24 |
| Peak memory | 306680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519835299 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.3519835299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.524713515 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 329762685 ps |
| CPU time | 9.5 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:17 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524713515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.524713515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.462877493 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 38050486618 ps |
| CPU time | 187.22 seconds |
| Started | Aug 25 01:54:20 PM UTC 24 |
| Finished | Aug 25 01:57:31 PM UTC 24 |
| Peak memory | 253560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462877493 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.462877493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.934403269 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1617356290 ps |
| CPU time | 18.56 seconds |
| Started | Aug 25 01:55:07 PM UTC 24 |
| Finished | Aug 25 01:55:27 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934403269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.934403269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.279370931 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6887795410 ps |
| CPU time | 102.18 seconds |
| Started | Aug 25 01:56:29 PM UTC 24 |
| Finished | Aug 25 01:58:13 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=279370931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.279370931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.3798993078 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 110461227 ps |
| CPU time | 6.07 seconds |
| Started | Aug 25 02:03:19 PM UTC 24 |
| Finished | Aug 25 02:03:26 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798993078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3798993078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.2083159342 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 22554539556 ps |
| CPU time | 258.96 seconds |
| Started | Aug 25 02:00:43 PM UTC 24 |
| Finished | Aug 25 02:05:07 PM UTC 24 |
| Peak memory | 273880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083159342 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.2083159342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.3402751518 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 503870703 ps |
| CPU time | 7.97 seconds |
| Started | Aug 25 01:53:38 PM UTC 24 |
| Finished | Aug 25 01:53:47 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402751518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3402751518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2841405757 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 173751920 ps |
| CPU time | 4.94 seconds |
| Started | Aug 25 01:54:29 PM UTC 24 |
| Finished | Aug 25 01:54:35 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841405757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2841405757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.2111110689 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 283600948 ps |
| CPU time | 12.5 seconds |
| Started | Aug 25 01:56:59 PM UTC 24 |
| Finished | Aug 25 01:57:13 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111110689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2111110689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.3863292914 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1174800317 ps |
| CPU time | 13.9 seconds |
| Started | Aug 25 01:59:18 PM UTC 24 |
| Finished | Aug 25 01:59:33 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863292914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3863292914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1768596141 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 70037007 ps |
| CPU time | 2.49 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768596141 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1768596141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.27039955 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 10964888513 ps |
| CPU time | 97.29 seconds |
| Started | Aug 25 02:06:04 PM UTC 24 |
| Finished | Aug 25 02:07:44 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=27039955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.27039955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.149106120 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1053804475 ps |
| CPU time | 20.22 seconds |
| Started | Aug 25 01:53:17 PM UTC 24 |
| Finished | Aug 25 01:53:38 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149106120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.149106120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.3970006805 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1517073255 ps |
| CPU time | 5.82 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:52 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970006805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3970006805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.2056215313 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 158418319 ps |
| CPU time | 5.96 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:19 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056215313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2056215313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3493722449 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 20314610112 ps |
| CPU time | 32.93 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:12:13 PM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493722449 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.3493722449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1635539583 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1815039069 ps |
| CPU time | 8.57 seconds |
| Started | Aug 25 02:09:31 PM UTC 24 |
| Finished | Aug 25 02:09:41 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635539583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1635539583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.1191341239 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 787648392 ps |
| CPU time | 6.79 seconds |
| Started | Aug 25 01:59:55 PM UTC 24 |
| Finished | Aug 25 02:00:03 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191341239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1191341239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.413874415 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 174514748 ps |
| CPU time | 6.74 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413874415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.413874415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2937993865 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 547383126 ps |
| CPU time | 4.14 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937993865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2937993865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.3271263036 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 18785664125 ps |
| CPU time | 139.95 seconds |
| Started | Aug 25 02:02:55 PM UTC 24 |
| Finished | Aug 25 02:05:19 PM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271263036 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.3271263036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.179148961 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 27987481965 ps |
| CPU time | 632.73 seconds |
| Started | Aug 25 02:07:20 PM UTC 24 |
| Finished | Aug 25 02:18:01 PM UTC 24 |
| Peak memory | 269812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179148961 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.179148961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.2449968890 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 10723374069 ps |
| CPU time | 42.39 seconds |
| Started | Aug 25 01:55:18 PM UTC 24 |
| Finished | Aug 25 01:56:02 PM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449968890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2449968890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.4150597287 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1799430152 ps |
| CPU time | 25.23 seconds |
| Started | Aug 25 02:03:50 PM UTC 24 |
| Finished | Aug 25 02:04:17 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150597287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.4150597287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.534190313 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 19412623483 ps |
| CPU time | 308.35 seconds |
| Started | Aug 25 02:00:02 PM UTC 24 |
| Finished | Aug 25 02:05:20 PM UTC 24 |
| Peak memory | 274012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=534190313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.534190313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.2828454235 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 305501941 ps |
| CPU time | 10.45 seconds |
| Started | Aug 25 02:00:01 PM UTC 24 |
| Finished | Aug 25 02:00:17 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828454235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2828454235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.457767409 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2316878325 ps |
| CPU time | 24.43 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:12:18 PM UTC 24 |
| Peak memory | 252888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457767409 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.457767409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.2204021044 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1463272421 ps |
| CPU time | 29.58 seconds |
| Started | Aug 25 01:55:37 PM UTC 24 |
| Finished | Aug 25 01:56:09 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204021044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2204021044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.3744023867 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1273299092 ps |
| CPU time | 37.77 seconds |
| Started | Aug 25 02:00:18 PM UTC 24 |
| Finished | Aug 25 02:00:59 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744023867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3744023867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3330585604 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 659295914 ps |
| CPU time | 27.13 seconds |
| Started | Aug 25 02:04:16 PM UTC 24 |
| Finished | Aug 25 02:04:45 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330585604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3330585604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.43895526 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 10395941579 ps |
| CPU time | 21.85 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:12:15 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43895526 -assert nopostproc +UVM_TESTN AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.43895526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.1440572122 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 12084888339 ps |
| CPU time | 209.01 seconds |
| Started | Aug 25 02:06:27 PM UTC 24 |
| Finished | Aug 25 02:10:00 PM UTC 24 |
| Peak memory | 274348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1440572122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.otp_ctrl_stress_all_with_rand_reset.1440572122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.2676609157 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 830425102 ps |
| CPU time | 38.75 seconds |
| Started | Aug 25 01:57:46 PM UTC 24 |
| Finished | Aug 25 01:58:26 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676609157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2676609157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.37702053 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 25508486478 ps |
| CPU time | 503.32 seconds |
| Started | Aug 25 01:57:05 PM UTC 24 |
| Finished | Aug 25 02:05:36 PM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37702053 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.37702053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.2978919122 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 126150376 ps |
| CPU time | 4.78 seconds |
| Started | Aug 25 02:09:32 PM UTC 24 |
| Finished | Aug 25 02:09:38 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978919122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2978919122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.1522875652 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 566825302 ps |
| CPU time | 5.83 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522875652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1522875652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.2922060933 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1622392940 ps |
| CPU time | 5.19 seconds |
| Started | Aug 25 02:09:39 PM UTC 24 |
| Finished | Aug 25 02:09:45 PM UTC 24 |
| Peak memory | 253236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922060933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2922060933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2223497007 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 111179131 ps |
| CPU time | 6.43 seconds |
| Started | Aug 25 02:09:50 PM UTC 24 |
| Finished | Aug 25 02:09:57 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223497007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2223497007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.73953367 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 105304001 ps |
| CPU time | 5.66 seconds |
| Started | Aug 25 02:10:08 PM UTC 24 |
| Finished | Aug 25 02:10:14 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73953367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.73953367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2027658637 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1064472582 ps |
| CPU time | 10.56 seconds |
| Started | Aug 25 01:57:30 PM UTC 24 |
| Finished | Aug 25 01:57:42 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027658637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2027658637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3353900411 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1331064730 ps |
| CPU time | 37.89 seconds |
| Started | Aug 25 01:58:30 PM UTC 24 |
| Finished | Aug 25 01:59:10 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353900411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3353900411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.873981603 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3027523114 ps |
| CPU time | 7.86 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:48 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873981603 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.873981603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3881572179 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 308313101 ps |
| CPU time | 6.3 seconds |
| Started | Aug 25 01:54:36 PM UTC 24 |
| Finished | Aug 25 01:54:44 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881572179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3881572179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.1639668336 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1912197754 ps |
| CPU time | 34.72 seconds |
| Started | Aug 25 01:54:16 PM UTC 24 |
| Finished | Aug 25 01:54:52 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639668336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1639668336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.471950845 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 523591510 ps |
| CPU time | 16.06 seconds |
| Started | Aug 25 01:55:21 PM UTC 24 |
| Finished | Aug 25 01:55:39 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471950845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.471950845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2626357743 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 142531002 ps |
| CPU time | 2.7 seconds |
| Started | Aug 25 01:53:16 PM UTC 24 |
| Finished | Aug 25 01:53:20 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626357743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2626357743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.3414661815 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2927103690 ps |
| CPU time | 15.81 seconds |
| Started | Aug 25 01:58:00 PM UTC 24 |
| Finished | Aug 25 01:58:17 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414661815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3414661815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.1294444815 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 6215609234 ps |
| CPU time | 52.17 seconds |
| Started | Aug 25 01:59:47 PM UTC 24 |
| Finished | Aug 25 02:00:41 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294444815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1294444815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.731236637 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 12171961161 ps |
| CPU time | 190.96 seconds |
| Started | Aug 25 02:01:04 PM UTC 24 |
| Finished | Aug 25 02:04:18 PM UTC 24 |
| Peak memory | 288632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731236637 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.731236637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.2271147923 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 448793808 ps |
| CPU time | 4.14 seconds |
| Started | Aug 25 02:01:07 PM UTC 24 |
| Finished | Aug 25 02:01:13 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271147923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2271147923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1602200167 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5366362150 ps |
| CPU time | 26.04 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:26 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602200167 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.1602200167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.563260014 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2810553864 ps |
| CPU time | 10 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:05 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563260014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.563260014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.1594365203 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 35818223888 ps |
| CPU time | 363.35 seconds |
| Started | Aug 25 01:59:39 PM UTC 24 |
| Finished | Aug 25 02:05:48 PM UTC 24 |
| Peak memory | 304692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594365203 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.1594365203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.2366160676 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 300950057 ps |
| CPU time | 6.13 seconds |
| Started | Aug 25 02:00:18 PM UTC 24 |
| Finished | Aug 25 02:00:26 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366160676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2366160676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.3259132060 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 230586050 ps |
| CPU time | 4.39 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:01 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259132060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3259132060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.4022566722 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2756800607 ps |
| CPU time | 43.63 seconds |
| Started | Aug 25 01:56:15 PM UTC 24 |
| Finished | Aug 25 01:57:00 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022566722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.4022566722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.2898756109 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 12293165149 ps |
| CPU time | 39.62 seconds |
| Started | Aug 25 01:54:44 PM UTC 24 |
| Finished | Aug 25 01:55:26 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898756109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2898756109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.2314936744 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2562652456 ps |
| CPU time | 6.68 seconds |
| Started | Aug 25 02:10:09 PM UTC 24 |
| Finished | Aug 25 02:10:17 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314936744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2314936744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.3736291597 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 10567956897 ps |
| CPU time | 42.86 seconds |
| Started | Aug 25 01:54:45 PM UTC 24 |
| Finished | Aug 25 01:55:29 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736291597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3736291597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.1638363639 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 8911993264 ps |
| CPU time | 219.58 seconds |
| Started | Aug 25 01:59:14 PM UTC 24 |
| Finished | Aug 25 02:02:59 PM UTC 24 |
| Peak memory | 267760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638363639 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.1638363639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.888480287 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 234184153 ps |
| CPU time | 5.44 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888480287 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.888480287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3681128865 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1053270418 ps |
| CPU time | 3.79 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681128865 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.3681128865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3965536317 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1148149330 ps |
| CPU time | 3.63 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 258836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3965536317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.3965536317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1794181946 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 601810833 ps |
| CPU time | 2.79 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794181946 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1794181946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2688532702 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 149800898 ps |
| CPU time | 2.23 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:41 PM UTC 24 |
| Peak memory | 241888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688532702 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2688532702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.816609465 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 74389426 ps |
| CPU time | 2.08 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 242328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816609465 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.816609465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1598093143 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 145310990 ps |
| CPU time | 2.06 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 241724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598093143 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.1598093143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1472868614 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1060915061 ps |
| CPU time | 3.88 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472868614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.1472868614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2952713746 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 1201199307 ps |
| CPU time | 6.73 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:46 PM UTC 24 |
| Peak memory | 259012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952713746 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2952713746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.21301089 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 381112928 ps |
| CPU time | 6.01 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:46 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21301089 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.21301089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3065334477 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 122869405 ps |
| CPU time | 2.46 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065334477 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.3065334477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3579157277 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 1615872294 ps |
| CPU time | 8.32 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:48 PM UTC 24 |
| Peak memory | 258880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3579157277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.3579157277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2093117662 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 605602946 ps |
| CPU time | 3.29 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093117662 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2093117662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2944899004 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 75937922 ps |
| CPU time | 2.26 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 241868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944899004 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2944899004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2113217864 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 38857859 ps |
| CPU time | 2.16 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 242132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113217864 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.2113217864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4060857890 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 73177816 ps |
| CPU time | 2.16 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 241724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060857890 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.4060857890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1559335974 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 121666941 ps |
| CPU time | 3.7 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 254876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559335974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.1559335974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2511514749 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 80442423 ps |
| CPU time | 5.31 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 259132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511514749 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2511514749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.582296853 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 169513997 ps |
| CPU time | 2.36 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=582296853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_cs r_mem_rw_with_rand_reset.582296853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3825707507 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 47613503 ps |
| CPU time | 2.64 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 254736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825707507 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3825707507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.786459205 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 142358701 ps |
| CPU time | 2.11 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:55 PM UTC 24 |
| Peak memory | 242672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786459205 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.786459205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1008683994 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 87619198 ps |
| CPU time | 2.55 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008683994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.1008683994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1638119513 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 298882543 ps |
| CPU time | 5.78 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:59 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638119513 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1638119513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.393064173 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 1506093497 ps |
| CPU time | 5.57 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:04 PM UTC 24 |
| Peak memory | 258880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=393064173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_cs r_mem_rw_with_rand_reset.393064173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2390779256 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 146099466 ps |
| CPU time | 2.43 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390779256 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2390779256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.1087835223 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 83122947 ps |
| CPU time | 1.96 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:55 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087835223 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1087835223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2045572970 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 261369268 ps |
| CPU time | 2.62 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:01 PM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045572970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.2045572970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1584437370 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 161298406 ps |
| CPU time | 4.6 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:58 PM UTC 24 |
| Peak memory | 259088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584437370 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1584437370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1371987888 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2535621161 ps |
| CPU time | 12.2 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:12:06 PM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371987888 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.1371987888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1765999107 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 1095102157 ps |
| CPU time | 4.55 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1765999107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.1765999107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2168708456 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 615874832 ps |
| CPU time | 3.04 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:01 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168708456 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2168708456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.562729469 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 138359665 ps |
| CPU time | 1.75 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:00 PM UTC 24 |
| Peak memory | 241288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562729469 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.562729469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3571623425 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 143205018 ps |
| CPU time | 3.11 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571623425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.3571623425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3063543857 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 177887452 ps |
| CPU time | 6.54 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:05 PM UTC 24 |
| Peak memory | 259004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063543857 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3063543857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.331898242 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2609768758 ps |
| CPU time | 18.97 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:17 PM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331898242 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.331898242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.881607268 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 344571423 ps |
| CPU time | 4.03 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=881607268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_cs r_mem_rw_with_rand_reset.881607268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.109295063 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 566150736 ps |
| CPU time | 2.38 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 254744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109295063 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.109295063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1813009359 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 42237839 ps |
| CPU time | 2.25 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:01 PM UTC 24 |
| Peak memory | 242480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813009359 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1813009359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3044689250 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 151864633 ps |
| CPU time | 5.4 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:05 PM UTC 24 |
| Peak memory | 254716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044689250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.3044689250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.349748116 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 810506568 ps |
| CPU time | 6.5 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:06 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349748116 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.349748116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3018736418 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 1242541247 ps |
| CPU time | 23.59 seconds |
| Started | Aug 25 02:11:57 PM UTC 24 |
| Finished | Aug 25 02:12:23 PM UTC 24 |
| Peak memory | 257116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018736418 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.3018736418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.483076766 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 1558042424 ps |
| CPU time | 5.57 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:05 PM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=483076766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_cs r_mem_rw_with_rand_reset.483076766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1369577247 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 567426881 ps |
| CPU time | 3.08 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369577247 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1369577247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.4272556167 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 164333814 ps |
| CPU time | 2.07 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:01 PM UTC 24 |
| Peak memory | 242456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272556167 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4272556167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.717532783 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 1115622687 ps |
| CPU time | 3.58 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 254688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717532783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.717532783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3291967989 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 320302708 ps |
| CPU time | 4.26 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:04 PM UTC 24 |
| Peak memory | 259008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291967989 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3291967989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3543567647 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 1288195732 ps |
| CPU time | 25.81 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:25 PM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543567647 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.3543567647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3205731406 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 83415162 ps |
| CPU time | 2.24 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 256800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3205731406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.3205731406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.611794093 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 90615577 ps |
| CPU time | 2.29 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 254860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611794093 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.611794093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.3829868563 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 146482389 ps |
| CPU time | 2.08 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 242204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829868563 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3829868563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3681390876 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 452360740 ps |
| CPU time | 5.93 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:06 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681390876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.3681390876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1118795619 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 66136850 ps |
| CPU time | 3.72 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118795619 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1118795619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2417558806 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 73134074 ps |
| CPU time | 2.26 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 256792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2417558806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.2417558806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3879934791 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 54327632 ps |
| CPU time | 2.44 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 254532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879934791 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3879934791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3776452153 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 37046425 ps |
| CPU time | 1.92 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776452153 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3776452153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2248239882 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 79041490 ps |
| CPU time | 3.08 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 254808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248239882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.2248239882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3050070190 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 188505681 ps |
| CPU time | 8.82 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 259196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050070190 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3050070190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3723888399 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 10349596812 ps |
| CPU time | 19.66 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:20 PM UTC 24 |
| Peak memory | 257068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723888399 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.3723888399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4183565014 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 205080276 ps |
| CPU time | 4.35 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4183565014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.4183565014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3042593283 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 43183969 ps |
| CPU time | 2.24 seconds |
| Started | Aug 25 02:11:59 PM UTC 24 |
| Finished | Aug 25 02:12:02 PM UTC 24 |
| Peak memory | 252800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042593283 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3042593283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.2170600146 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 518313107 ps |
| CPU time | 2.77 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 241716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170600146 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2170600146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2344319978 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 105745531 ps |
| CPU time | 3.58 seconds |
| Started | Aug 25 02:11:59 PM UTC 24 |
| Finished | Aug 25 02:12:04 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344319978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.2344319978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1778670768 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 337664929 ps |
| CPU time | 4.51 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:05 PM UTC 24 |
| Peak memory | 258836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778670768 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1778670768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.366487179 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 715718871 ps |
| CPU time | 12.44 seconds |
| Started | Aug 25 02:11:58 PM UTC 24 |
| Finished | Aug 25 02:12:13 PM UTC 24 |
| Peak memory | 256720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366487179 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.366487179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1049219063 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 1674037657 ps |
| CPU time | 6.93 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:13 PM UTC 24 |
| Peak memory | 258544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1049219063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.1049219063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.854238959 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 139505307 ps |
| CPU time | 2.73 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854238959 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.854238959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2805439190 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 142676459 ps |
| CPU time | 1.91 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:08 PM UTC 24 |
| Peak memory | 240968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805439190 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2805439190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3107517629 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 68422330 ps |
| CPU time | 3.15 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107517629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.3107517629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.65051917 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 96065426 ps |
| CPU time | 4.99 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:11 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65051917 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.65051917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2323765222 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 10289348005 ps |
| CPU time | 29.33 seconds |
| Started | Aug 25 02:12:04 PM UTC 24 |
| Finished | Aug 25 02:12:36 PM UTC 24 |
| Peak memory | 256856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323765222 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.2323765222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2544217435 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 113558507 ps |
| CPU time | 4.25 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 258888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2544217435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.2544217435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.43160737 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 72657279 ps |
| CPU time | 2.51 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43160737 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.43160737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3310108560 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 75309243 ps |
| CPU time | 2.35 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310108560 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3310108560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1882388160 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 92737639 ps |
| CPU time | 3.68 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882388160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.1882388160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.342607860 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 57082813 ps |
| CPU time | 4.62 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:11 PM UTC 24 |
| Peak memory | 259108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342607860 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.342607860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1115060984 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4821560698 ps |
| CPU time | 39.27 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:46 PM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115060984 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1115060984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.409474530 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 384807083 ps |
| CPU time | 8.72 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 242480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409474530 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.409474530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.145489723 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 315593165 ps |
| CPU time | 6.32 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:11:54 PM UTC 24 |
| Peak memory | 242388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145489723 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.145489723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2996563226 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 106440452 ps |
| CPU time | 2.72 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996563226 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.2996563226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2690338587 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 123128322 ps |
| CPU time | 2.66 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:11:50 PM UTC 24 |
| Peak memory | 256960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2690338587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.2690338587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.462110970 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 146765009 ps |
| CPU time | 2.39 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 242672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462110970 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.462110970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2535387882 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 38459593 ps |
| CPU time | 2.17 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 241152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535387882 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.2535387882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.805815617 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 37322241 ps |
| CPU time | 2.14 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 241232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805815617 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.805815617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2548940023 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 160435958 ps |
| CPU time | 4.27 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548940023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.2548940023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1541409026 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 143922916 ps |
| CPU time | 4.73 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541409026 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.1541409026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3581430379 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4579368537 ps |
| CPU time | 19.99 seconds |
| Started | Aug 25 02:11:39 PM UTC 24 |
| Finished | Aug 25 02:12:00 PM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581430379 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.3581430379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.991317454 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 39455877 ps |
| CPU time | 2.23 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:08 PM UTC 24 |
| Peak memory | 241912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991317454 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.991317454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2410221857 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 521793245 ps |
| CPU time | 2.02 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:08 PM UTC 24 |
| Peak memory | 242608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410221857 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2410221857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1053641889 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 75229945 ps |
| CPU time | 2.36 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053641889 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1053641889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3300657724 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 78276616 ps |
| CPU time | 2.25 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300657724 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3300657724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.327630267 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 580240745 ps |
| CPU time | 2.47 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327630267 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.327630267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.4085166020 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 37801907 ps |
| CPU time | 2.27 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085166020 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.4085166020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2303417545 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 48663660 ps |
| CPU time | 2.28 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303417545 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2303417545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.252167437 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 42107584 ps |
| CPU time | 2.24 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252167437 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.252167437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3363180796 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 528074282 ps |
| CPU time | 2.97 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363180796 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3363180796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.4237131597 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 39247244 ps |
| CPU time | 1.95 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237131597 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.4237131597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3263587579 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 613547102 ps |
| CPU time | 7.59 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263587579 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.3263587579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4125379038 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 235305444 ps |
| CPU time | 7.29 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:55 PM UTC 24 |
| Peak memory | 242444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125379038 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.4125379038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.4122082811 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 357468262 ps |
| CPU time | 3.41 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122082811 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.4122082811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1095354897 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 279967797 ps |
| CPU time | 3.92 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 259072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1095354897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.1095354897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4112836632 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 155518678 ps |
| CPU time | 2.41 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:50 PM UTC 24 |
| Peak memory | 254924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112836632 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.4112836632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.3817433736 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 41545155 ps |
| CPU time | 1.87 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:11:49 PM UTC 24 |
| Peak memory | 241764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817433736 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3817433736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2580492118 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 68724652 ps |
| CPU time | 1.79 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:50 PM UTC 24 |
| Peak memory | 240540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580492118 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.2580492118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.382803640 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 93429937 ps |
| CPU time | 1.5 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:49 PM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382803640 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.382803640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1966581720 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 117386951 ps |
| CPU time | 3.52 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 254712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966581720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.1966581720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3471074272 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 58810191 ps |
| CPU time | 4.32 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471074272 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3471074272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.639191640 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5643237489 ps |
| CPU time | 26.36 seconds |
| Started | Aug 25 02:11:46 PM UTC 24 |
| Finished | Aug 25 02:12:14 PM UTC 24 |
| Peak memory | 258976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639191640 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.639191640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2199775368 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 40644597 ps |
| CPU time | 1.88 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199775368 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2199775368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1159603431 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 36917112 ps |
| CPU time | 2.08 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159603431 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1159603431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2163374025 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 544511453 ps |
| CPU time | 3 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163374025 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2163374025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.4152758895 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 80945496 ps |
| CPU time | 2.2 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152758895 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.4152758895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2985505762 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 547857225 ps |
| CPU time | 2.26 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985505762 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2985505762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3597507346 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 141398090 ps |
| CPU time | 2.19 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597507346 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3597507346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.1983954989 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 39104574 ps |
| CPU time | 2.18 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983954989 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1983954989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.2337207399 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 152659598 ps |
| CPU time | 2.46 seconds |
| Started | Aug 25 02:12:05 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337207399 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2337207399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2851637945 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 75340246 ps |
| CPU time | 2.27 seconds |
| Started | Aug 25 02:12:06 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 242480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851637945 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2851637945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2121102668 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 44202414 ps |
| CPU time | 2.22 seconds |
| Started | Aug 25 02:12:06 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121102668 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2121102668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1939221691 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 132636770 ps |
| CPU time | 5.74 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:54 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939221691 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.1939221691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2718146127 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 493428216 ps |
| CPU time | 12.03 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:12:01 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718146127 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.2718146127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.72119447 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 211883405 ps |
| CPU time | 4.02 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72119447 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.72119447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.4178870747 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 92264804 ps |
| CPU time | 3.68 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 258976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4178870747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.4178870747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.170756116 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 541168982 ps |
| CPU time | 2.54 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 254200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170756116 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.170756116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.149293737 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 72384378 ps |
| CPU time | 1.8 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:50 PM UTC 24 |
| Peak memory | 241464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149293737 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.149293737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1703431575 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 105979338 ps |
| CPU time | 1.74 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:50 PM UTC 24 |
| Peak memory | 240272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703431575 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.1703431575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2258336418 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 67863425 ps |
| CPU time | 1.85 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:50 PM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258336418 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.2258336418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.965868217 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 124646162 ps |
| CPU time | 3.04 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965868217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.965868217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1883147298 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 111540635 ps |
| CPU time | 3.77 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883147298 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1883147298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3303574879 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2089947205 ps |
| CPU time | 16.34 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:12:05 PM UTC 24 |
| Peak memory | 256840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303574879 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.3303574879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.2913640099 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 544930331 ps |
| CPU time | 3.37 seconds |
| Started | Aug 25 02:12:06 PM UTC 24 |
| Finished | Aug 25 02:12:11 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913640099 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2913640099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3270891607 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 151000303 ps |
| CPU time | 2.41 seconds |
| Started | Aug 25 02:12:06 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 242032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270891607 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3270891607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2285528686 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 39742527 ps |
| CPU time | 2 seconds |
| Started | Aug 25 02:12:06 PM UTC 24 |
| Finished | Aug 25 02:12:09 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285528686 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2285528686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1359623488 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 50489551 ps |
| CPU time | 2.36 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359623488 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1359623488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.408512884 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 45629304 ps |
| CPU time | 2.17 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408512884 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.408512884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.806069938 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 75621460 ps |
| CPU time | 2.32 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806069938 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.806069938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.104465914 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 52372408 ps |
| CPU time | 1.96 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104465914 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.104465914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.861907491 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 71742430 ps |
| CPU time | 1.96 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 241816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861907491 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.861907491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.126711547 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 61024985 ps |
| CPU time | 2.26 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:10 PM UTC 24 |
| Peak memory | 242480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126711547 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.126711547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3389330447 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 146489121 ps |
| CPU time | 2.37 seconds |
| Started | Aug 25 02:12:07 PM UTC 24 |
| Finished | Aug 25 02:12:11 PM UTC 24 |
| Peak memory | 242476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389330447 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3389330447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2767107389 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 1602023137 ps |
| CPU time | 7.02 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 259008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2767107389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.2767107389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1396298128 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 42584795 ps |
| CPU time | 2.37 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396298128 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1396298128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3268377972 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 66956871 ps |
| CPU time | 2.17 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 242608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268377972 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3268377972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1820338840 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 223772886 ps |
| CPU time | 3.43 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820338840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.1820338840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.805509316 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 209389572 ps |
| CPU time | 5.38 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:11:54 PM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805509316 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.805509316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4186374980 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3012060341 ps |
| CPU time | 22.57 seconds |
| Started | Aug 25 02:11:47 PM UTC 24 |
| Finished | Aug 25 02:12:11 PM UTC 24 |
| Peak memory | 256864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186374980 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.4186374980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1451704367 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 398420720 ps |
| CPU time | 4.72 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:54 PM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1451704367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.1451704367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2106734116 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 43625484 ps |
| CPU time | 2.11 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106734116 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2106734116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1283371929 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 144443169 ps |
| CPU time | 2.47 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 241944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283371929 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1283371929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3410778171 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 245920043 ps |
| CPU time | 2.85 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410778171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3410778171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3746050691 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 126944022 ps |
| CPU time | 6.24 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:55 PM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746050691 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3746050691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3963316711 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1019442485 ps |
| CPU time | 10.63 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:59 PM UTC 24 |
| Peak memory | 256928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963316711 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.3963316711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2611032752 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 1685250077 ps |
| CPU time | 6.93 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2611032752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs r_mem_rw_with_rand_reset.2611032752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.398933415 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 77587588 ps |
| CPU time | 2.4 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398933415 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.398933415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.4181229374 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 47403825 ps |
| CPU time | 2.25 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 241860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181229374 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.4181229374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1667864639 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 62960146 ps |
| CPU time | 3.09 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:52 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667864639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.1667864639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2136223179 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 493575429 ps |
| CPU time | 6.65 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 259224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136223179 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2136223179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.373883380 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 640457202 ps |
| CPU time | 10.07 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:59 PM UTC 24 |
| Peak memory | 256988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373883380 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.373883380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3575103382 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 215487333 ps |
| CPU time | 3.71 seconds |
| Started | Aug 25 02:11:49 PM UTC 24 |
| Finished | Aug 25 02:11:54 PM UTC 24 |
| Peak memory | 259072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3575103382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.3575103382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2697766621 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 45743902 ps |
| CPU time | 2.74 seconds |
| Started | Aug 25 02:11:49 PM UTC 24 |
| Finished | Aug 25 02:11:53 PM UTC 24 |
| Peak memory | 254696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697766621 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2697766621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.4061298631 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 157338313 ps |
| CPU time | 2.43 seconds |
| Started | Aug 25 02:11:49 PM UTC 24 |
| Finished | Aug 25 02:11:53 PM UTC 24 |
| Peak memory | 241676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061298631 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.4061298631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1464758034 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 124923816 ps |
| CPU time | 2.35 seconds |
| Started | Aug 25 02:11:49 PM UTC 24 |
| Finished | Aug 25 02:11:53 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464758034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.1464758034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3568295831 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 59971600 ps |
| CPU time | 4.73 seconds |
| Started | Aug 25 02:11:48 PM UTC 24 |
| Finished | Aug 25 02:11:54 PM UTC 24 |
| Peak memory | 259040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568295831 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3568295831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3510383490 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 19063339659 ps |
| CPU time | 46.68 seconds |
| Started | Aug 25 02:11:49 PM UTC 24 |
| Finished | Aug 25 02:12:37 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510383490 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3510383490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3296040704 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 231564532 ps |
| CPU time | 5.14 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:58 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3296040704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.3296040704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3674735419 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 625287547 ps |
| CPU time | 4.15 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:57 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674735419 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3674735419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.842442256 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 139141177 ps |
| CPU time | 2.17 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:55 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842442256 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.842442256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2127426196 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 136112660 ps |
| CPU time | 3.37 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:11:56 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127426196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.2127426196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.966468518 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 1410733343 ps |
| CPU time | 7.58 seconds |
| Started | Aug 25 02:11:52 PM UTC 24 |
| Finished | Aug 25 02:12:01 PM UTC 24 |
| Peak memory | 259132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966468518 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.966468518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.3214793923 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1234632368 ps |
| CPU time | 47.45 seconds |
| Started | Aug 25 01:53:55 PM UTC 24 |
| Finished | Aug 25 01:54:45 PM UTC 24 |
| Peak memory | 255352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214793923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3214793923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.1519137148 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7058428175 ps |
| CPU time | 26.81 seconds |
| Started | Aug 25 01:53:51 PM UTC 24 |
| Finished | Aug 25 01:54:19 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519137148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1519137148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.2069491220 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2991601115 ps |
| CPU time | 19.62 seconds |
| Started | Aug 25 01:53:33 PM UTC 24 |
| Finished | Aug 25 01:53:54 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069491220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2069491220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.768412457 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 218334722 ps |
| CPU time | 9.93 seconds |
| Started | Aug 25 01:53:49 PM UTC 24 |
| Finished | Aug 25 01:54:01 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768412457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.768412457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.2735128422 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6500559476 ps |
| CPU time | 31.33 seconds |
| Started | Aug 25 01:53:49 PM UTC 24 |
| Finished | Aug 25 01:54:22 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735128422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2735128422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.177582006 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 722143689 ps |
| CPU time | 26.85 seconds |
| Started | Aug 25 01:53:20 PM UTC 24 |
| Finished | Aug 25 01:53:48 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177582006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.177582006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.1834871603 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4607804193 ps |
| CPU time | 18.41 seconds |
| Started | Aug 25 01:54:16 PM UTC 24 |
| Finished | Aug 25 01:54:36 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834871603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1834871603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.2346677334 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 154963880706 ps |
| CPU time | 379.52 seconds |
| Started | Aug 25 01:54:20 PM UTC 24 |
| Finished | Aug 25 02:00:46 PM UTC 24 |
| Peak memory | 287992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346677334 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2346677334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1761815386 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 133229580 ps |
| CPU time | 3.54 seconds |
| Started | Aug 25 01:55:01 PM UTC 24 |
| Finished | Aug 25 01:55:05 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761815386 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1761815386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.531415345 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1871294929 ps |
| CPU time | 21.01 seconds |
| Started | Aug 25 01:54:43 PM UTC 24 |
| Finished | Aug 25 01:55:06 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531415345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.531415345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.2161815420 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5561017563 ps |
| CPU time | 18.01 seconds |
| Started | Aug 25 01:54:41 PM UTC 24 |
| Finished | Aug 25 01:55:00 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161815420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2161815420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.1265421821 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 648235267 ps |
| CPU time | 20.3 seconds |
| Started | Aug 25 01:54:46 PM UTC 24 |
| Finished | Aug 25 01:55:08 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265421821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1265421821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.1277144236 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 493911790 ps |
| CPU time | 19.86 seconds |
| Started | Aug 25 01:54:36 PM UTC 24 |
| Finished | Aug 25 01:54:57 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277144236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1277144236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.2331544242 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 620821937 ps |
| CPU time | 8.43 seconds |
| Started | Aug 25 01:54:47 PM UTC 24 |
| Finished | Aug 25 01:54:57 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331544242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2331544242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.2637108316 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1068198819 ps |
| CPU time | 17.71 seconds |
| Started | Aug 25 01:54:25 PM UTC 24 |
| Finished | Aug 25 01:54:44 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637108316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2637108316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.4028688269 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1312286720 ps |
| CPU time | 15.72 seconds |
| Started | Aug 25 01:54:54 PM UTC 24 |
| Finished | Aug 25 01:55:11 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028688269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.4028688269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.3789705845 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 420583668 ps |
| CPU time | 3.79 seconds |
| Started | Aug 25 01:59:02 PM UTC 24 |
| Finished | Aug 25 01:59:07 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789705845 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3789705845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.3092967935 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 520665203 ps |
| CPU time | 17.59 seconds |
| Started | Aug 25 01:58:53 PM UTC 24 |
| Finished | Aug 25 01:59:11 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092967935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3092967935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.3037473146 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1975303159 ps |
| CPU time | 39.3 seconds |
| Started | Aug 25 01:58:53 PM UTC 24 |
| Finished | Aug 25 01:59:34 PM UTC 24 |
| Peak memory | 253276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037473146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.3037473146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.2757494580 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 399745386 ps |
| CPU time | 11.48 seconds |
| Started | Aug 25 01:58:51 PM UTC 24 |
| Finished | Aug 25 01:59:03 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757494580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2757494580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.4056588991 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 21233286587 ps |
| CPU time | 72.96 seconds |
| Started | Aug 25 01:58:55 PM UTC 24 |
| Finished | Aug 25 02:00:10 PM UTC 24 |
| Peak memory | 257640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056588991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.4056588991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.4123204544 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1614643383 ps |
| CPU time | 25.93 seconds |
| Started | Aug 25 01:58:55 PM UTC 24 |
| Finished | Aug 25 01:59:22 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123204544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.4123204544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.926753463 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 186298660 ps |
| CPU time | 12.88 seconds |
| Started | Aug 25 01:58:49 PM UTC 24 |
| Finished | Aug 25 01:59:03 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926753463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.926753463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.2942400512 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 538423795 ps |
| CPU time | 19.33 seconds |
| Started | Aug 25 01:58:49 PM UTC 24 |
| Finished | Aug 25 01:59:09 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942400512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2942400512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.2650374715 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2438107188 ps |
| CPU time | 10.41 seconds |
| Started | Aug 25 01:58:56 PM UTC 24 |
| Finished | Aug 25 01:59:08 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650374715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2650374715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.3048498320 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 358928250 ps |
| CPU time | 7.62 seconds |
| Started | Aug 25 01:58:46 PM UTC 24 |
| Finished | Aug 25 01:58:55 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048498320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3048498320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.3301720638 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1216660109 ps |
| CPU time | 37.88 seconds |
| Started | Aug 25 01:58:56 PM UTC 24 |
| Finished | Aug 25 01:59:36 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301720638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3301720638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.1869198291 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 235892633 ps |
| CPU time | 5.9 seconds |
| Started | Aug 25 02:09:29 PM UTC 24 |
| Finished | Aug 25 02:09:36 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869198291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1869198291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.4263400353 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 231483442 ps |
| CPU time | 5.62 seconds |
| Started | Aug 25 02:09:31 PM UTC 24 |
| Finished | Aug 25 02:09:38 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263400353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.4263400353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.2165994258 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1139408873 ps |
| CPU time | 39.71 seconds |
| Started | Aug 25 02:09:31 PM UTC 24 |
| Finished | Aug 25 02:10:12 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165994258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2165994258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.2838415240 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 96699628 ps |
| CPU time | 8.18 seconds |
| Started | Aug 25 02:09:34 PM UTC 24 |
| Finished | Aug 25 02:09:44 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838415240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2838415240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.2212323313 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 267952889 ps |
| CPU time | 5.37 seconds |
| Started | Aug 25 02:09:37 PM UTC 24 |
| Finished | Aug 25 02:09:43 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212323313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2212323313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.1976499059 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 296637701 ps |
| CPU time | 10.44 seconds |
| Started | Aug 25 02:09:37 PM UTC 24 |
| Finished | Aug 25 02:09:49 PM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976499059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1976499059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.914708139 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 292442310 ps |
| CPU time | 6.62 seconds |
| Started | Aug 25 02:09:37 PM UTC 24 |
| Finished | Aug 25 02:09:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914708139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.914708139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.2230987033 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3467208935 ps |
| CPU time | 14.41 seconds |
| Started | Aug 25 02:09:39 PM UTC 24 |
| Finished | Aug 25 02:09:55 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230987033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2230987033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.3394523873 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 735798392 ps |
| CPU time | 19.16 seconds |
| Started | Aug 25 02:09:39 PM UTC 24 |
| Finished | Aug 25 02:10:00 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394523873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3394523873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.317121188 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1713268140 ps |
| CPU time | 7.25 seconds |
| Started | Aug 25 02:09:39 PM UTC 24 |
| Finished | Aug 25 02:09:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317121188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.317121188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.1663537389 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2633347362 ps |
| CPU time | 10.4 seconds |
| Started | Aug 25 02:09:41 PM UTC 24 |
| Finished | Aug 25 02:09:53 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663537389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1663537389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.1717266276 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 356693960 ps |
| CPU time | 5.42 seconds |
| Started | Aug 25 02:09:41 PM UTC 24 |
| Finished | Aug 25 02:09:48 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717266276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1717266276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.4134596865 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 243740489 ps |
| CPU time | 8.84 seconds |
| Started | Aug 25 02:09:43 PM UTC 24 |
| Finished | Aug 25 02:09:53 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134596865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.4134596865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.506909149 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 173824118 ps |
| CPU time | 5.23 seconds |
| Started | Aug 25 02:09:45 PM UTC 24 |
| Finished | Aug 25 02:09:51 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506909149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.506909149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.1169305283 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3566524720 ps |
| CPU time | 10.79 seconds |
| Started | Aug 25 02:09:45 PM UTC 24 |
| Finished | Aug 25 02:09:57 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169305283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1169305283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.4170185547 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 544735130 ps |
| CPU time | 5.65 seconds |
| Started | Aug 25 02:09:46 PM UTC 24 |
| Finished | Aug 25 02:09:53 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170185547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.4170185547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.1985789651 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1210750792 ps |
| CPU time | 23.64 seconds |
| Started | Aug 25 02:09:46 PM UTC 24 |
| Finished | Aug 25 02:10:11 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985789651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1985789651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.1880518164 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 109574697 ps |
| CPU time | 2.64 seconds |
| Started | Aug 25 01:59:14 PM UTC 24 |
| Finished | Aug 25 01:59:18 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880518164 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1880518164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.3075506702 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 723377900 ps |
| CPU time | 6.6 seconds |
| Started | Aug 25 01:59:09 PM UTC 24 |
| Finished | Aug 25 01:59:17 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075506702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3075506702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.3145699916 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 341332799 ps |
| CPU time | 27.96 seconds |
| Started | Aug 25 01:59:08 PM UTC 24 |
| Finished | Aug 25 01:59:37 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145699916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3145699916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.1654017204 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 206220822 ps |
| CPU time | 7.06 seconds |
| Started | Aug 25 01:59:05 PM UTC 24 |
| Finished | Aug 25 01:59:14 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654017204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1654017204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.3211880814 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 244896759 ps |
| CPU time | 7.36 seconds |
| Started | Aug 25 01:59:05 PM UTC 24 |
| Finished | Aug 25 01:59:14 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211880814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3211880814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.1567270952 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 457711772 ps |
| CPU time | 11.41 seconds |
| Started | Aug 25 01:59:10 PM UTC 24 |
| Finished | Aug 25 01:59:23 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567270952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1567270952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.199625480 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2379388961 ps |
| CPU time | 45.76 seconds |
| Started | Aug 25 01:59:12 PM UTC 24 |
| Finished | Aug 25 01:59:59 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199625480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.199625480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.1861901986 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 896789491 ps |
| CPU time | 37.92 seconds |
| Started | Aug 25 01:59:05 PM UTC 24 |
| Finished | Aug 25 01:59:45 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861901986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1861901986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3977475286 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 189027011 ps |
| CPU time | 8.94 seconds |
| Started | Aug 25 01:59:05 PM UTC 24 |
| Finished | Aug 25 01:59:15 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977475286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3977475286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.2019867480 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 216506233 ps |
| CPU time | 4.44 seconds |
| Started | Aug 25 01:59:14 PM UTC 24 |
| Finished | Aug 25 01:59:20 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019867480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2019867480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.824814705 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 464632083 ps |
| CPU time | 8.18 seconds |
| Started | Aug 25 01:59:03 PM UTC 24 |
| Finished | Aug 25 01:59:12 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824814705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.824814705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.603095014 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3045318999 ps |
| CPU time | 54.84 seconds |
| Started | Aug 25 01:59:14 PM UTC 24 |
| Finished | Aug 25 02:00:11 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603095014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.603095014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.1018271908 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 183075552 ps |
| CPU time | 4.14 seconds |
| Started | Aug 25 02:09:48 PM UTC 24 |
| Finished | Aug 25 02:09:54 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018271908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1018271908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.1579157903 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 813806433 ps |
| CPU time | 16.44 seconds |
| Started | Aug 25 02:09:48 PM UTC 24 |
| Finished | Aug 25 02:10:06 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579157903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1579157903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.1949007840 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4801274379 ps |
| CPU time | 25.21 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:20 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949007840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1949007840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.1076990391 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 177940329 ps |
| CPU time | 4.71 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:09:59 PM UTC 24 |
| Peak memory | 253328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076990391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1076990391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.4265548468 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 165762498 ps |
| CPU time | 7.24 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:02 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265548468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.4265548468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.2981967226 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 584175577 ps |
| CPU time | 5.84 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:01 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981967226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2981967226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.400139371 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 99314788 ps |
| CPU time | 5.72 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:01 PM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400139371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.400139371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.4267477621 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 165984899 ps |
| CPU time | 5.28 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:00 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267477621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4267477621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.1080224907 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 492219702 ps |
| CPU time | 7.17 seconds |
| Started | Aug 25 02:09:54 PM UTC 24 |
| Finished | Aug 25 02:10:02 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080224907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1080224907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.1006651794 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 379619841 ps |
| CPU time | 12.45 seconds |
| Started | Aug 25 02:09:56 PM UTC 24 |
| Finished | Aug 25 02:10:09 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006651794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1006651794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.741802386 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 264785101 ps |
| CPU time | 6.34 seconds |
| Started | Aug 25 02:09:56 PM UTC 24 |
| Finished | Aug 25 02:10:03 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741802386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.741802386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.3749271583 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 651436758 ps |
| CPU time | 7.42 seconds |
| Started | Aug 25 02:09:56 PM UTC 24 |
| Finished | Aug 25 02:10:04 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749271583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3749271583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.2080522294 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 257428338 ps |
| CPU time | 6.56 seconds |
| Started | Aug 25 02:09:56 PM UTC 24 |
| Finished | Aug 25 02:10:03 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080522294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2080522294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.3705864712 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 264678011 ps |
| CPU time | 6.58 seconds |
| Started | Aug 25 02:09:58 PM UTC 24 |
| Finished | Aug 25 02:10:06 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705864712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3705864712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.3516087556 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 4526124519 ps |
| CPU time | 16.34 seconds |
| Started | Aug 25 02:10:01 PM UTC 24 |
| Finished | Aug 25 02:10:19 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516087556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3516087556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.3516688183 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 284978147 ps |
| CPU time | 4.21 seconds |
| Started | Aug 25 02:10:01 PM UTC 24 |
| Finished | Aug 25 02:10:06 PM UTC 24 |
| Peak memory | 250960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516688183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3516688183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.2852990138 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 628270823 ps |
| CPU time | 7.51 seconds |
| Started | Aug 25 02:10:01 PM UTC 24 |
| Finished | Aug 25 02:10:10 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852990138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2852990138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.3603104586 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 178406653 ps |
| CPU time | 2.71 seconds |
| Started | Aug 25 01:59:25 PM UTC 24 |
| Finished | Aug 25 01:59:29 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603104586 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.3603104586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.926974941 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2588674248 ps |
| CPU time | 37.46 seconds |
| Started | Aug 25 01:59:20 PM UTC 24 |
| Finished | Aug 25 01:59:58 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926974941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.926974941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.3322615695 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 497334906 ps |
| CPU time | 25.83 seconds |
| Started | Aug 25 01:59:18 PM UTC 24 |
| Finished | Aug 25 01:59:45 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322615695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3322615695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.3237851988 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1119305867 ps |
| CPU time | 26.66 seconds |
| Started | Aug 25 01:59:18 PM UTC 24 |
| Finished | Aug 25 01:59:46 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237851988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3237851988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1603039579 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 419199033 ps |
| CPU time | 4.86 seconds |
| Started | Aug 25 01:59:17 PM UTC 24 |
| Finished | Aug 25 01:59:23 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603039579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1603039579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.799633003 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 759877773 ps |
| CPU time | 17.54 seconds |
| Started | Aug 25 01:59:20 PM UTC 24 |
| Finished | Aug 25 01:59:38 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799633003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.799633003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.3063135489 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 12689296427 ps |
| CPU time | 47.53 seconds |
| Started | Aug 25 01:59:20 PM UTC 24 |
| Finished | Aug 25 02:00:09 PM UTC 24 |
| Peak memory | 253412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063135489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3063135489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2425247518 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5878021492 ps |
| CPU time | 20.34 seconds |
| Started | Aug 25 01:59:18 PM UTC 24 |
| Finished | Aug 25 01:59:39 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425247518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2425247518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.2874971961 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 171307645 ps |
| CPU time | 7.88 seconds |
| Started | Aug 25 01:59:21 PM UTC 24 |
| Finished | Aug 25 01:59:30 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874971961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2874971961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.1488277941 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 592280502 ps |
| CPU time | 16.68 seconds |
| Started | Aug 25 01:59:17 PM UTC 24 |
| Finished | Aug 25 01:59:35 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488277941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1488277941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.3597591023 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 125850705994 ps |
| CPU time | 377.84 seconds |
| Started | Aug 25 01:59:25 PM UTC 24 |
| Finished | Aug 25 02:05:50 PM UTC 24 |
| Peak memory | 284240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597591023 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.3597591023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.3290217964 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 4596693429 ps |
| CPU time | 170.81 seconds |
| Started | Aug 25 01:59:25 PM UTC 24 |
| Finished | Aug 25 02:02:19 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3290217964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.otp_ctrl_stress_all_with_rand_reset.3290217964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.234820136 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 9240300792 ps |
| CPU time | 39.43 seconds |
| Started | Aug 25 01:59:22 PM UTC 24 |
| Finished | Aug 25 02:00:03 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234820136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.234820136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.2020626854 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 345153918 ps |
| CPU time | 6.51 seconds |
| Started | Aug 25 02:10:01 PM UTC 24 |
| Finished | Aug 25 02:10:09 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020626854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2020626854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.2515478464 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1077248541 ps |
| CPU time | 21.38 seconds |
| Started | Aug 25 02:10:01 PM UTC 24 |
| Finished | Aug 25 02:10:24 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515478464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2515478464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.3088837464 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 191380551 ps |
| CPU time | 4.88 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:11 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088837464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.3088837464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.2519666017 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 314247043 ps |
| CPU time | 15.39 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:22 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519666017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2519666017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.3496564160 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 226583848 ps |
| CPU time | 5.82 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496564160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3496564160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.3508112016 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1830721384 ps |
| CPU time | 10.27 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:17 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508112016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3508112016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.339069424 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 501537282 ps |
| CPU time | 6.22 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:13 PM UTC 24 |
| Peak memory | 250912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339069424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.339069424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.213991700 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 8596289213 ps |
| CPU time | 23.57 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:30 PM UTC 24 |
| Peak memory | 251008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213991700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.213991700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.531947032 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 161756312 ps |
| CPU time | 6.18 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:13 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531947032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.531947032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.1762027683 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 67668419 ps |
| CPU time | 4.98 seconds |
| Started | Aug 25 02:10:05 PM UTC 24 |
| Finished | Aug 25 02:10:12 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762027683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1762027683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.4235044881 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 410280745 ps |
| CPU time | 4.7 seconds |
| Started | Aug 25 02:10:07 PM UTC 24 |
| Finished | Aug 25 02:10:13 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235044881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.4235044881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.1479284085 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 502356493 ps |
| CPU time | 19.01 seconds |
| Started | Aug 25 02:10:08 PM UTC 24 |
| Finished | Aug 25 02:10:28 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479284085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1479284085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.1816619874 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 265679501 ps |
| CPU time | 6.36 seconds |
| Started | Aug 25 02:10:08 PM UTC 24 |
| Finished | Aug 25 02:10:15 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816619874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1816619874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.1250632956 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 566437638 ps |
| CPU time | 5.69 seconds |
| Started | Aug 25 02:10:08 PM UTC 24 |
| Finished | Aug 25 02:10:14 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250632956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1250632956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.165391767 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 419166401 ps |
| CPU time | 8.11 seconds |
| Started | Aug 25 02:10:08 PM UTC 24 |
| Finished | Aug 25 02:10:17 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165391767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.165391767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.3779154259 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 131906802 ps |
| CPU time | 7.22 seconds |
| Started | Aug 25 02:10:09 PM UTC 24 |
| Finished | Aug 25 02:10:18 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779154259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3779154259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.3814156404 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 1910639038 ps |
| CPU time | 8.01 seconds |
| Started | Aug 25 02:10:09 PM UTC 24 |
| Finished | Aug 25 02:10:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814156404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3814156404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.2949710673 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2409075857 ps |
| CPU time | 11.18 seconds |
| Started | Aug 25 02:10:11 PM UTC 24 |
| Finished | Aug 25 02:10:24 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949710673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2949710673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1247981405 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 78937370 ps |
| CPU time | 2.53 seconds |
| Started | Aug 25 01:59:41 PM UTC 24 |
| Finished | Aug 25 01:59:44 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247981405 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1247981405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.1797635594 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 326583754 ps |
| CPU time | 13.01 seconds |
| Started | Aug 25 01:59:33 PM UTC 24 |
| Finished | Aug 25 01:59:47 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797635594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1797635594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3276185522 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 439025660 ps |
| CPU time | 17.69 seconds |
| Started | Aug 25 01:59:33 PM UTC 24 |
| Finished | Aug 25 01:59:52 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276185522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3276185522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.1491627198 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3293353060 ps |
| CPU time | 37.52 seconds |
| Started | Aug 25 01:59:31 PM UTC 24 |
| Finished | Aug 25 02:00:10 PM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491627198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1491627198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.4106757370 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 202243565 ps |
| CPU time | 5.16 seconds |
| Started | Aug 25 01:59:25 PM UTC 24 |
| Finished | Aug 25 01:59:32 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106757370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.4106757370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.535286847 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 861896219 ps |
| CPU time | 23.68 seconds |
| Started | Aug 25 01:59:34 PM UTC 24 |
| Finished | Aug 25 01:59:59 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535286847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.535286847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2457020629 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 13532662458 ps |
| CPU time | 39.07 seconds |
| Started | Aug 25 01:59:36 PM UTC 24 |
| Finished | Aug 25 02:00:16 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457020629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2457020629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.1729296637 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 515308140 ps |
| CPU time | 16.92 seconds |
| Started | Aug 25 01:59:30 PM UTC 24 |
| Finished | Aug 25 01:59:48 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729296637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1729296637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.377679386 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4681638883 ps |
| CPU time | 20.61 seconds |
| Started | Aug 25 01:59:28 PM UTC 24 |
| Finished | Aug 25 01:59:50 PM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377679386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.377679386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.4095918537 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 501606516 ps |
| CPU time | 9.79 seconds |
| Started | Aug 25 01:59:37 PM UTC 24 |
| Finished | Aug 25 01:59:48 PM UTC 24 |
| Peak memory | 257672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095918537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.4095918537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.1267263775 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 912085582 ps |
| CPU time | 13.63 seconds |
| Started | Aug 25 01:59:25 PM UTC 24 |
| Finished | Aug 25 01:59:40 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267263775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1267263775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.575220968 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1622183101 ps |
| CPU time | 53.48 seconds |
| Started | Aug 25 01:59:39 PM UTC 24 |
| Finished | Aug 25 02:00:35 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=575220968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.575220968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.3647681999 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1451169150 ps |
| CPU time | 26 seconds |
| Started | Aug 25 01:59:37 PM UTC 24 |
| Finished | Aug 25 02:00:04 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647681999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3647681999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.1198657109 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 484863616 ps |
| CPU time | 5.83 seconds |
| Started | Aug 25 02:10:11 PM UTC 24 |
| Finished | Aug 25 02:10:18 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198657109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1198657109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2276689951 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 5246230460 ps |
| CPU time | 28.37 seconds |
| Started | Aug 25 02:10:11 PM UTC 24 |
| Finished | Aug 25 02:10:41 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276689951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2276689951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1082247124 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 90861441 ps |
| CPU time | 4.7 seconds |
| Started | Aug 25 02:10:13 PM UTC 24 |
| Finished | Aug 25 02:10:19 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082247124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1082247124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.4099001731 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 424534511 ps |
| CPU time | 14.48 seconds |
| Started | Aug 25 02:10:13 PM UTC 24 |
| Finished | Aug 25 02:10:29 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099001731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.4099001731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.3064776064 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 100574981 ps |
| CPU time | 4.96 seconds |
| Started | Aug 25 02:10:13 PM UTC 24 |
| Finished | Aug 25 02:10:19 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064776064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3064776064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.3025469564 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 171748601 ps |
| CPU time | 6.67 seconds |
| Started | Aug 25 02:10:13 PM UTC 24 |
| Finished | Aug 25 02:10:21 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025469564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3025469564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.23719786 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1632216740 ps |
| CPU time | 8.75 seconds |
| Started | Aug 25 02:10:13 PM UTC 24 |
| Finished | Aug 25 02:10:23 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23719786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.23719786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.1011355938 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 246089570 ps |
| CPU time | 14.02 seconds |
| Started | Aug 25 02:10:13 PM UTC 24 |
| Finished | Aug 25 02:10:29 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011355938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1011355938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.3287284270 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 307249954 ps |
| CPU time | 6.32 seconds |
| Started | Aug 25 02:10:16 PM UTC 24 |
| Finished | Aug 25 02:10:24 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287284270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3287284270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.1082494748 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 10067513565 ps |
| CPU time | 36.51 seconds |
| Started | Aug 25 02:10:16 PM UTC 24 |
| Finished | Aug 25 02:10:54 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082494748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1082494748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.4212040995 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 125312389 ps |
| CPU time | 6.49 seconds |
| Started | Aug 25 02:10:16 PM UTC 24 |
| Finished | Aug 25 02:10:24 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212040995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.4212040995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.3655785724 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1370999304 ps |
| CPU time | 24.41 seconds |
| Started | Aug 25 02:10:16 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655785724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3655785724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.3716548156 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 132602088 ps |
| CPU time | 5 seconds |
| Started | Aug 25 02:10:16 PM UTC 24 |
| Finished | Aug 25 02:10:22 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716548156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3716548156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.627174743 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 216163209 ps |
| CPU time | 5.28 seconds |
| Started | Aug 25 02:10:16 PM UTC 24 |
| Finished | Aug 25 02:10:23 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627174743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.627174743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.2128047260 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 97418264 ps |
| CPU time | 3.65 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:26 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128047260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2128047260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.534615508 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 440759577 ps |
| CPU time | 7.32 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:29 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534615508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.534615508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.2268479033 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1582858737 ps |
| CPU time | 8.24 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:30 PM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268479033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2268479033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.2442168267 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 137609549 ps |
| CPU time | 5.34 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:27 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442168267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2442168267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.1188263702 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 122013043 ps |
| CPU time | 5.33 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:27 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188263702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1188263702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.2815457098 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 475364399 ps |
| CPU time | 15.81 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:38 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815457098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2815457098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.1816861876 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 46789940 ps |
| CPU time | 2.39 seconds |
| Started | Aug 25 01:59:52 PM UTC 24 |
| Finished | Aug 25 01:59:55 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816861876 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1816861876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.1595004918 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1818528182 ps |
| CPU time | 15.8 seconds |
| Started | Aug 25 01:59:48 PM UTC 24 |
| Finished | Aug 25 02:00:06 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595004918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1595004918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.2824527311 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 277877389 ps |
| CPU time | 20.15 seconds |
| Started | Aug 25 01:59:47 PM UTC 24 |
| Finished | Aug 25 02:00:08 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824527311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.2824527311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1826015707 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2123222916 ps |
| CPU time | 6.54 seconds |
| Started | Aug 25 01:59:48 PM UTC 24 |
| Finished | Aug 25 01:59:56 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826015707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1826015707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.4267287525 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3300061671 ps |
| CPU time | 28.3 seconds |
| Started | Aug 25 01:59:50 PM UTC 24 |
| Finished | Aug 25 02:00:20 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267287525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.4267287525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.2183162802 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 586230444 ps |
| CPU time | 5.72 seconds |
| Started | Aug 25 01:59:46 PM UTC 24 |
| Finished | Aug 25 01:59:53 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183162802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2183162802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.3248326104 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 872892897 ps |
| CPU time | 20.42 seconds |
| Started | Aug 25 01:59:42 PM UTC 24 |
| Finished | Aug 25 02:00:04 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248326104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3248326104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.1411099937 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 115268833 ps |
| CPU time | 5.24 seconds |
| Started | Aug 25 01:59:50 PM UTC 24 |
| Finished | Aug 25 01:59:57 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411099937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1411099937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.2806749523 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 282764309 ps |
| CPU time | 6.18 seconds |
| Started | Aug 25 01:59:42 PM UTC 24 |
| Finished | Aug 25 01:59:49 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806749523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2806749523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.4019242463 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 18273310407 ps |
| CPU time | 290.17 seconds |
| Started | Aug 25 01:59:52 PM UTC 24 |
| Finished | Aug 25 02:04:48 PM UTC 24 |
| Peak memory | 255676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019242463 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.4019242463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.3484565283 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9849711686 ps |
| CPU time | 139.62 seconds |
| Started | Aug 25 01:59:51 PM UTC 24 |
| Finished | Aug 25 02:02:14 PM UTC 24 |
| Peak memory | 274032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3484565283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.otp_ctrl_stress_all_with_rand_reset.3484565283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.923386075 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1723891348 ps |
| CPU time | 39.67 seconds |
| Started | Aug 25 01:59:51 PM UTC 24 |
| Finished | Aug 25 02:00:32 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923386075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.923386075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.810956970 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 287004267 ps |
| CPU time | 5.15 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:27 PM UTC 24 |
| Peak memory | 253524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810956970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.810956970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.1355628624 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 361262651 ps |
| CPU time | 4.94 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:27 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355628624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1355628624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.1748714572 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 139871659 ps |
| CPU time | 5.62 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:28 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748714572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1748714572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.1554702887 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 94392970 ps |
| CPU time | 4.75 seconds |
| Started | Aug 25 02:10:21 PM UTC 24 |
| Finished | Aug 25 02:10:27 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554702887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1554702887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.1625952890 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 568412353 ps |
| CPU time | 6.24 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625952890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1625952890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.762003470 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 266077497 ps |
| CPU time | 17.63 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762003470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.762003470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.3680665606 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 228544339 ps |
| CPU time | 6.14 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680665606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3680665606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.28406808 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 326642542 ps |
| CPU time | 13.81 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:50 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28406808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.28406808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.1778551118 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 209559111 ps |
| CPU time | 6.31 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778551118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1778551118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.3356346118 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 1365929675 ps |
| CPU time | 15.1 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356346118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3356346118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.1007593468 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 790641947 ps |
| CPU time | 6.4 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007593468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.1007593468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.3802522136 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 192581542 ps |
| CPU time | 13.36 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:50 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802522136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3802522136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.266743227 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 145848483 ps |
| CPU time | 5.53 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266743227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.266743227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.3897961091 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 256500884 ps |
| CPU time | 17.97 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:55 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897961091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3897961091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.3828462460 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 446495125 ps |
| CPU time | 4.92 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828462460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3828462460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.3217990941 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 165009467 ps |
| CPU time | 5.87 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:43 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217990941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3217990941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.3085645145 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 303795805 ps |
| CPU time | 5.73 seconds |
| Started | Aug 25 02:10:34 PM UTC 24 |
| Finished | Aug 25 02:10:43 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085645145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3085645145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.2023043715 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 1179943404 ps |
| CPU time | 20.93 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:58 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023043715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2023043715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.2305365161 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2618171421 ps |
| CPU time | 9.1 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:46 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305365161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2305365161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.4284782327 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 1082445773 ps |
| CPU time | 23.65 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:11:01 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284782327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.4284782327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.3149795722 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 108944830 ps |
| CPU time | 2.79 seconds |
| Started | Aug 25 02:00:03 PM UTC 24 |
| Finished | Aug 25 02:00:10 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149795722 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3149795722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.23551218 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1988234221 ps |
| CPU time | 20.38 seconds |
| Started | Aug 25 01:59:57 PM UTC 24 |
| Finished | Aug 25 02:00:19 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23551218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.23551218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.4127041135 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 750083352 ps |
| CPU time | 15.43 seconds |
| Started | Aug 25 01:59:57 PM UTC 24 |
| Finished | Aug 25 02:00:14 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127041135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.4127041135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.2692005109 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 266848106 ps |
| CPU time | 6.89 seconds |
| Started | Aug 25 01:59:57 PM UTC 24 |
| Finished | Aug 25 02:00:05 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692005109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2692005109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.1754120156 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1923418124 ps |
| CPU time | 6.21 seconds |
| Started | Aug 25 01:59:53 PM UTC 24 |
| Finished | Aug 25 02:00:01 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754120156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1754120156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1843154856 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 952492191 ps |
| CPU time | 10.43 seconds |
| Started | Aug 25 01:59:58 PM UTC 24 |
| Finished | Aug 25 02:00:10 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843154856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1843154856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.2869609258 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1669519698 ps |
| CPU time | 21.19 seconds |
| Started | Aug 25 02:00:01 PM UTC 24 |
| Finished | Aug 25 02:00:28 PM UTC 24 |
| Peak memory | 253668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869609258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2869609258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.1519325597 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2593280205 ps |
| CPU time | 32.24 seconds |
| Started | Aug 25 01:59:54 PM UTC 24 |
| Finished | Aug 25 02:00:28 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519325597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1519325597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.1212399095 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2374101214 ps |
| CPU time | 12.23 seconds |
| Started | Aug 25 01:59:53 PM UTC 24 |
| Finished | Aug 25 02:00:07 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212399095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1212399095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.690627680 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3065888888 ps |
| CPU time | 36.14 seconds |
| Started | Aug 25 02:00:02 PM UTC 24 |
| Finished | Aug 25 02:00:44 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690627680 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.690627680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.2265880462 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2799120018 ps |
| CPU time | 24.24 seconds |
| Started | Aug 25 02:00:01 PM UTC 24 |
| Finished | Aug 25 02:00:31 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265880462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2265880462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.1685790453 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 112650652 ps |
| CPU time | 5.01 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685790453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1685790453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.253611298 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 153559884 ps |
| CPU time | 7.65 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:45 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253611298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.253611298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.951249231 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 138534059 ps |
| CPU time | 5.31 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 250500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951249231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.951249231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.43133029 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 728811515 ps |
| CPU time | 15.72 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43133029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.43133029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.4162512333 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 288704993 ps |
| CPU time | 6.24 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:43 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162512333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.4162512333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.1773396060 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 304073554 ps |
| CPU time | 6.76 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:44 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773396060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1773396060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.383801688 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 462200584 ps |
| CPU time | 4.95 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383801688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.383801688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.3595027981 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 363349424 ps |
| CPU time | 4.93 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:42 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595027981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3595027981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.2547756018 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 405276803 ps |
| CPU time | 7.07 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:45 PM UTC 24 |
| Peak memory | 251000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547756018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2547756018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.2194910034 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 238426588 ps |
| CPU time | 8.65 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:46 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194910034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2194910034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.1423089231 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 462849857 ps |
| CPU time | 5.79 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:43 PM UTC 24 |
| Peak memory | 250988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423089231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1423089231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.183575827 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 305488057 ps |
| CPU time | 9.27 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:47 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183575827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.183575827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.1072789222 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 175765568 ps |
| CPU time | 5.63 seconds |
| Started | Aug 25 02:10:35 PM UTC 24 |
| Finished | Aug 25 02:10:43 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072789222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1072789222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.1509652542 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2678495993 ps |
| CPU time | 13.13 seconds |
| Started | Aug 25 02:10:38 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509652542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1509652542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.1836809615 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2639779815 ps |
| CPU time | 10.17 seconds |
| Started | Aug 25 02:10:38 PM UTC 24 |
| Finished | Aug 25 02:10:50 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836809615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1836809615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.2023201603 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 728315030 ps |
| CPU time | 19.44 seconds |
| Started | Aug 25 02:10:39 PM UTC 24 |
| Finished | Aug 25 02:11:00 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023201603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2023201603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.871969643 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 296777794 ps |
| CPU time | 6.57 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:10:52 PM UTC 24 |
| Peak memory | 250864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871969643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.871969643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.2382600790 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 460707078 ps |
| CPU time | 7.06 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382600790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2382600790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.2336329266 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 2217321822 ps |
| CPU time | 17.29 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:11:03 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336329266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2336329266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.2952763583 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 56346960 ps |
| CPU time | 3.04 seconds |
| Started | Aug 25 02:00:13 PM UTC 24 |
| Finished | Aug 25 02:00:18 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952763583 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2952763583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.1614788891 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3810027606 ps |
| CPU time | 64.41 seconds |
| Started | Aug 25 02:00:10 PM UTC 24 |
| Finished | Aug 25 02:01:16 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614788891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1614788891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1913427252 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 689442193 ps |
| CPU time | 12.71 seconds |
| Started | Aug 25 02:00:10 PM UTC 24 |
| Finished | Aug 25 02:00:24 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913427252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1913427252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.3217332542 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 493160792 ps |
| CPU time | 7.81 seconds |
| Started | Aug 25 02:00:10 PM UTC 24 |
| Finished | Aug 25 02:00:19 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217332542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3217332542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.1673654886 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 498508272 ps |
| CPU time | 7.8 seconds |
| Started | Aug 25 02:00:09 PM UTC 24 |
| Finished | Aug 25 02:00:18 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673654886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1673654886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.150772831 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2430096232 ps |
| CPU time | 30.04 seconds |
| Started | Aug 25 02:00:10 PM UTC 24 |
| Finished | Aug 25 02:00:41 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150772831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.150772831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.4190528151 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1250657377 ps |
| CPU time | 30.32 seconds |
| Started | Aug 25 02:00:13 PM UTC 24 |
| Finished | Aug 25 02:00:45 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190528151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4190528151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.3803309212 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 215417573 ps |
| CPU time | 7.31 seconds |
| Started | Aug 25 02:00:10 PM UTC 24 |
| Finished | Aug 25 02:00:18 PM UTC 24 |
| Peak memory | 251048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803309212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3803309212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.2419046822 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 10802598664 ps |
| CPU time | 44.93 seconds |
| Started | Aug 25 02:00:09 PM UTC 24 |
| Finished | Aug 25 02:00:56 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419046822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2419046822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.2203048647 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 451151506 ps |
| CPU time | 9.09 seconds |
| Started | Aug 25 02:00:09 PM UTC 24 |
| Finished | Aug 25 02:00:20 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203048647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2203048647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.3132030610 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 8370119029 ps |
| CPU time | 237.7 seconds |
| Started | Aug 25 02:00:13 PM UTC 24 |
| Finished | Aug 25 02:04:16 PM UTC 24 |
| Peak memory | 267740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132030610 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.3132030610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.64480094 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 7944392073 ps |
| CPU time | 238.91 seconds |
| Started | Aug 25 02:00:13 PM UTC 24 |
| Finished | Aug 25 02:04:17 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=64480094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.64480094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.244967148 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3462583489 ps |
| CPU time | 57.24 seconds |
| Started | Aug 25 02:00:13 PM UTC 24 |
| Finished | Aug 25 02:01:13 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244967148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.244967148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.863697723 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2182382177 ps |
| CPU time | 8.18 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:10:54 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863697723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.863697723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1139761825 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 228146579 ps |
| CPU time | 5.5 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139761825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1139761825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.3218039776 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 160844087 ps |
| CPU time | 5.59 seconds |
| Started | Aug 25 02:10:44 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218039776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3218039776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.2336711007 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 198040071 ps |
| CPU time | 7.96 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:54 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336711007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2336711007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.133971023 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 325771356 ps |
| CPU time | 4.84 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133971023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.133971023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.1716625228 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 684135766 ps |
| CPU time | 7.03 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716625228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1716625228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.18844452 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2230804496 ps |
| CPU time | 11.67 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:58 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18844452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.18844452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.1236840630 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2286143329 ps |
| CPU time | 13.24 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:59 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236840630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1236840630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.3511532849 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 161927231 ps |
| CPU time | 4.23 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:50 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511532849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3511532849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.1951580735 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 226832576 ps |
| CPU time | 5.14 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951580735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1951580735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.2243908856 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 133113571 ps |
| CPU time | 3.69 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:50 PM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243908856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2243908856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.75486388 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 113957041 ps |
| CPU time | 5.21 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:51 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75486388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.75486388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.634094964 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 511514307 ps |
| CPU time | 10.62 seconds |
| Started | Aug 25 02:10:45 PM UTC 24 |
| Finished | Aug 25 02:10:57 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634094964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.634094964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.3528051307 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1705795412 ps |
| CPU time | 5.25 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:10:55 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528051307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3528051307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.718084673 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 510847633 ps |
| CPU time | 11.87 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:11:02 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718084673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.718084673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.1661142613 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 309596809 ps |
| CPU time | 7.03 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:10:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661142613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1661142613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.2232909199 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 149236994 ps |
| CPU time | 9.08 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:11:00 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232909199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.2232909199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.2744469804 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 482611921 ps |
| CPU time | 7.27 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:10:58 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744469804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2744469804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.941375626 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 379089525 ps |
| CPU time | 5.74 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:10:56 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941375626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.941375626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.3223401992 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 99631263 ps |
| CPU time | 3.47 seconds |
| Started | Aug 25 02:00:27 PM UTC 24 |
| Finished | Aug 25 02:00:32 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223401992 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3223401992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.4093805814 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 802286308 ps |
| CPU time | 24.54 seconds |
| Started | Aug 25 02:00:20 PM UTC 24 |
| Finished | Aug 25 02:00:46 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093805814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.4093805814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.4049956262 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 466240565 ps |
| CPU time | 17.05 seconds |
| Started | Aug 25 02:00:20 PM UTC 24 |
| Finished | Aug 25 02:00:39 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049956262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.4049956262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.2308855916 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 4115617516 ps |
| CPU time | 36.99 seconds |
| Started | Aug 25 02:00:20 PM UTC 24 |
| Finished | Aug 25 02:00:59 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308855916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2308855916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.3278161232 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3268621720 ps |
| CPU time | 35.91 seconds |
| Started | Aug 25 02:00:20 PM UTC 24 |
| Finished | Aug 25 02:00:58 PM UTC 24 |
| Peak memory | 255540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278161232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3278161232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.1768512209 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 15883852047 ps |
| CPU time | 41.38 seconds |
| Started | Aug 25 02:00:22 PM UTC 24 |
| Finished | Aug 25 02:01:05 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768512209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1768512209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.1146723536 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 701122143 ps |
| CPU time | 22.18 seconds |
| Started | Aug 25 02:00:20 PM UTC 24 |
| Finished | Aug 25 02:00:44 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146723536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1146723536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.2327528439 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 284599680 ps |
| CPU time | 13.29 seconds |
| Started | Aug 25 02:00:22 PM UTC 24 |
| Finished | Aug 25 02:00:36 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327528439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2327528439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.1735440361 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 526926711 ps |
| CPU time | 6.87 seconds |
| Started | Aug 25 02:00:15 PM UTC 24 |
| Finished | Aug 25 02:00:23 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735440361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1735440361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.2464561576 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1044070586 ps |
| CPU time | 26.38 seconds |
| Started | Aug 25 02:00:24 PM UTC 24 |
| Finished | Aug 25 02:00:52 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464561576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2464561576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.2663462518 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 208657432 ps |
| CPU time | 4.62 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:10:55 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663462518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2663462518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.2768606232 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2286714647 ps |
| CPU time | 20.8 seconds |
| Started | Aug 25 02:10:49 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768606232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2768606232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.151868029 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 225393848 ps |
| CPU time | 7.18 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:03 PM UTC 24 |
| Peak memory | 250512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151868029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.151868029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.1269326019 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 122508919 ps |
| CPU time | 7.23 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:03 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269326019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.1269326019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.225135554 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 465145923 ps |
| CPU time | 6.91 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:02 PM UTC 24 |
| Peak memory | 250608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225135554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.225135554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.4282585873 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 1072574742 ps |
| CPU time | 9.34 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:05 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282585873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.4282585873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.191133968 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 1987607785 ps |
| CPU time | 7.96 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:03 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191133968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.191133968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.3056452276 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 632862376 ps |
| CPU time | 20.3 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:16 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056452276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3056452276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.3771460703 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 225380377 ps |
| CPU time | 6.13 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:02 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771460703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3771460703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.3895708265 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 106816165 ps |
| CPU time | 3.59 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:10:59 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895708265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3895708265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.3662810038 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 127273422 ps |
| CPU time | 5.05 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:01 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662810038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3662810038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.2864217674 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 317486095 ps |
| CPU time | 9.12 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:05 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864217674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2864217674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.1613676132 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 325183634 ps |
| CPU time | 4.42 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:01 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613676132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.1613676132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.463005760 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 209100324 ps |
| CPU time | 11.54 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:08 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463005760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.463005760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.2918621357 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 146548379 ps |
| CPU time | 5.65 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:02 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918621357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2918621357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.4027006959 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 866135311 ps |
| CPU time | 29.75 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:26 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027006959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.4027006959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.4148025741 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 240322784 ps |
| CPU time | 5.91 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:02 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148025741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.4148025741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.11186097 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 384991351 ps |
| CPU time | 16.79 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11186097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.11186097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.2813413931 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 483603648 ps |
| CPU time | 8.07 seconds |
| Started | Aug 25 02:10:54 PM UTC 24 |
| Finished | Aug 25 02:11:04 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813413931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2813413931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.1836506527 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 69015574 ps |
| CPU time | 2.81 seconds |
| Started | Aug 25 02:00:46 PM UTC 24 |
| Finished | Aug 25 02:00:50 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836506527 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1836506527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.916271268 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1328927335 ps |
| CPU time | 15 seconds |
| Started | Aug 25 02:00:36 PM UTC 24 |
| Finished | Aug 25 02:00:52 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916271268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.916271268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.3168586784 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1031464534 ps |
| CPU time | 41.01 seconds |
| Started | Aug 25 02:00:34 PM UTC 24 |
| Finished | Aug 25 02:01:17 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168586784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3168586784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.945580754 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1672445031 ps |
| CPU time | 10.96 seconds |
| Started | Aug 25 02:00:34 PM UTC 24 |
| Finished | Aug 25 02:00:47 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945580754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.945580754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2514772954 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 449630740 ps |
| CPU time | 7.26 seconds |
| Started | Aug 25 02:00:30 PM UTC 24 |
| Finished | Aug 25 02:00:38 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514772954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2514772954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.3895750307 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 167014092 ps |
| CPU time | 7.51 seconds |
| Started | Aug 25 02:00:38 PM UTC 24 |
| Finished | Aug 25 02:00:47 PM UTC 24 |
| Peak memory | 257440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895750307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3895750307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.3941726439 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4570393118 ps |
| CPU time | 30.08 seconds |
| Started | Aug 25 02:00:32 PM UTC 24 |
| Finished | Aug 25 02:01:04 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941726439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3941726439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.296551956 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1023259279 ps |
| CPU time | 19.79 seconds |
| Started | Aug 25 02:00:30 PM UTC 24 |
| Finished | Aug 25 02:00:51 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296551956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.296551956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.1255868475 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 117715366 ps |
| CPU time | 7.3 seconds |
| Started | Aug 25 02:00:39 PM UTC 24 |
| Finished | Aug 25 02:00:48 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255868475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1255868475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.975879713 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2242367017 ps |
| CPU time | 18.61 seconds |
| Started | Aug 25 02:00:30 PM UTC 24 |
| Finished | Aug 25 02:00:50 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975879713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.975879713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.1925792638 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 901780064 ps |
| CPU time | 6.71 seconds |
| Started | Aug 25 02:00:41 PM UTC 24 |
| Finished | Aug 25 02:00:49 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925792638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1925792638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.2601916542 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 376643174 ps |
| CPU time | 5.36 seconds |
| Started | Aug 25 02:10:55 PM UTC 24 |
| Finished | Aug 25 02:11:01 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601916542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2601916542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.2532512391 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 117714510 ps |
| CPU time | 4.42 seconds |
| Started | Aug 25 02:10:55 PM UTC 24 |
| Finished | Aug 25 02:11:00 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532512391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2532512391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.3323180380 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 719572872 ps |
| CPU time | 7.32 seconds |
| Started | Aug 25 02:11:04 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323180380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3323180380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.3893193307 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 416454674 ps |
| CPU time | 8.65 seconds |
| Started | Aug 25 02:11:04 PM UTC 24 |
| Finished | Aug 25 02:11:14 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893193307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3893193307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.3195659335 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 315278952 ps |
| CPU time | 6.58 seconds |
| Started | Aug 25 02:11:04 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195659335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3195659335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.1611583877 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 618421609 ps |
| CPU time | 12.94 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:19 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611583877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1611583877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.891554626 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 154011274 ps |
| CPU time | 4.92 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:11 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891554626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.891554626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3827776876 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 191263948 ps |
| CPU time | 11.59 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:17 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827776876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3827776876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.689373848 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 264045309 ps |
| CPU time | 6.17 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689373848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.689373848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.3026859446 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 967631367 ps |
| CPU time | 7.95 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:14 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026859446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3026859446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.650161284 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 241099372 ps |
| CPU time | 8.59 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:15 PM UTC 24 |
| Peak memory | 250940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650161284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.650161284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2488973349 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 348364474 ps |
| CPU time | 5.92 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488973349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2488973349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1016345999 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 1610307314 ps |
| CPU time | 15.19 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:22 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016345999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1016345999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3346646002 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 126788598 ps |
| CPU time | 3.92 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:10 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346646002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3346646002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.2738532467 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1348837213 ps |
| CPU time | 6.27 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738532467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2738532467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1311543850 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2560822979 ps |
| CPU time | 21.41 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311543850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1311543850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2838946326 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 136813140 ps |
| CPU time | 5.98 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838946326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2838946326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.3531657774 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 351060072 ps |
| CPU time | 9.07 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:15 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531657774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3531657774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.3088800194 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 326611557 ps |
| CPU time | 3.3 seconds |
| Started | Aug 25 02:00:54 PM UTC 24 |
| Finished | Aug 25 02:00:58 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088800194 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3088800194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.968219097 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 474704231 ps |
| CPU time | 6.34 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:00:59 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968219097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.968219097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.1233510964 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 513602702 ps |
| CPU time | 19.08 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:01:12 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233510964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1233510964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.3436426601 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 212120018 ps |
| CPU time | 5.24 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:00:58 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436426601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3436426601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.3106918405 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 418131889 ps |
| CPU time | 5.47 seconds |
| Started | Aug 25 02:00:47 PM UTC 24 |
| Finished | Aug 25 02:00:53 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106918405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3106918405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.882407909 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1542881498 ps |
| CPU time | 19.21 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:01:12 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882407909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.882407909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2201996617 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2483268790 ps |
| CPU time | 40.86 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:01:34 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201996617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2201996617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.967875099 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 112197450 ps |
| CPU time | 5.51 seconds |
| Started | Aug 25 02:00:51 PM UTC 24 |
| Finished | Aug 25 02:00:58 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967875099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.967875099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.2674179750 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 277762014 ps |
| CPU time | 9.63 seconds |
| Started | Aug 25 02:00:51 PM UTC 24 |
| Finished | Aug 25 02:01:02 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674179750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2674179750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.3756090044 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 369739046 ps |
| CPU time | 5.29 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:00:58 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756090044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3756090044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.590739133 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1243981922 ps |
| CPU time | 12.82 seconds |
| Started | Aug 25 02:00:46 PM UTC 24 |
| Finished | Aug 25 02:01:01 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590739133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.590739133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.700929824 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2267079025 ps |
| CPU time | 55.46 seconds |
| Started | Aug 25 02:00:54 PM UTC 24 |
| Finished | Aug 25 02:01:51 PM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700929824 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.700929824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.485780255 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 10113955897 ps |
| CPU time | 148.45 seconds |
| Started | Aug 25 02:00:52 PM UTC 24 |
| Finished | Aug 25 02:03:23 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485780255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.485780255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.2182644393 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 278151295 ps |
| CPU time | 5.8 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182644393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2182644393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3090807167 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 16425083249 ps |
| CPU time | 55.41 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:12:03 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090807167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3090807167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3791304426 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 1594853053 ps |
| CPU time | 6.4 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791304426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3791304426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.1906213524 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 924485009 ps |
| CPU time | 17.48 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:24 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906213524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1906213524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.764736579 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 162889161 ps |
| CPU time | 6.11 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764736579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.764736579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.256460705 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 268103193 ps |
| CPU time | 9.85 seconds |
| Started | Aug 25 02:11:05 PM UTC 24 |
| Finished | Aug 25 02:11:17 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256460705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.256460705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.261773732 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 1965915193 ps |
| CPU time | 8.47 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:15 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261773732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.261773732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.227878174 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 225955916 ps |
| CPU time | 6.91 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:14 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227878174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.227878174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.642682158 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2153513019 ps |
| CPU time | 8.85 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:16 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642682158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.642682158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.1405962517 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 104771692 ps |
| CPU time | 4.76 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405962517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1405962517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2370452710 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 143084026 ps |
| CPU time | 4.92 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370452710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2370452710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2962084101 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 99720904 ps |
| CPU time | 5.35 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962084101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2962084101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3193015949 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 427552539 ps |
| CPU time | 10.28 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:17 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193015949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3193015949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2636075105 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 111130259 ps |
| CPU time | 5.16 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:12 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636075105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2636075105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.106752785 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2732549668 ps |
| CPU time | 26.96 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:34 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106752785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.106752785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.262051480 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 228678794 ps |
| CPU time | 6.07 seconds |
| Started | Aug 25 02:11:06 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262051480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.262051480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2726055919 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 169811885 ps |
| CPU time | 7.44 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726055919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2726055919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.2146550787 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 316838753 ps |
| CPU time | 6.13 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:18 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146550787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2146550787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.3912370086 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 1043078675 ps |
| CPU time | 29.59 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:42 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912370086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3912370086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.308271814 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 629253728 ps |
| CPU time | 3.27 seconds |
| Started | Aug 25 01:55:27 PM UTC 24 |
| Finished | Aug 25 01:55:32 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308271814 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.308271814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.669029047 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 718646209 ps |
| CPU time | 28.8 seconds |
| Started | Aug 25 01:55:06 PM UTC 24 |
| Finished | Aug 25 01:55:36 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669029047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.669029047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.3804693176 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 160614758 ps |
| CPU time | 4.17 seconds |
| Started | Aug 25 01:55:12 PM UTC 24 |
| Finished | Aug 25 01:55:17 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804693176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3804693176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.4031599528 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1108521575 ps |
| CPU time | 39.52 seconds |
| Started | Aug 25 01:55:11 PM UTC 24 |
| Finished | Aug 25 01:55:52 PM UTC 24 |
| Peak memory | 257396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031599528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.4031599528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1743622943 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 289429669 ps |
| CPU time | 9.18 seconds |
| Started | Aug 25 01:55:11 PM UTC 24 |
| Finished | Aug 25 01:55:21 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743622943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1743622943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3212678683 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1603297463 ps |
| CPU time | 23.71 seconds |
| Started | Aug 25 01:55:17 PM UTC 24 |
| Finished | Aug 25 01:55:42 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212678683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3212678683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.3738066660 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3811729160 ps |
| CPU time | 25.09 seconds |
| Started | Aug 25 01:55:08 PM UTC 24 |
| Finished | Aug 25 01:55:35 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738066660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3738066660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.3906463090 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 92733044 ps |
| CPU time | 4.73 seconds |
| Started | Aug 25 01:55:19 PM UTC 24 |
| Finished | Aug 25 01:55:25 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906463090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3906463090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.3064902743 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 18837029706 ps |
| CPU time | 304.93 seconds |
| Started | Aug 25 01:55:27 PM UTC 24 |
| Finished | Aug 25 02:00:37 PM UTC 24 |
| Peak memory | 298104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064902743 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3064902743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.4256336464 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2894282832 ps |
| CPU time | 8.22 seconds |
| Started | Aug 25 01:55:01 PM UTC 24 |
| Finished | Aug 25 01:55:10 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256336464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.4256336464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.3761541331 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 97191427 ps |
| CPU time | 2.69 seconds |
| Started | Aug 25 02:01:04 PM UTC 24 |
| Finished | Aug 25 02:01:07 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761541331 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3761541331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.1580388798 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1303146510 ps |
| CPU time | 45.31 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:48 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580388798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1580388798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.1368713922 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1621159312 ps |
| CPU time | 16.33 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:19 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368713922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1368713922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.4008387058 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1029927906 ps |
| CPU time | 21.05 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:24 PM UTC 24 |
| Peak memory | 253300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008387058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.4008387058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.3251360434 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4458706712 ps |
| CPU time | 39.91 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:43 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251360434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3251360434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.3457723144 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 339281094 ps |
| CPU time | 5.61 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:08 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457723144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.3457723144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.3777745081 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1502451478 ps |
| CPU time | 13.51 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:16 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777745081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3777745081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.474667774 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2913518201 ps |
| CPU time | 9.13 seconds |
| Started | Aug 25 02:01:01 PM UTC 24 |
| Finished | Aug 25 02:01:12 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474667774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.474667774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.4151061905 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 6809791879 ps |
| CPU time | 18.48 seconds |
| Started | Aug 25 02:00:54 PM UTC 24 |
| Finished | Aug 25 02:01:14 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151061905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.4151061905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2612707979 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1354303584 ps |
| CPU time | 20.67 seconds |
| Started | Aug 25 02:01:02 PM UTC 24 |
| Finished | Aug 25 02:01:24 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612707979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2612707979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.3328947829 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1905213206 ps |
| CPU time | 7.35 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328947829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3328947829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2164366629 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 288473453 ps |
| CPU time | 6.29 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:19 PM UTC 24 |
| Peak memory | 253328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164366629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2164366629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3465035132 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 403450842 ps |
| CPU time | 5.86 seconds |
| Started | Aug 25 02:11:11 PM UTC 24 |
| Finished | Aug 25 02:11:18 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465035132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3465035132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2758162515 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 386141148 ps |
| CPU time | 6.94 seconds |
| Started | Aug 25 02:11:12 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758162515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2758162515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.331822882 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 439718210 ps |
| CPU time | 4.18 seconds |
| Started | Aug 25 02:11:12 PM UTC 24 |
| Finished | Aug 25 02:11:17 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331822882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.331822882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.3083446707 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 269647454 ps |
| CPU time | 5.83 seconds |
| Started | Aug 25 02:11:12 PM UTC 24 |
| Finished | Aug 25 02:11:19 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083446707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3083446707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.3159636889 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 175299296 ps |
| CPU time | 5.86 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:21 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159636889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3159636889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3419446210 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 655870971 ps |
| CPU time | 5.84 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:21 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419446210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3419446210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2794450933 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 235025386 ps |
| CPU time | 4.76 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794450933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2794450933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.1539550208 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 196996510 ps |
| CPU time | 3.26 seconds |
| Started | Aug 25 02:01:16 PM UTC 24 |
| Finished | Aug 25 02:01:20 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539550208 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1539550208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.1779883839 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 7308164518 ps |
| CPU time | 19.05 seconds |
| Started | Aug 25 02:01:09 PM UTC 24 |
| Finished | Aug 25 02:01:29 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779883839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1779883839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.4240560208 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1598177835 ps |
| CPU time | 25.55 seconds |
| Started | Aug 25 02:01:09 PM UTC 24 |
| Finished | Aug 25 02:01:36 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240560208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.4240560208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.2273709803 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3969972398 ps |
| CPU time | 40.73 seconds |
| Started | Aug 25 02:01:09 PM UTC 24 |
| Finished | Aug 25 02:01:51 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273709803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2273709803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.4001638892 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2036844731 ps |
| CPU time | 30.14 seconds |
| Started | Aug 25 02:01:14 PM UTC 24 |
| Finished | Aug 25 02:01:45 PM UTC 24 |
| Peak memory | 255408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001638892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.4001638892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2251760938 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2443360242 ps |
| CPU time | 8.13 seconds |
| Started | Aug 25 02:01:14 PM UTC 24 |
| Finished | Aug 25 02:01:23 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251760938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2251760938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.3116487047 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 551938628 ps |
| CPU time | 11.05 seconds |
| Started | Aug 25 02:01:09 PM UTC 24 |
| Finished | Aug 25 02:01:21 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116487047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3116487047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.1096947006 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 5698498708 ps |
| CPU time | 18.04 seconds |
| Started | Aug 25 02:01:07 PM UTC 24 |
| Finished | Aug 25 02:01:27 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096947006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1096947006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.707532953 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 850790348 ps |
| CPU time | 14.53 seconds |
| Started | Aug 25 02:01:14 PM UTC 24 |
| Finished | Aug 25 02:01:29 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707532953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.707532953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.1509401391 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2067593724 ps |
| CPU time | 11.4 seconds |
| Started | Aug 25 02:01:05 PM UTC 24 |
| Finished | Aug 25 02:01:18 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509401391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1509401391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.2999532144 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 8529494655 ps |
| CPU time | 152.14 seconds |
| Started | Aug 25 02:01:16 PM UTC 24 |
| Finished | Aug 25 02:03:51 PM UTC 24 |
| Peak memory | 269808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999532144 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.2999532144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2463622262 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 55574496411 ps |
| CPU time | 186.46 seconds |
| Started | Aug 25 02:01:14 PM UTC 24 |
| Finished | Aug 25 02:04:24 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2463622262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.otp_ctrl_stress_all_with_rand_reset.2463622262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.2054944715 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 928263477 ps |
| CPU time | 26.64 seconds |
| Started | Aug 25 02:01:14 PM UTC 24 |
| Finished | Aug 25 02:01:42 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054944715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2054944715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1799452307 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2600578407 ps |
| CPU time | 4.49 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:19 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799452307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1799452307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2518900651 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 132123195 ps |
| CPU time | 5.74 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:21 PM UTC 24 |
| Peak memory | 251000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518900651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2518900651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2784825517 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 289714317 ps |
| CPU time | 3.72 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:19 PM UTC 24 |
| Peak memory | 251032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784825517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2784825517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1088967658 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 385104875 ps |
| CPU time | 5.29 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088967658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1088967658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3844296227 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2705071256 ps |
| CPU time | 8 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:23 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844296227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3844296227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2027537993 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 1793703242 ps |
| CPU time | 6.86 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:22 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027537993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2027537993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.1357658961 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 416059411 ps |
| CPU time | 7.88 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:23 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357658961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1357658961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2591888539 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 343920980 ps |
| CPU time | 5.74 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:21 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591888539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2591888539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1048953934 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 227269034 ps |
| CPU time | 4.65 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:20 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048953934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1048953934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.2110876814 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 105589186 ps |
| CPU time | 3.21 seconds |
| Started | Aug 25 02:01:30 PM UTC 24 |
| Finished | Aug 25 02:01:35 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110876814 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2110876814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.2420691128 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 763633766 ps |
| CPU time | 12.28 seconds |
| Started | Aug 25 02:01:23 PM UTC 24 |
| Finished | Aug 25 02:01:36 PM UTC 24 |
| Peak memory | 253720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420691128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2420691128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.1963794024 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3976547630 ps |
| CPU time | 27.16 seconds |
| Started | Aug 25 02:01:21 PM UTC 24 |
| Finished | Aug 25 02:01:50 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963794024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1963794024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.4271121817 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 8071456369 ps |
| CPU time | 45.84 seconds |
| Started | Aug 25 02:01:20 PM UTC 24 |
| Finished | Aug 25 02:02:08 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271121817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.4271121817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.2936342618 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 127146083 ps |
| CPU time | 5.11 seconds |
| Started | Aug 25 02:01:17 PM UTC 24 |
| Finished | Aug 25 02:01:23 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936342618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.2936342618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2430287548 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2261570278 ps |
| CPU time | 7.67 seconds |
| Started | Aug 25 02:01:24 PM UTC 24 |
| Finished | Aug 25 02:01:33 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430287548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2430287548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.654636573 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 9997137991 ps |
| CPU time | 42.43 seconds |
| Started | Aug 25 02:01:24 PM UTC 24 |
| Finished | Aug 25 02:02:08 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654636573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.654636573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.2067310447 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3851364126 ps |
| CPU time | 13.89 seconds |
| Started | Aug 25 02:01:19 PM UTC 24 |
| Finished | Aug 25 02:01:34 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067310447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2067310447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.2128904554 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1168674891 ps |
| CPU time | 25.57 seconds |
| Started | Aug 25 02:01:19 PM UTC 24 |
| Finished | Aug 25 02:01:46 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128904554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2128904554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.2643288810 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1890810227 ps |
| CPU time | 8.37 seconds |
| Started | Aug 25 02:01:26 PM UTC 24 |
| Finished | Aug 25 02:01:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643288810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2643288810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.11695568 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 141357564 ps |
| CPU time | 6.25 seconds |
| Started | Aug 25 02:01:17 PM UTC 24 |
| Finished | Aug 25 02:01:24 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11695568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.11695568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.2901211050 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 10286750806 ps |
| CPU time | 248.96 seconds |
| Started | Aug 25 02:01:28 PM UTC 24 |
| Finished | Aug 25 02:05:42 PM UTC 24 |
| Peak memory | 268084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901211050 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.2901211050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.1784758265 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 13366323748 ps |
| CPU time | 254.56 seconds |
| Started | Aug 25 02:01:26 PM UTC 24 |
| Finished | Aug 25 02:05:45 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1784758265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.otp_ctrl_stress_all_with_rand_reset.1784758265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.2676144841 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1245686101 ps |
| CPU time | 36.1 seconds |
| Started | Aug 25 02:01:26 PM UTC 24 |
| Finished | Aug 25 02:02:03 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676144841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2676144841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2024435035 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 1723164253 ps |
| CPU time | 7.73 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:23 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024435035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2024435035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1012198716 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 147868523 ps |
| CPU time | 5.12 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:21 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012198716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1012198716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.1415810946 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 163117883 ps |
| CPU time | 5.45 seconds |
| Started | Aug 25 02:11:14 PM UTC 24 |
| Finished | Aug 25 02:11:21 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415810946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.1415810946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3041887301 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 333115381 ps |
| CPU time | 6.16 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041887301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3041887301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1570436058 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 476013964 ps |
| CPU time | 6.96 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570436058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1570436058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2182631646 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 729046693 ps |
| CPU time | 6.67 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182631646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2182631646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.1321035950 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 470137636 ps |
| CPU time | 3.92 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:26 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321035950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.1321035950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.2620244071 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 2092438926 ps |
| CPU time | 7.75 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620244071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2620244071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2532872947 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 151936363 ps |
| CPU time | 5.97 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532872947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2532872947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.2198689020 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 2239465589 ps |
| CPU time | 8.44 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198689020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2198689020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.1144134525 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 89321596 ps |
| CPU time | 2.47 seconds |
| Started | Aug 25 02:01:45 PM UTC 24 |
| Finished | Aug 25 02:01:49 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144134525 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1144134525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.827700310 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2839860068 ps |
| CPU time | 36.7 seconds |
| Started | Aug 25 02:01:37 PM UTC 24 |
| Finished | Aug 25 02:02:16 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827700310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.827700310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.2921983053 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 357985352 ps |
| CPU time | 25.66 seconds |
| Started | Aug 25 02:01:36 PM UTC 24 |
| Finished | Aug 25 02:02:03 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921983053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2921983053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.3253504045 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3851916481 ps |
| CPU time | 23.78 seconds |
| Started | Aug 25 02:01:36 PM UTC 24 |
| Finished | Aug 25 02:02:01 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253504045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3253504045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.1526303420 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 146172120 ps |
| CPU time | 4.7 seconds |
| Started | Aug 25 02:01:32 PM UTC 24 |
| Finished | Aug 25 02:01:38 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526303420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1526303420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.1210337620 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 12259198906 ps |
| CPU time | 44.08 seconds |
| Started | Aug 25 02:01:38 PM UTC 24 |
| Finished | Aug 25 02:02:24 PM UTC 24 |
| Peak memory | 255444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210337620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.1210337620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.3537631865 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2717656186 ps |
| CPU time | 11.58 seconds |
| Started | Aug 25 02:01:38 PM UTC 24 |
| Finished | Aug 25 02:01:51 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537631865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3537631865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.1559168954 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 645759629 ps |
| CPU time | 10.64 seconds |
| Started | Aug 25 02:01:36 PM UTC 24 |
| Finished | Aug 25 02:01:48 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559168954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1559168954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.1141153723 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2546433490 ps |
| CPU time | 7.23 seconds |
| Started | Aug 25 02:01:34 PM UTC 24 |
| Finished | Aug 25 02:01:42 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141153723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1141153723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.3842463546 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 133404733 ps |
| CPU time | 6.1 seconds |
| Started | Aug 25 02:01:39 PM UTC 24 |
| Finished | Aug 25 02:01:46 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842463546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3842463546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.4002277148 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 642293705 ps |
| CPU time | 7.02 seconds |
| Started | Aug 25 02:01:30 PM UTC 24 |
| Finished | Aug 25 02:01:39 PM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002277148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.4002277148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.2547692700 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 76365646138 ps |
| CPU time | 283.09 seconds |
| Started | Aug 25 02:01:43 PM UTC 24 |
| Finished | Aug 25 02:06:32 PM UTC 24 |
| Peak memory | 274032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547692700 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.2547692700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1756476376 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3091567587 ps |
| CPU time | 125.57 seconds |
| Started | Aug 25 02:01:43 PM UTC 24 |
| Finished | Aug 25 02:03:52 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1756476376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.1756476376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.3888404265 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 14956141241 ps |
| CPU time | 47.02 seconds |
| Started | Aug 25 02:01:40 PM UTC 24 |
| Finished | Aug 25 02:02:29 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888404265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3888404265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.857340051 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2073017545 ps |
| CPU time | 6.43 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857340051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.857340051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.1659673257 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 97541847 ps |
| CPU time | 4.43 seconds |
| Started | Aug 25 02:11:21 PM UTC 24 |
| Finished | Aug 25 02:11:27 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659673257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1659673257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2130120330 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 320388109 ps |
| CPU time | 6.09 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 250572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130120330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2130120330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.481088123 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 156857702 ps |
| CPU time | 6.11 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481088123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.481088123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.1452613265 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 132749728 ps |
| CPU time | 4.92 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 250200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452613265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1452613265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.4013023069 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 1753937288 ps |
| CPU time | 5.56 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013023069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.4013023069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.3257067250 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 426074119 ps |
| CPU time | 6 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257067250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3257067250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.4231071028 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 1266869748 ps |
| CPU time | 5.47 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231071028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4231071028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.3587634546 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 250154840 ps |
| CPU time | 5.38 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587634546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3587634546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.2700992078 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 546070227 ps |
| CPU time | 6.02 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700992078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2700992078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.1583937740 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 45579671 ps |
| CPU time | 2.4 seconds |
| Started | Aug 25 02:01:58 PM UTC 24 |
| Finished | Aug 25 02:02:02 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583937740 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1583937740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.4199030914 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 313482977 ps |
| CPU time | 11.79 seconds |
| Started | Aug 25 02:01:51 PM UTC 24 |
| Finished | Aug 25 02:02:03 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199030914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.4199030914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.2352740475 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 488026747 ps |
| CPU time | 10.13 seconds |
| Started | Aug 25 02:01:50 PM UTC 24 |
| Finished | Aug 25 02:02:02 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352740475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2352740475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.3667404246 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1581961195 ps |
| CPU time | 24.47 seconds |
| Started | Aug 25 02:01:49 PM UTC 24 |
| Finished | Aug 25 02:02:15 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667404246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3667404246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.1334974034 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 103519480 ps |
| CPU time | 4.58 seconds |
| Started | Aug 25 02:01:49 PM UTC 24 |
| Finished | Aug 25 02:01:54 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334974034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1334974034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.2286137372 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 10682719240 ps |
| CPU time | 122.69 seconds |
| Started | Aug 25 02:01:53 PM UTC 24 |
| Finished | Aug 25 02:03:59 PM UTC 24 |
| Peak memory | 253852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286137372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2286137372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.1874946227 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 336580053 ps |
| CPU time | 11.87 seconds |
| Started | Aug 25 02:01:54 PM UTC 24 |
| Finished | Aug 25 02:02:07 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874946227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1874946227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.136888259 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 75292287 ps |
| CPU time | 5.95 seconds |
| Started | Aug 25 02:01:49 PM UTC 24 |
| Finished | Aug 25 02:01:56 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136888259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.136888259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.3495275168 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 284036103 ps |
| CPU time | 7.64 seconds |
| Started | Aug 25 02:01:49 PM UTC 24 |
| Finished | Aug 25 02:01:57 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495275168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3495275168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.2510901216 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1985179229 ps |
| CPU time | 7.5 seconds |
| Started | Aug 25 02:01:54 PM UTC 24 |
| Finished | Aug 25 02:02:02 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510901216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2510901216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.4237351546 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2430153072 ps |
| CPU time | 13.65 seconds |
| Started | Aug 25 02:01:46 PM UTC 24 |
| Finished | Aug 25 02:02:01 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237351546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.4237351546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.2410320195 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 10414242357 ps |
| CPU time | 200.57 seconds |
| Started | Aug 25 02:01:57 PM UTC 24 |
| Finished | Aug 25 02:05:21 PM UTC 24 |
| Peak memory | 267768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410320195 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.2410320195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.1149888837 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 607363701 ps |
| CPU time | 26.07 seconds |
| Started | Aug 25 02:01:54 PM UTC 24 |
| Finished | Aug 25 02:02:21 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149888837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1149888837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3843533270 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 182556964 ps |
| CPU time | 5.61 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843533270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3843533270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2859885011 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 158889511 ps |
| CPU time | 5.74 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859885011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2859885011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1687271047 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 408320107 ps |
| CPU time | 4.9 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687271047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1687271047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3498318620 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 156526600 ps |
| CPU time | 5.48 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498318620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3498318620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.1433726200 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 547218008 ps |
| CPU time | 7.1 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433726200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1433726200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.3660664062 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 299462376 ps |
| CPU time | 5.18 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660664062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3660664062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.2503608232 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 150047736 ps |
| CPU time | 5.23 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:29 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503608232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2503608232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.4260424258 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 416669299 ps |
| CPU time | 7.19 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260424258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4260424258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.3543157951 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 1664788044 ps |
| CPU time | 8.71 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:32 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543157951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3543157951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.953775283 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 81220432 ps |
| CPU time | 3.04 seconds |
| Started | Aug 25 02:02:16 PM UTC 24 |
| Finished | Aug 25 02:02:20 PM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953775283 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.953775283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.4261079619 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 922192604 ps |
| CPU time | 33.74 seconds |
| Started | Aug 25 02:02:05 PM UTC 24 |
| Finished | Aug 25 02:02:41 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261079619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.4261079619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.1517731477 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3066104239 ps |
| CPU time | 46.14 seconds |
| Started | Aug 25 02:02:03 PM UTC 24 |
| Finished | Aug 25 02:02:51 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517731477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1517731477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.3683522892 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 971475292 ps |
| CPU time | 24.26 seconds |
| Started | Aug 25 02:02:06 PM UTC 24 |
| Finished | Aug 25 02:02:31 PM UTC 24 |
| Peak memory | 253696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683522892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3683522892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.2003531709 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 322325490 ps |
| CPU time | 20.21 seconds |
| Started | Aug 25 02:02:08 PM UTC 24 |
| Finished | Aug 25 02:02:29 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003531709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2003531709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.4254108497 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3490367865 ps |
| CPU time | 17.2 seconds |
| Started | Aug 25 02:02:03 PM UTC 24 |
| Finished | Aug 25 02:02:22 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254108497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.4254108497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2996666237 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9951530545 ps |
| CPU time | 47.93 seconds |
| Started | Aug 25 02:02:03 PM UTC 24 |
| Finished | Aug 25 02:02:53 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996666237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2996666237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.4107149612 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 282714209 ps |
| CPU time | 7.24 seconds |
| Started | Aug 25 02:02:09 PM UTC 24 |
| Finished | Aug 25 02:02:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107149612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.4107149612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.3408062698 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 146204494 ps |
| CPU time | 5.46 seconds |
| Started | Aug 25 02:02:03 PM UTC 24 |
| Finished | Aug 25 02:02:09 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408062698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3408062698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.99752245 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 15136234868 ps |
| CPU time | 93.8 seconds |
| Started | Aug 25 02:02:12 PM UTC 24 |
| Finished | Aug 25 02:03:48 PM UTC 24 |
| Peak memory | 255576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99752245 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.99752245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2849751798 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 759432273 ps |
| CPU time | 23.72 seconds |
| Started | Aug 25 02:02:09 PM UTC 24 |
| Finished | Aug 25 02:02:34 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849751798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2849751798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2830088486 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 1922998635 ps |
| CPU time | 8.6 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:32 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830088486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2830088486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1039287926 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 2157830188 ps |
| CPU time | 6.84 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039287926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1039287926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.1466071194 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 1996522151 ps |
| CPU time | 9.46 seconds |
| Started | Aug 25 02:11:22 PM UTC 24 |
| Finished | Aug 25 02:11:33 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466071194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1466071194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.4208385008 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 415187060 ps |
| CPU time | 6.4 seconds |
| Started | Aug 25 02:11:23 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208385008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4208385008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.3473640624 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 279870345 ps |
| CPU time | 5.91 seconds |
| Started | Aug 25 02:11:23 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473640624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3473640624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.4234078336 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 122938761 ps |
| CPU time | 4.53 seconds |
| Started | Aug 25 02:11:23 PM UTC 24 |
| Finished | Aug 25 02:11:28 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234078336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.4234078336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.923994187 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2587951938 ps |
| CPU time | 10.21 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:36 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923994187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.923994187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.707042042 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 138861340 ps |
| CPU time | 5.6 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707042042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.707042042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2483726182 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 154909169 ps |
| CPU time | 6.58 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:32 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483726182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2483726182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3797173662 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 194179662 ps |
| CPU time | 4.33 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:30 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797173662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3797173662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.562478271 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 73402028 ps |
| CPU time | 2.36 seconds |
| Started | Aug 25 02:02:31 PM UTC 24 |
| Finished | Aug 25 02:02:35 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562478271 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.562478271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.1603912184 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 29585209116 ps |
| CPU time | 72.03 seconds |
| Started | Aug 25 02:02:23 PM UTC 24 |
| Finished | Aug 25 02:03:37 PM UTC 24 |
| Peak memory | 253660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603912184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1603912184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.2983094177 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 489699333 ps |
| CPU time | 18.43 seconds |
| Started | Aug 25 02:02:21 PM UTC 24 |
| Finished | Aug 25 02:02:41 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983094177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2983094177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.3612182391 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 30289607824 ps |
| CPU time | 76.64 seconds |
| Started | Aug 25 02:02:21 PM UTC 24 |
| Finished | Aug 25 02:03:40 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612182391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3612182391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.3180412345 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2019511740 ps |
| CPU time | 11.08 seconds |
| Started | Aug 25 02:02:18 PM UTC 24 |
| Finished | Aug 25 02:02:30 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180412345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3180412345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.720166246 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 888440841 ps |
| CPU time | 31.92 seconds |
| Started | Aug 25 02:02:23 PM UTC 24 |
| Finished | Aug 25 02:02:56 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720166246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.720166246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.4250754723 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 443037451 ps |
| CPU time | 20.14 seconds |
| Started | Aug 25 02:02:23 PM UTC 24 |
| Finished | Aug 25 02:02:44 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250754723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.4250754723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.2794964066 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 8182279770 ps |
| CPU time | 26.7 seconds |
| Started | Aug 25 02:02:18 PM UTC 24 |
| Finished | Aug 25 02:02:46 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794964066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2794964066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.152504443 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3255450613 ps |
| CPU time | 37.55 seconds |
| Started | Aug 25 02:02:18 PM UTC 24 |
| Finished | Aug 25 02:02:57 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152504443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.152504443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.1588502921 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 83157124 ps |
| CPU time | 4.21 seconds |
| Started | Aug 25 02:02:25 PM UTC 24 |
| Finished | Aug 25 02:02:31 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588502921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1588502921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.3857238446 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 195701016 ps |
| CPU time | 4.56 seconds |
| Started | Aug 25 02:02:16 PM UTC 24 |
| Finished | Aug 25 02:02:22 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857238446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3857238446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.1776937826 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 14888660929 ps |
| CPU time | 146.64 seconds |
| Started | Aug 25 02:02:31 PM UTC 24 |
| Finished | Aug 25 02:05:01 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776937826 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.1776937826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.197619907 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 8957448146 ps |
| CPU time | 109.68 seconds |
| Started | Aug 25 02:02:30 PM UTC 24 |
| Finished | Aug 25 02:04:23 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=197619907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.197619907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.1077520986 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1496209474 ps |
| CPU time | 43.16 seconds |
| Started | Aug 25 02:02:30 PM UTC 24 |
| Finished | Aug 25 02:03:15 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077520986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1077520986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.3786809754 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 198380044 ps |
| CPU time | 5.29 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786809754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3786809754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.4107444726 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 155061856 ps |
| CPU time | 5.67 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:32 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107444726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.4107444726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1185016553 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 1645329475 ps |
| CPU time | 5.88 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:32 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185016553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1185016553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.2450117510 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 559584923 ps |
| CPU time | 4.98 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450117510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2450117510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1182049610 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 113767663 ps |
| CPU time | 4.89 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182049610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1182049610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.841107282 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 194941256 ps |
| CPU time | 5.57 seconds |
| Started | Aug 25 02:11:25 PM UTC 24 |
| Finished | Aug 25 02:11:32 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841107282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.841107282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.2645160556 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 191130079 ps |
| CPU time | 5.29 seconds |
| Started | Aug 25 02:11:27 PM UTC 24 |
| Finished | Aug 25 02:11:33 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645160556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2645160556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.383030633 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 180055583 ps |
| CPU time | 5.14 seconds |
| Started | Aug 25 02:11:27 PM UTC 24 |
| Finished | Aug 25 02:11:33 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383030633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.383030633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.2677672540 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 292003102 ps |
| CPU time | 3.94 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677672540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2677672540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.1615639420 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 208608787 ps |
| CPU time | 4.63 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615639420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1615639420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2798185230 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 502354510 ps |
| CPU time | 6.03 seconds |
| Started | Aug 25 02:02:55 PM UTC 24 |
| Finished | Aug 25 02:03:03 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798185230 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2798185230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.4293258516 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 8168525688 ps |
| CPU time | 49.5 seconds |
| Started | Aug 25 02:02:46 PM UTC 24 |
| Finished | Aug 25 02:03:37 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293258516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.4293258516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.908544821 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4974832226 ps |
| CPU time | 49.71 seconds |
| Started | Aug 25 02:02:43 PM UTC 24 |
| Finished | Aug 25 02:03:34 PM UTC 24 |
| Peak memory | 257408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908544821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.908544821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.2139316589 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3419454722 ps |
| CPU time | 31.04 seconds |
| Started | Aug 25 02:02:42 PM UTC 24 |
| Finished | Aug 25 02:03:14 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139316589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2139316589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.1373458609 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 186806613 ps |
| CPU time | 4.9 seconds |
| Started | Aug 25 02:02:36 PM UTC 24 |
| Finished | Aug 25 02:02:42 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373458609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1373458609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.1087092537 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 451600897 ps |
| CPU time | 7.82 seconds |
| Started | Aug 25 02:02:46 PM UTC 24 |
| Finished | Aug 25 02:02:55 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087092537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.1087092537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.1654148338 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1111852778 ps |
| CPU time | 36.36 seconds |
| Started | Aug 25 02:02:46 PM UTC 24 |
| Finished | Aug 25 02:03:24 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654148338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1654148338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.3656933900 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 276765040 ps |
| CPU time | 18.2 seconds |
| Started | Aug 25 02:02:42 PM UTC 24 |
| Finished | Aug 25 02:03:01 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656933900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3656933900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.704784260 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 378335236 ps |
| CPU time | 7.23 seconds |
| Started | Aug 25 02:02:36 PM UTC 24 |
| Finished | Aug 25 02:02:44 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704784260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.704784260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.759532966 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 156798992 ps |
| CPU time | 7.23 seconds |
| Started | Aug 25 02:02:47 PM UTC 24 |
| Finished | Aug 25 02:02:55 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759532966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.759532966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.3744635103 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3283700208 ps |
| CPU time | 10.21 seconds |
| Started | Aug 25 02:02:33 PM UTC 24 |
| Finished | Aug 25 02:02:44 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744635103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3744635103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2700201640 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 15347534426 ps |
| CPU time | 212.36 seconds |
| Started | Aug 25 02:02:53 PM UTC 24 |
| Finished | Aug 25 02:06:29 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2700201640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.otp_ctrl_stress_all_with_rand_reset.2700201640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1396354347 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 923442340 ps |
| CPU time | 29.02 seconds |
| Started | Aug 25 02:02:49 PM UTC 24 |
| Finished | Aug 25 02:03:20 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396354347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1396354347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.920161342 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 2315041407 ps |
| CPU time | 9.83 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:41 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920161342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.920161342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3120422040 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 432542926 ps |
| CPU time | 5.25 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:36 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120422040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3120422040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3982155085 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 98235717 ps |
| CPU time | 4.44 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982155085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3982155085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3802856106 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2143783560 ps |
| CPU time | 6.73 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:38 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802856106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3802856106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.211529575 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 479588141 ps |
| CPU time | 4.03 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211529575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.211529575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.2316344177 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 280172958 ps |
| CPU time | 4.66 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:36 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316344177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2316344177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3596234287 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 1972645645 ps |
| CPU time | 7.94 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:39 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596234287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3596234287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.1535133278 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 119063975 ps |
| CPU time | 3.63 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535133278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1535133278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.3141588113 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 343904924 ps |
| CPU time | 4.73 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:36 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141588113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3141588113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3446820297 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 164310966 ps |
| CPU time | 5.51 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:37 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446820297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3446820297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.2666888960 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 73260110 ps |
| CPU time | 2.86 seconds |
| Started | Aug 25 02:03:17 PM UTC 24 |
| Finished | Aug 25 02:03:21 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666888960 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.2666888960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.1266754572 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 176349635 ps |
| CPU time | 5.61 seconds |
| Started | Aug 25 02:03:04 PM UTC 24 |
| Finished | Aug 25 02:03:11 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266754572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1266754572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.1666700085 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1664940064 ps |
| CPU time | 28.54 seconds |
| Started | Aug 25 02:03:04 PM UTC 24 |
| Finished | Aug 25 02:03:34 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666700085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1666700085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.968388238 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2326618587 ps |
| CPU time | 32.86 seconds |
| Started | Aug 25 02:03:04 PM UTC 24 |
| Finished | Aug 25 02:03:38 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968388238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.968388238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.1690159843 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2130061607 ps |
| CPU time | 7.02 seconds |
| Started | Aug 25 02:02:57 PM UTC 24 |
| Finished | Aug 25 02:03:05 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690159843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1690159843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.1284162084 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 4999398505 ps |
| CPU time | 63.69 seconds |
| Started | Aug 25 02:03:06 PM UTC 24 |
| Finished | Aug 25 02:04:12 PM UTC 24 |
| Peak memory | 257920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284162084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1284162084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2842336143 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 10536982123 ps |
| CPU time | 36.27 seconds |
| Started | Aug 25 02:03:07 PM UTC 24 |
| Finished | Aug 25 02:03:45 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842336143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2842336143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.1968890092 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 219441507 ps |
| CPU time | 5.83 seconds |
| Started | Aug 25 02:02:59 PM UTC 24 |
| Finished | Aug 25 02:03:06 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968890092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1968890092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.434288797 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1481901540 ps |
| CPU time | 23.87 seconds |
| Started | Aug 25 02:02:57 PM UTC 24 |
| Finished | Aug 25 02:03:22 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434288797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.434288797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.3604210359 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 612088682 ps |
| CPU time | 15.2 seconds |
| Started | Aug 25 02:03:11 PM UTC 24 |
| Finished | Aug 25 02:03:27 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604210359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3604210359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3781998724 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3283960235 ps |
| CPU time | 12.89 seconds |
| Started | Aug 25 02:02:56 PM UTC 24 |
| Finished | Aug 25 02:03:10 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781998724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3781998724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.662692292 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 42143198318 ps |
| CPU time | 151.32 seconds |
| Started | Aug 25 02:03:15 PM UTC 24 |
| Finished | Aug 25 02:05:50 PM UTC 24 |
| Peak memory | 269896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662692292 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.662692292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.1000130077 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1040162556 ps |
| CPU time | 29.06 seconds |
| Started | Aug 25 02:03:12 PM UTC 24 |
| Finished | Aug 25 02:03:42 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000130077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1000130077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.3069618870 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 1622281842 ps |
| CPU time | 5.72 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:37 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069618870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3069618870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3729813355 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 585374093 ps |
| CPU time | 4.72 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:36 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729813355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3729813355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.1607728795 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 137368260 ps |
| CPU time | 4.48 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:36 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607728795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1607728795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.251470284 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 147256457 ps |
| CPU time | 3.58 seconds |
| Started | Aug 25 02:11:30 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251470284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.251470284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3572129798 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 160635875 ps |
| CPU time | 5.76 seconds |
| Started | Aug 25 02:11:37 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572129798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3572129798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.2578380451 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 243972076 ps |
| CPU time | 4.93 seconds |
| Started | Aug 25 02:11:37 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578380451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2578380451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3064543524 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 277307103 ps |
| CPU time | 6.21 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064543524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3064543524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1324288592 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 1745679604 ps |
| CPU time | 5.84 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324288592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1324288592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.631357563 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 110113934 ps |
| CPU time | 5.15 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631357563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.631357563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.346686617 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 119104937 ps |
| CPU time | 4 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346686617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.346686617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.1666040327 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 890983958 ps |
| CPU time | 3.53 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:03:47 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666040327 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1666040327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.3773674714 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5625736851 ps |
| CPU time | 22.73 seconds |
| Started | Aug 25 02:03:24 PM UTC 24 |
| Finished | Aug 25 02:03:48 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773674714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3773674714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3148101921 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 229084049 ps |
| CPU time | 6.84 seconds |
| Started | Aug 25 02:03:22 PM UTC 24 |
| Finished | Aug 25 02:03:30 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148101921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3148101921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3565561032 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2860961169 ps |
| CPU time | 49.36 seconds |
| Started | Aug 25 02:03:26 PM UTC 24 |
| Finished | Aug 25 02:04:17 PM UTC 24 |
| Peak memory | 268124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565561032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3565561032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.1908365394 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 341862473 ps |
| CPU time | 19.51 seconds |
| Started | Aug 25 02:03:26 PM UTC 24 |
| Finished | Aug 25 02:03:47 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908365394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1908365394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.625989489 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 80475978 ps |
| CPU time | 3.09 seconds |
| Started | Aug 25 02:03:21 PM UTC 24 |
| Finished | Aug 25 02:03:25 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625989489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.625989489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.1013881061 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 8485370346 ps |
| CPU time | 47.79 seconds |
| Started | Aug 25 02:03:19 PM UTC 24 |
| Finished | Aug 25 02:04:09 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013881061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1013881061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.1236265938 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 530535281 ps |
| CPU time | 8.2 seconds |
| Started | Aug 25 02:03:27 PM UTC 24 |
| Finished | Aug 25 02:03:36 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236265938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1236265938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.1346546258 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 565275916 ps |
| CPU time | 15.08 seconds |
| Started | Aug 25 02:03:18 PM UTC 24 |
| Finished | Aug 25 02:03:34 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346546258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1346546258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.1436658320 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 8481841214 ps |
| CPU time | 62.32 seconds |
| Started | Aug 25 02:03:31 PM UTC 24 |
| Finished | Aug 25 02:04:35 PM UTC 24 |
| Peak memory | 253788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436658320 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.1436658320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.296952191 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 187526010 ps |
| CPU time | 8.23 seconds |
| Started | Aug 25 02:03:28 PM UTC 24 |
| Finished | Aug 25 02:03:38 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296952191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.296952191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.1479242503 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 533033786 ps |
| CPU time | 6.5 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479242503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1479242503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.914378591 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 179333125 ps |
| CPU time | 4.41 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914378591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.914378591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2823206833 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 135455315 ps |
| CPU time | 4.48 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:43 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823206833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2823206833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.312710899 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 189815472 ps |
| CPU time | 5.54 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312710899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.312710899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1108167507 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 1336081934 ps |
| CPU time | 4.65 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108167507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1108167507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.302132409 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 328292705 ps |
| CPU time | 6.41 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302132409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.302132409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2942019259 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 236799826 ps |
| CPU time | 5.71 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942019259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2942019259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.305040426 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 143097902 ps |
| CPU time | 5.54 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:45 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305040426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.305040426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.3667609340 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 157885539 ps |
| CPU time | 4.35 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667609340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3667609340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3951942601 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 120980693 ps |
| CPU time | 4.34 seconds |
| Started | Aug 25 02:11:38 PM UTC 24 |
| Finished | Aug 25 02:11:44 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951942601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3951942601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.2172978269 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 180905103 ps |
| CPU time | 2.96 seconds |
| Started | Aug 25 01:55:53 PM UTC 24 |
| Finished | Aug 25 01:55:57 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172978269 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2172978269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.952180617 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 19002957233 ps |
| CPU time | 29.36 seconds |
| Started | Aug 25 01:55:30 PM UTC 24 |
| Finished | Aug 25 01:56:01 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952180617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.952180617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.3714456086 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 22487930368 ps |
| CPU time | 61.07 seconds |
| Started | Aug 25 01:55:36 PM UTC 24 |
| Finished | Aug 25 01:56:39 PM UTC 24 |
| Peak memory | 259444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714456086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3714456086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.1873277362 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2231089722 ps |
| CPU time | 26.01 seconds |
| Started | Aug 25 01:55:36 PM UTC 24 |
| Finished | Aug 25 01:56:03 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873277362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1873277362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3895251890 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 132484355 ps |
| CPU time | 5.19 seconds |
| Started | Aug 25 01:55:28 PM UTC 24 |
| Finished | Aug 25 01:55:35 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895251890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3895251890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.250337700 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3633307409 ps |
| CPU time | 33.21 seconds |
| Started | Aug 25 01:55:39 PM UTC 24 |
| Finished | Aug 25 01:56:13 PM UTC 24 |
| Peak memory | 255456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250337700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.250337700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.681710709 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 343498390 ps |
| CPU time | 5.19 seconds |
| Started | Aug 25 01:55:32 PM UTC 24 |
| Finished | Aug 25 01:55:39 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681710709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.681710709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.3921467089 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 185820596 ps |
| CPU time | 7.81 seconds |
| Started | Aug 25 01:55:40 PM UTC 24 |
| Finished | Aug 25 01:55:49 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921467089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3921467089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.4020000529 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 19986582707 ps |
| CPU time | 247.87 seconds |
| Started | Aug 25 01:55:50 PM UTC 24 |
| Finished | Aug 25 02:00:02 PM UTC 24 |
| Peak memory | 285812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020000529 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.4020000529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.315012654 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 852997369 ps |
| CPU time | 18.78 seconds |
| Started | Aug 25 01:55:28 PM UTC 24 |
| Finished | Aug 25 01:55:49 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315012654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.315012654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.928229549 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 14884451600 ps |
| CPU time | 46.29 seconds |
| Started | Aug 25 01:55:43 PM UTC 24 |
| Finished | Aug 25 01:56:32 PM UTC 24 |
| Peak memory | 253784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928229549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.928229549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.3928460095 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 766076479 ps |
| CPU time | 3.38 seconds |
| Started | Aug 25 02:03:46 PM UTC 24 |
| Finished | Aug 25 02:03:51 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928460095 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3928460095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1150602214 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 120247191 ps |
| CPU time | 5.77 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:03:49 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150602214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1150602214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.1276371107 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 6885016903 ps |
| CPU time | 27.41 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:04:11 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276371107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.1276371107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.663072899 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2353556014 ps |
| CPU time | 33.79 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:04:18 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663072899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.663072899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.3031534163 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 240072953 ps |
| CPU time | 5.15 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:03:48 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031534163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3031534163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.1162594455 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1454960482 ps |
| CPU time | 26.91 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:04:11 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162594455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1162594455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.4238630122 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 20337738613 ps |
| CPU time | 43.38 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:04:27 PM UTC 24 |
| Peak memory | 253500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238630122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.4238630122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.183105478 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 351602742 ps |
| CPU time | 14.22 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:03:58 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183105478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.183105478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.1726641634 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 337087658 ps |
| CPU time | 8.22 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:03:52 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726641634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1726641634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.4084377442 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 198790693 ps |
| CPU time | 4.48 seconds |
| Started | Aug 25 02:03:43 PM UTC 24 |
| Finished | Aug 25 02:03:48 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084377442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.4084377442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.1629163942 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 216622377 ps |
| CPU time | 9.84 seconds |
| Started | Aug 25 02:03:42 PM UTC 24 |
| Finished | Aug 25 02:03:53 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629163942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1629163942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.967150346 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 29275878689 ps |
| CPU time | 415.02 seconds |
| Started | Aug 25 02:03:45 PM UTC 24 |
| Finished | Aug 25 02:10:47 PM UTC 24 |
| Peak memory | 268112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967150346 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.967150346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.145962997 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2757771211 ps |
| CPU time | 32.02 seconds |
| Started | Aug 25 02:03:45 PM UTC 24 |
| Finished | Aug 25 02:04:18 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145962997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.145962997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.1211434493 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 179015128 ps |
| CPU time | 2.69 seconds |
| Started | Aug 25 02:03:56 PM UTC 24 |
| Finished | Aug 25 02:04:00 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211434493 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1211434493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.2939981895 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1600604194 ps |
| CPU time | 54.51 seconds |
| Started | Aug 25 02:03:50 PM UTC 24 |
| Finished | Aug 25 02:04:46 PM UTC 24 |
| Peak memory | 255388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939981895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2939981895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.2039767338 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2081222147 ps |
| CPU time | 22.12 seconds |
| Started | Aug 25 02:03:50 PM UTC 24 |
| Finished | Aug 25 02:04:13 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039767338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2039767338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.1684148453 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 148150798 ps |
| CPU time | 7.24 seconds |
| Started | Aug 25 02:03:50 PM UTC 24 |
| Finished | Aug 25 02:03:58 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684148453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1684148453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.1581907146 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2024113322 ps |
| CPU time | 27.24 seconds |
| Started | Aug 25 02:03:51 PM UTC 24 |
| Finished | Aug 25 02:04:20 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581907146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1581907146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.662082841 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 847929361 ps |
| CPU time | 9.59 seconds |
| Started | Aug 25 02:03:51 PM UTC 24 |
| Finished | Aug 25 02:04:02 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662082841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.662082841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.479509753 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 180821972 ps |
| CPU time | 4.75 seconds |
| Started | Aug 25 02:03:50 PM UTC 24 |
| Finished | Aug 25 02:03:56 PM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479509753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.479509753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.1020368137 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1938585814 ps |
| CPU time | 21.58 seconds |
| Started | Aug 25 02:03:50 PM UTC 24 |
| Finished | Aug 25 02:04:13 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020368137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1020368137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.2277772887 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4022881404 ps |
| CPU time | 15.96 seconds |
| Started | Aug 25 02:03:55 PM UTC 24 |
| Finished | Aug 25 02:04:12 PM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277772887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2277772887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.2673153768 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 492269996 ps |
| CPU time | 16.79 seconds |
| Started | Aug 25 02:03:47 PM UTC 24 |
| Finished | Aug 25 02:04:05 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673153768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2673153768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3552295676 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 55778160097 ps |
| CPU time | 163.28 seconds |
| Started | Aug 25 02:03:55 PM UTC 24 |
| Finished | Aug 25 02:06:42 PM UTC 24 |
| Peak memory | 271832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552295676 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.3552295676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.2746527511 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2242985108 ps |
| CPU time | 8.78 seconds |
| Started | Aug 25 02:03:55 PM UTC 24 |
| Finished | Aug 25 02:04:05 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746527511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2746527511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.3293289125 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 187409629 ps |
| CPU time | 2.92 seconds |
| Started | Aug 25 02:04:13 PM UTC 24 |
| Finished | Aug 25 02:04:17 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293289125 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3293289125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.1605351475 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1048876897 ps |
| CPU time | 25.83 seconds |
| Started | Aug 25 02:04:06 PM UTC 24 |
| Finished | Aug 25 02:04:34 PM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605351475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1605351475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.3608646914 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4193018723 ps |
| CPU time | 55.32 seconds |
| Started | Aug 25 02:04:06 PM UTC 24 |
| Finished | Aug 25 02:05:03 PM UTC 24 |
| Peak memory | 259808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608646914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3608646914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.3381667744 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 568195212 ps |
| CPU time | 8.3 seconds |
| Started | Aug 25 02:04:06 PM UTC 24 |
| Finished | Aug 25 02:04:16 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381667744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3381667744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.1238876485 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 123329898 ps |
| CPU time | 4.94 seconds |
| Started | Aug 25 02:03:59 PM UTC 24 |
| Finished | Aug 25 02:04:05 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238876485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1238876485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.2437738732 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 31702428229 ps |
| CPU time | 205.98 seconds |
| Started | Aug 25 02:04:06 PM UTC 24 |
| Finished | Aug 25 02:07:36 PM UTC 24 |
| Peak memory | 257752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437738732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2437738732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.3978446851 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 5118190034 ps |
| CPU time | 71.25 seconds |
| Started | Aug 25 02:04:06 PM UTC 24 |
| Finished | Aug 25 02:05:20 PM UTC 24 |
| Peak memory | 253756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978446851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3978446851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.3063912967 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 87516805 ps |
| CPU time | 3.71 seconds |
| Started | Aug 25 02:04:01 PM UTC 24 |
| Finished | Aug 25 02:04:06 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063912967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3063912967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.2832398783 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 547187232 ps |
| CPU time | 22.72 seconds |
| Started | Aug 25 02:04:00 PM UTC 24 |
| Finished | Aug 25 02:04:24 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832398783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2832398783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.3829536058 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 204455764 ps |
| CPU time | 6.87 seconds |
| Started | Aug 25 02:04:08 PM UTC 24 |
| Finished | Aug 25 02:04:15 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829536058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3829536058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.325320197 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1195607309 ps |
| CPU time | 23.35 seconds |
| Started | Aug 25 02:03:59 PM UTC 24 |
| Finished | Aug 25 02:04:23 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325320197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.325320197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1332900679 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 16027741632 ps |
| CPU time | 213.12 seconds |
| Started | Aug 25 02:04:13 PM UTC 24 |
| Finished | Aug 25 02:07:50 PM UTC 24 |
| Peak memory | 267804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332900679 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1332900679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3331387822 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 30170859313 ps |
| CPU time | 244.25 seconds |
| Started | Aug 25 02:04:10 PM UTC 24 |
| Finished | Aug 25 02:08:19 PM UTC 24 |
| Peak memory | 274032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3331387822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.otp_ctrl_stress_all_with_rand_reset.3331387822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.3301174434 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 223094175 ps |
| CPU time | 5.78 seconds |
| Started | Aug 25 02:04:08 PM UTC 24 |
| Finished | Aug 25 02:04:14 PM UTC 24 |
| Peak memory | 251028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301174434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3301174434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.1757426326 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 154835345 ps |
| CPU time | 2.44 seconds |
| Started | Aug 25 02:04:25 PM UTC 24 |
| Finished | Aug 25 02:04:28 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757426326 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.1757426326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.2046841434 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 850854145 ps |
| CPU time | 35.79 seconds |
| Started | Aug 25 02:04:16 PM UTC 24 |
| Finished | Aug 25 02:04:54 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046841434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.2046841434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.1077773369 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1684858442 ps |
| CPU time | 34.61 seconds |
| Started | Aug 25 02:04:15 PM UTC 24 |
| Finished | Aug 25 02:04:52 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077773369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1077773369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.4136222813 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 252887226 ps |
| CPU time | 5.25 seconds |
| Started | Aug 25 02:04:15 PM UTC 24 |
| Finished | Aug 25 02:04:21 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136222813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.4136222813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.2902181859 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 325902360 ps |
| CPU time | 12.8 seconds |
| Started | Aug 25 02:04:24 PM UTC 24 |
| Finished | Aug 25 02:04:38 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902181859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2902181859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.2346875089 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 13331809472 ps |
| CPU time | 39.91 seconds |
| Started | Aug 25 02:04:24 PM UTC 24 |
| Finished | Aug 25 02:05:06 PM UTC 24 |
| Peak memory | 257508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346875089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2346875089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.519959371 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 281526115 ps |
| CPU time | 11.32 seconds |
| Started | Aug 25 02:04:15 PM UTC 24 |
| Finished | Aug 25 02:04:28 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519959371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.519959371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.2035882116 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 308054993 ps |
| CPU time | 12.22 seconds |
| Started | Aug 25 02:04:15 PM UTC 24 |
| Finished | Aug 25 02:04:28 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035882116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.2035882116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.1112700554 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3970523060 ps |
| CPU time | 14 seconds |
| Started | Aug 25 02:04:24 PM UTC 24 |
| Finished | Aug 25 02:04:40 PM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112700554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1112700554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.605408051 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 583198652 ps |
| CPU time | 14.68 seconds |
| Started | Aug 25 02:04:13 PM UTC 24 |
| Finished | Aug 25 02:04:29 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605408051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.605408051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.3899457647 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 51755179891 ps |
| CPU time | 152.72 seconds |
| Started | Aug 25 02:04:24 PM UTC 24 |
| Finished | Aug 25 02:07:00 PM UTC 24 |
| Peak memory | 257916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899457647 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.3899457647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.548652758 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 865229878 ps |
| CPU time | 28.97 seconds |
| Started | Aug 25 02:04:24 PM UTC 24 |
| Finished | Aug 25 02:04:55 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548652758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.548652758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.2370320453 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 101912088 ps |
| CPU time | 2.58 seconds |
| Started | Aug 25 02:04:35 PM UTC 24 |
| Finished | Aug 25 02:04:39 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370320453 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2370320453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1967398369 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 342236466 ps |
| CPU time | 18.09 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:04:51 PM UTC 24 |
| Peak memory | 257844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967398369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1967398369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.1813271401 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1251167016 ps |
| CPU time | 44.53 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:05:18 PM UTC 24 |
| Peak memory | 253296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813271401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1813271401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.2829820129 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 6285159381 ps |
| CPU time | 30.97 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:05:03 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829820129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2829820129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.2504500387 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 555238738 ps |
| CPU time | 8.53 seconds |
| Started | Aug 25 02:04:25 PM UTC 24 |
| Finished | Aug 25 02:04:34 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504500387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2504500387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.3405639700 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1236462729 ps |
| CPU time | 12.75 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:04:45 PM UTC 24 |
| Peak memory | 257384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405639700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3405639700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.3099467150 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1001289864 ps |
| CPU time | 41.77 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:05:15 PM UTC 24 |
| Peak memory | 257492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099467150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3099467150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.3938384095 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1052299721 ps |
| CPU time | 17.31 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:04:50 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938384095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3938384095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.3267835408 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 487867345 ps |
| CPU time | 7.86 seconds |
| Started | Aug 25 02:04:25 PM UTC 24 |
| Finished | Aug 25 02:04:34 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267835408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3267835408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.1348778266 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 269237569 ps |
| CPU time | 7.76 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:04:40 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348778266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.1348778266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1113495564 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1603371352 ps |
| CPU time | 15.96 seconds |
| Started | Aug 25 02:04:25 PM UTC 24 |
| Finished | Aug 25 02:04:42 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113495564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1113495564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.1543209205 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 369019494 ps |
| CPU time | 20.06 seconds |
| Started | Aug 25 02:04:31 PM UTC 24 |
| Finished | Aug 25 02:04:53 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543209205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1543209205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2238827715 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 157556835 ps |
| CPU time | 3.17 seconds |
| Started | Aug 25 02:04:48 PM UTC 24 |
| Finished | Aug 25 02:04:52 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238827715 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2238827715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.1342706121 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2077314714 ps |
| CPU time | 31.89 seconds |
| Started | Aug 25 02:04:41 PM UTC 24 |
| Finished | Aug 25 02:05:14 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342706121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1342706121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.313547524 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1054943112 ps |
| CPU time | 41.11 seconds |
| Started | Aug 25 02:04:40 PM UTC 24 |
| Finished | Aug 25 02:05:23 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313547524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.313547524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.3565119010 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2898474977 ps |
| CPU time | 33.38 seconds |
| Started | Aug 25 02:04:40 PM UTC 24 |
| Finished | Aug 25 02:05:15 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565119010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3565119010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.3117811200 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7755024765 ps |
| CPU time | 71.41 seconds |
| Started | Aug 25 02:04:41 PM UTC 24 |
| Finished | Aug 25 02:05:54 PM UTC 24 |
| Peak memory | 267800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117811200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3117811200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1327364289 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 648450904 ps |
| CPU time | 18.08 seconds |
| Started | Aug 25 02:04:43 PM UTC 24 |
| Finished | Aug 25 02:05:03 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327364289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1327364289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.3516382719 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1279185490 ps |
| CPU time | 12.17 seconds |
| Started | Aug 25 02:04:37 PM UTC 24 |
| Finished | Aug 25 02:04:51 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516382719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3516382719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.1647023118 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 5657522832 ps |
| CPU time | 17.5 seconds |
| Started | Aug 25 02:04:36 PM UTC 24 |
| Finished | Aug 25 02:04:55 PM UTC 24 |
| Peak memory | 250948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647023118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1647023118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.879303064 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 425852224 ps |
| CPU time | 11.38 seconds |
| Started | Aug 25 02:04:45 PM UTC 24 |
| Finished | Aug 25 02:04:57 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879303064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.879303064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.57040123 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 378158908 ps |
| CPU time | 7.75 seconds |
| Started | Aug 25 02:04:35 PM UTC 24 |
| Finished | Aug 25 02:04:44 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57040123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.57040123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.819197228 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 14789363283 ps |
| CPU time | 325.48 seconds |
| Started | Aug 25 02:04:46 PM UTC 24 |
| Finished | Aug 25 02:10:17 PM UTC 24 |
| Peak memory | 267824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819197228 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.819197228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.2683278454 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 7204668251 ps |
| CPU time | 82.16 seconds |
| Started | Aug 25 02:04:46 PM UTC 24 |
| Finished | Aug 25 02:06:10 PM UTC 24 |
| Peak memory | 268208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2683278454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.2683278454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.2165153495 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2137996438 ps |
| CPU time | 53.58 seconds |
| Started | Aug 25 02:04:45 PM UTC 24 |
| Finished | Aug 25 02:05:40 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165153495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2165153495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.909800192 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 96106097 ps |
| CPU time | 2.62 seconds |
| Started | Aug 25 02:05:06 PM UTC 24 |
| Finished | Aug 25 02:05:10 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909800192 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.909800192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.2549374582 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 713471997 ps |
| CPU time | 27.62 seconds |
| Started | Aug 25 02:04:54 PM UTC 24 |
| Finished | Aug 25 02:05:23 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549374582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2549374582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.925840342 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 9530607927 ps |
| CPU time | 38.86 seconds |
| Started | Aug 25 02:04:54 PM UTC 24 |
| Finished | Aug 25 02:05:34 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925840342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.925840342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.199050571 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 954141672 ps |
| CPU time | 30.69 seconds |
| Started | Aug 25 02:04:54 PM UTC 24 |
| Finished | Aug 25 02:05:26 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199050571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.199050571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.4291567899 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 188788164 ps |
| CPU time | 7.51 seconds |
| Started | Aug 25 02:04:52 PM UTC 24 |
| Finished | Aug 25 02:05:00 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291567899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.4291567899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.1391823696 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 250024728 ps |
| CPU time | 8.73 seconds |
| Started | Aug 25 02:04:56 PM UTC 24 |
| Finished | Aug 25 02:05:06 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391823696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1391823696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.1611953633 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1080764662 ps |
| CPU time | 31.77 seconds |
| Started | Aug 25 02:04:56 PM UTC 24 |
| Finished | Aug 25 02:05:30 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611953633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1611953633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.1958900631 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 628631395 ps |
| CPU time | 21.1 seconds |
| Started | Aug 25 02:04:52 PM UTC 24 |
| Finished | Aug 25 02:05:14 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958900631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1958900631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.1987433571 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1033333382 ps |
| CPU time | 23.49 seconds |
| Started | Aug 25 02:04:52 PM UTC 24 |
| Finished | Aug 25 02:05:17 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987433571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1987433571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.1871871055 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 476957632 ps |
| CPU time | 7.64 seconds |
| Started | Aug 25 02:04:56 PM UTC 24 |
| Finished | Aug 25 02:05:05 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871871055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1871871055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.793927242 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 133423094 ps |
| CPU time | 5.34 seconds |
| Started | Aug 25 02:04:52 PM UTC 24 |
| Finished | Aug 25 02:04:58 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793927242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.793927242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.1716084965 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 446358875 ps |
| CPU time | 20.7 seconds |
| Started | Aug 25 02:04:58 PM UTC 24 |
| Finished | Aug 25 02:05:20 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716084965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1716084965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.2629079948 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 97111283 ps |
| CPU time | 2.47 seconds |
| Started | Aug 25 02:05:17 PM UTC 24 |
| Finished | Aug 25 02:05:21 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629079948 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2629079948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.2671495997 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2718790431 ps |
| CPU time | 32.56 seconds |
| Started | Aug 25 02:05:12 PM UTC 24 |
| Finished | Aug 25 02:05:46 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671495997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2671495997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.2730959461 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 7609744516 ps |
| CPU time | 24.61 seconds |
| Started | Aug 25 02:05:12 PM UTC 24 |
| Finished | Aug 25 02:05:38 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730959461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2730959461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.3650080016 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 754355706 ps |
| CPU time | 32.63 seconds |
| Started | Aug 25 02:05:12 PM UTC 24 |
| Finished | Aug 25 02:05:46 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650080016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3650080016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.3893976528 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 323680401 ps |
| CPU time | 5.54 seconds |
| Started | Aug 25 02:05:06 PM UTC 24 |
| Finished | Aug 25 02:05:13 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893976528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3893976528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.1777512603 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3656583711 ps |
| CPU time | 51.74 seconds |
| Started | Aug 25 02:05:12 PM UTC 24 |
| Finished | Aug 25 02:06:05 PM UTC 24 |
| Peak memory | 271916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777512603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1777512603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.1248814739 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 13874876622 ps |
| CPU time | 41.57 seconds |
| Started | Aug 25 02:05:12 PM UTC 24 |
| Finished | Aug 25 02:05:55 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248814739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1248814739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.4178257754 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1260655337 ps |
| CPU time | 8.14 seconds |
| Started | Aug 25 02:05:06 PM UTC 24 |
| Finished | Aug 25 02:05:16 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178257754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4178257754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.2203940039 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 799319786 ps |
| CPU time | 17.11 seconds |
| Started | Aug 25 02:05:06 PM UTC 24 |
| Finished | Aug 25 02:05:25 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203940039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2203940039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.4095266598 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3528299666 ps |
| CPU time | 16.29 seconds |
| Started | Aug 25 02:05:14 PM UTC 24 |
| Finished | Aug 25 02:05:32 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095266598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.4095266598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.434133783 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3903202717 ps |
| CPU time | 19.58 seconds |
| Started | Aug 25 02:05:06 PM UTC 24 |
| Finished | Aug 25 02:05:27 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434133783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.434133783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.4277120193 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 30634019739 ps |
| CPU time | 302.65 seconds |
| Started | Aug 25 02:05:17 PM UTC 24 |
| Finished | Aug 25 02:10:25 PM UTC 24 |
| Peak memory | 267824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277120193 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.4277120193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.3349875298 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 16500528454 ps |
| CPU time | 134.74 seconds |
| Started | Aug 25 02:05:17 PM UTC 24 |
| Finished | Aug 25 02:07:35 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3349875298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.3349875298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.909081013 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1315024436 ps |
| CPU time | 31.4 seconds |
| Started | Aug 25 02:05:17 PM UTC 24 |
| Finished | Aug 25 02:05:50 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909081013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.909081013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.3902668406 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 690047526 ps |
| CPU time | 3.07 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:37 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902668406 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3902668406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.1708944517 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2203368821 ps |
| CPU time | 25.78 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:06:00 PM UTC 24 |
| Peak memory | 257644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708944517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1708944517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.3171674744 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2496688402 ps |
| CPU time | 22.48 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:57 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171674744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3171674744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.1645589587 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3504091499 ps |
| CPU time | 17.51 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:52 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645589587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1645589587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.3144253035 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 252390608 ps |
| CPU time | 6.17 seconds |
| Started | Aug 25 02:05:19 PM UTC 24 |
| Finished | Aug 25 02:05:27 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144253035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.3144253035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.3057685440 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 887369944 ps |
| CPU time | 13.46 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:48 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057685440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3057685440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.4088602578 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 468875076 ps |
| CPU time | 10.62 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:45 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088602578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.4088602578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.273135724 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2197625850 ps |
| CPU time | 38.33 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:06:13 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273135724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.273135724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.914321000 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 782018540 ps |
| CPU time | 29.6 seconds |
| Started | Aug 25 02:05:19 PM UTC 24 |
| Finished | Aug 25 02:05:51 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914321000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.914321000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.3057539732 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 587971857 ps |
| CPU time | 12.42 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:47 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057539732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3057539732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.247927614 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4537049804 ps |
| CPU time | 12.1 seconds |
| Started | Aug 25 02:05:17 PM UTC 24 |
| Finished | Aug 25 02:05:31 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247927614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.247927614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.1088470021 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 14879257013 ps |
| CPU time | 276.88 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:10:15 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088470021 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.1088470021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.40117341 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 442816132 ps |
| CPU time | 15 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:50 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40117341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.40117341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.762442121 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 106839597 ps |
| CPU time | 2.77 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:05:53 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762442121 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.762442121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.4063837667 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1347771307 ps |
| CPU time | 20.1 seconds |
| Started | Aug 25 02:05:36 PM UTC 24 |
| Finished | Aug 25 02:05:58 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063837667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.4063837667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.2039078852 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 6340655187 ps |
| CPU time | 58.8 seconds |
| Started | Aug 25 02:05:35 PM UTC 24 |
| Finished | Aug 25 02:06:35 PM UTC 24 |
| Peak memory | 259508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039078852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2039078852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.3073761712 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3179695547 ps |
| CPU time | 42.02 seconds |
| Started | Aug 25 02:05:34 PM UTC 24 |
| Finished | Aug 25 02:06:17 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073761712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3073761712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.1599287037 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2146736987 ps |
| CPU time | 6.77 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:41 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599287037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1599287037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.2284735210 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2117391746 ps |
| CPU time | 18.66 seconds |
| Started | Aug 25 02:05:42 PM UTC 24 |
| Finished | Aug 25 02:06:02 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284735210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2284735210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.87321745 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 776970002 ps |
| CPU time | 27.44 seconds |
| Started | Aug 25 02:05:42 PM UTC 24 |
| Finished | Aug 25 02:06:11 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87321745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.87321745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.4086322366 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 526000938 ps |
| CPU time | 9.23 seconds |
| Started | Aug 25 02:05:34 PM UTC 24 |
| Finished | Aug 25 02:05:44 PM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086322366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.4086322366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.3094862554 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1683945681 ps |
| CPU time | 36.97 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:06:12 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094862554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3094862554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.75921311 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 119908790 ps |
| CPU time | 5.25 seconds |
| Started | Aug 25 02:05:42 PM UTC 24 |
| Finished | Aug 25 02:05:48 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75921311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.75921311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.3807033176 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 432543661 ps |
| CPU time | 12.76 seconds |
| Started | Aug 25 02:05:33 PM UTC 24 |
| Finished | Aug 25 02:05:47 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807033176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3807033176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.1856328787 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 11315628818 ps |
| CPU time | 125.7 seconds |
| Started | Aug 25 02:05:42 PM UTC 24 |
| Finished | Aug 25 02:07:51 PM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856328787 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.1856328787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.3654269287 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 9850690543 ps |
| CPU time | 70.21 seconds |
| Started | Aug 25 02:05:42 PM UTC 24 |
| Finished | Aug 25 02:06:54 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654269287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3654269287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.199154686 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 274240340 ps |
| CPU time | 4.06 seconds |
| Started | Aug 25 01:56:34 PM UTC 24 |
| Finished | Aug 25 01:56:39 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199154686 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.199154686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1151089018 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1091556606 ps |
| CPU time | 13.12 seconds |
| Started | Aug 25 01:56:03 PM UTC 24 |
| Finished | Aug 25 01:56:18 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151089018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1151089018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.2602603744 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 12926309797 ps |
| CPU time | 49.76 seconds |
| Started | Aug 25 01:56:10 PM UTC 24 |
| Finished | Aug 25 01:57:02 PM UTC 24 |
| Peak memory | 257844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602603744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2602603744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2086752139 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9761566701 ps |
| CPU time | 34.56 seconds |
| Started | Aug 25 01:56:10 PM UTC 24 |
| Finished | Aug 25 01:56:46 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086752139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2086752139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.1185866666 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 366461758 ps |
| CPU time | 16.07 seconds |
| Started | Aug 25 01:56:07 PM UTC 24 |
| Finished | Aug 25 01:56:24 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185866666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1185866666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1957239032 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 392697423 ps |
| CPU time | 6.13 seconds |
| Started | Aug 25 01:56:02 PM UTC 24 |
| Finished | Aug 25 01:56:09 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957239032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1957239032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.4182235318 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 16782211976 ps |
| CPU time | 64.43 seconds |
| Started | Aug 25 01:56:12 PM UTC 24 |
| Finished | Aug 25 01:57:18 PM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182235318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.4182235318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.3340303926 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1058811206 ps |
| CPU time | 22.23 seconds |
| Started | Aug 25 01:56:05 PM UTC 24 |
| Finished | Aug 25 01:56:28 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340303926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3340303926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2417498286 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1977135775 ps |
| CPU time | 26.11 seconds |
| Started | Aug 25 01:56:03 PM UTC 24 |
| Finished | Aug 25 01:56:31 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417498286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2417498286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.3502873790 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 201288836 ps |
| CPU time | 9.87 seconds |
| Started | Aug 25 01:56:18 PM UTC 24 |
| Finished | Aug 25 01:56:29 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502873790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3502873790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.3547447086 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 15562729818 ps |
| CPU time | 274.77 seconds |
| Started | Aug 25 01:56:32 PM UTC 24 |
| Finished | Aug 25 02:01:12 PM UTC 24 |
| Peak memory | 287868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547447086 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3547447086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.4115714311 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2236814518 ps |
| CPU time | 10.91 seconds |
| Started | Aug 25 01:55:58 PM UTC 24 |
| Finished | Aug 25 01:56:11 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115714311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.4115714311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.769734668 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 388430251 ps |
| CPU time | 14.34 seconds |
| Started | Aug 25 01:56:30 PM UTC 24 |
| Finished | Aug 25 01:56:46 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769734668 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.769734668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.2036198316 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 707111751 ps |
| CPU time | 7.06 seconds |
| Started | Aug 25 01:56:26 PM UTC 24 |
| Finished | Aug 25 01:56:34 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036198316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2036198316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.2410721056 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 45935770 ps |
| CPU time | 2.52 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:08 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410721056 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2410721056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1776726474 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8871110323 ps |
| CPU time | 17.02 seconds |
| Started | Aug 25 02:05:50 PM UTC 24 |
| Finished | Aug 25 02:06:08 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776726474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1776726474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.678271015 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 999480876 ps |
| CPU time | 17.31 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:06:08 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678271015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.678271015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.1723947705 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 639925158 ps |
| CPU time | 16.68 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:06:07 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723947705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1723947705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.1365459989 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 133784101 ps |
| CPU time | 4.58 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:05:55 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365459989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1365459989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.3906999390 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 7075124883 ps |
| CPU time | 47.97 seconds |
| Started | Aug 25 02:05:50 PM UTC 24 |
| Finished | Aug 25 02:06:39 PM UTC 24 |
| Peak memory | 269916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906999390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3906999390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.2665084622 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 6891612915 ps |
| CPU time | 25.3 seconds |
| Started | Aug 25 02:05:50 PM UTC 24 |
| Finished | Aug 25 02:06:16 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665084622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2665084622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.2991736947 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1768832054 ps |
| CPU time | 8.23 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:05:59 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991736947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2991736947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.3406173363 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1086849705 ps |
| CPU time | 17.78 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:06:08 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406173363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3406173363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.1134829868 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 265034260 ps |
| CPU time | 9.65 seconds |
| Started | Aug 25 02:06:04 PM UTC 24 |
| Finished | Aug 25 02:06:15 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134829868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1134829868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3096945833 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 237619982 ps |
| CPU time | 4.24 seconds |
| Started | Aug 25 02:05:49 PM UTC 24 |
| Finished | Aug 25 02:05:55 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096945833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3096945833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2018145233 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1854900041 ps |
| CPU time | 48.21 seconds |
| Started | Aug 25 02:06:04 PM UTC 24 |
| Finished | Aug 25 02:06:55 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018145233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2018145233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1388526058 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 83157591 ps |
| CPU time | 2.26 seconds |
| Started | Aug 25 02:06:07 PM UTC 24 |
| Finished | Aug 25 02:06:10 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388526058 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1388526058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.1978726671 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1026645336 ps |
| CPU time | 32.68 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:39 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978726671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1978726671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.3631780883 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2066203527 ps |
| CPU time | 44.01 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:51 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631780883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3631780883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.3559822068 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5302875934 ps |
| CPU time | 26.06 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:32 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559822068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3559822068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.3547577896 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 210419188 ps |
| CPU time | 6.42 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:12 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547577896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3547577896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.4149893999 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 131579137 ps |
| CPU time | 6.26 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:12 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149893999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.4149893999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.2628612014 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1921670615 ps |
| CPU time | 39 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:46 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628612014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2628612014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.4185676809 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 288824587 ps |
| CPU time | 9.36 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:15 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185676809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.4185676809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2558715601 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 365777040 ps |
| CPU time | 18.38 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:24 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558715601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2558715601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.3846689876 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 162251468 ps |
| CPU time | 7.52 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:14 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846689876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3846689876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.240372349 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 472738662 ps |
| CPU time | 11.76 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:18 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240372349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.240372349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.2281362618 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 59721466055 ps |
| CPU time | 324.29 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:11:35 PM UTC 24 |
| Peak memory | 269876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281362618 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.2281362618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.14685388 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 8550841673 ps |
| CPU time | 36.65 seconds |
| Started | Aug 25 02:06:05 PM UTC 24 |
| Finished | Aug 25 02:06:43 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14685388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.14685388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.224255273 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 876627219 ps |
| CPU time | 2.75 seconds |
| Started | Aug 25 02:06:16 PM UTC 24 |
| Finished | Aug 25 02:06:20 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224255273 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.224255273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.2343687847 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1616990717 ps |
| CPU time | 30.26 seconds |
| Started | Aug 25 02:06:12 PM UTC 24 |
| Finished | Aug 25 02:06:44 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343687847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2343687847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.286021921 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 13331120101 ps |
| CPU time | 62.34 seconds |
| Started | Aug 25 02:06:12 PM UTC 24 |
| Finished | Aug 25 02:07:16 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286021921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.286021921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.3377426452 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 586605049 ps |
| CPU time | 9.17 seconds |
| Started | Aug 25 02:06:10 PM UTC 24 |
| Finished | Aug 25 02:06:21 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377426452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3377426452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.3433750741 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 159234188 ps |
| CPU time | 6.47 seconds |
| Started | Aug 25 02:06:08 PM UTC 24 |
| Finished | Aug 25 02:06:16 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433750741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3433750741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.3041442636 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 6031014450 ps |
| CPU time | 18.25 seconds |
| Started | Aug 25 02:06:12 PM UTC 24 |
| Finished | Aug 25 02:06:32 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041442636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3041442636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.4215050044 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 10976019212 ps |
| CPU time | 42.71 seconds |
| Started | Aug 25 02:06:14 PM UTC 24 |
| Finished | Aug 25 02:06:59 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215050044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.4215050044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.1024003003 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3161232128 ps |
| CPU time | 11.48 seconds |
| Started | Aug 25 02:06:10 PM UTC 24 |
| Finished | Aug 25 02:06:23 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024003003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1024003003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.1689641317 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 11494788253 ps |
| CPU time | 36.14 seconds |
| Started | Aug 25 02:06:10 PM UTC 24 |
| Finished | Aug 25 02:06:48 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689641317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1689641317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.3185059162 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 385410151 ps |
| CPU time | 14.49 seconds |
| Started | Aug 25 02:06:15 PM UTC 24 |
| Finished | Aug 25 02:06:30 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185059162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3185059162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.2045901155 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 182683280 ps |
| CPU time | 8.67 seconds |
| Started | Aug 25 02:06:08 PM UTC 24 |
| Finished | Aug 25 02:06:18 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045901155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2045901155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.1556178731 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1844191825 ps |
| CPU time | 19.42 seconds |
| Started | Aug 25 02:06:15 PM UTC 24 |
| Finished | Aug 25 02:06:35 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556178731 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.1556178731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.4219942653 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4585073156 ps |
| CPU time | 159.55 seconds |
| Started | Aug 25 02:06:15 PM UTC 24 |
| Finished | Aug 25 02:08:57 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4219942653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.otp_ctrl_stress_all_with_rand_reset.4219942653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.3140818316 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2941443755 ps |
| CPU time | 45.39 seconds |
| Started | Aug 25 02:06:15 PM UTC 24 |
| Finished | Aug 25 02:07:02 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140818316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3140818316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.1152385141 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 699215870 ps |
| CPU time | 2.79 seconds |
| Started | Aug 25 02:06:29 PM UTC 24 |
| Finished | Aug 25 02:06:33 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152385141 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1152385141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.4239804860 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 9759533260 ps |
| CPU time | 55.94 seconds |
| Started | Aug 25 02:06:21 PM UTC 24 |
| Finished | Aug 25 02:07:18 PM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239804860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4239804860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.500703521 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1898121319 ps |
| CPU time | 45.37 seconds |
| Started | Aug 25 02:06:19 PM UTC 24 |
| Finished | Aug 25 02:07:07 PM UTC 24 |
| Peak memory | 255356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500703521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.500703521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3436302100 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1141993196 ps |
| CPU time | 29.1 seconds |
| Started | Aug 25 02:06:19 PM UTC 24 |
| Finished | Aug 25 02:06:50 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436302100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3436302100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.2978514659 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 518392877 ps |
| CPU time | 6.7 seconds |
| Started | Aug 25 02:06:17 PM UTC 24 |
| Finished | Aug 25 02:06:25 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978514659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2978514659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.4173169230 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1866177583 ps |
| CPU time | 28.2 seconds |
| Started | Aug 25 02:06:21 PM UTC 24 |
| Finished | Aug 25 02:06:50 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173169230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.4173169230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.1094417095 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1129737706 ps |
| CPU time | 9.82 seconds |
| Started | Aug 25 02:06:22 PM UTC 24 |
| Finished | Aug 25 02:06:33 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094417095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1094417095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.4115014021 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 215221996 ps |
| CPU time | 7.68 seconds |
| Started | Aug 25 02:06:19 PM UTC 24 |
| Finished | Aug 25 02:06:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115014021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.4115014021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.3896503315 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 530388060 ps |
| CPU time | 20.76 seconds |
| Started | Aug 25 02:06:17 PM UTC 24 |
| Finished | Aug 25 02:06:40 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896503315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3896503315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3469987143 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 663976708 ps |
| CPU time | 16.64 seconds |
| Started | Aug 25 02:06:23 PM UTC 24 |
| Finished | Aug 25 02:06:41 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469987143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3469987143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.1410857118 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 4476904618 ps |
| CPU time | 11.04 seconds |
| Started | Aug 25 02:06:16 PM UTC 24 |
| Finished | Aug 25 02:06:28 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410857118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1410857118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3808115962 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 36572133754 ps |
| CPU time | 316.85 seconds |
| Started | Aug 25 02:06:29 PM UTC 24 |
| Finished | Aug 25 02:11:51 PM UTC 24 |
| Peak memory | 267740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808115962 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.3808115962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.2991641173 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 207546962 ps |
| CPU time | 9.14 seconds |
| Started | Aug 25 02:06:25 PM UTC 24 |
| Finished | Aug 25 02:06:36 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991641173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2991641173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.3544450183 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 234923850 ps |
| CPU time | 3.92 seconds |
| Started | Aug 25 02:06:39 PM UTC 24 |
| Finished | Aug 25 02:06:44 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544450183 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3544450183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.1547716524 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 283519683 ps |
| CPU time | 8.03 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:06:47 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547716524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1547716524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.1029307141 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1132195281 ps |
| CPU time | 36.28 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:07:16 PM UTC 24 |
| Peak memory | 253212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029307141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1029307141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.4204686169 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1459672723 ps |
| CPU time | 36.37 seconds |
| Started | Aug 25 02:06:32 PM UTC 24 |
| Finished | Aug 25 02:07:11 PM UTC 24 |
| Peak memory | 253624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204686169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.4204686169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.4122879543 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 271749545 ps |
| CPU time | 5.73 seconds |
| Started | Aug 25 02:06:31 PM UTC 24 |
| Finished | Aug 25 02:06:39 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122879543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.4122879543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.431740088 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 768578681 ps |
| CPU time | 10.24 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:06:49 PM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431740088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.431740088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.456458866 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1636329647 ps |
| CPU time | 6.1 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:06:45 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456458866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.456458866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.3229851483 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1411906505 ps |
| CPU time | 22.98 seconds |
| Started | Aug 25 02:06:32 PM UTC 24 |
| Finished | Aug 25 02:06:57 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229851483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3229851483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.1074735648 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 1749080175 ps |
| CPU time | 21.58 seconds |
| Started | Aug 25 02:06:31 PM UTC 24 |
| Finished | Aug 25 02:06:55 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074735648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1074735648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.1444427818 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 252113150 ps |
| CPU time | 6.73 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:06:46 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444427818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1444427818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.2020689520 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 271722101 ps |
| CPU time | 6.68 seconds |
| Started | Aug 25 02:06:29 PM UTC 24 |
| Finished | Aug 25 02:06:37 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020689520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2020689520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.1423555785 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 34169244352 ps |
| CPU time | 313.35 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:11:57 PM UTC 24 |
| Peak memory | 300572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423555785 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.1423555785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1387236557 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 38686799487 ps |
| CPU time | 122.31 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:08:43 PM UTC 24 |
| Peak memory | 274008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1387236557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.otp_ctrl_stress_all_with_rand_reset.1387236557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.2973174994 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1978291402 ps |
| CPU time | 23.42 seconds |
| Started | Aug 25 02:06:38 PM UTC 24 |
| Finished | Aug 25 02:07:03 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973174994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2973174994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3444064033 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 84699763 ps |
| CPU time | 2.92 seconds |
| Started | Aug 25 02:06:49 PM UTC 24 |
| Finished | Aug 25 02:06:54 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444064033 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3444064033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.3514762490 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 474572374 ps |
| CPU time | 19.46 seconds |
| Started | Aug 25 02:06:45 PM UTC 24 |
| Finished | Aug 25 02:07:06 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514762490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3514762490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.1816965172 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 901384118 ps |
| CPU time | 18.5 seconds |
| Started | Aug 25 02:06:45 PM UTC 24 |
| Finished | Aug 25 02:07:05 PM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816965172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1816965172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.1560190728 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 12044811007 ps |
| CPU time | 41.64 seconds |
| Started | Aug 25 02:06:42 PM UTC 24 |
| Finished | Aug 25 02:07:25 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560190728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1560190728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.1627119694 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2348214331 ps |
| CPU time | 7.59 seconds |
| Started | Aug 25 02:06:42 PM UTC 24 |
| Finished | Aug 25 02:06:51 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627119694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1627119694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.1823862676 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1902447511 ps |
| CPU time | 32.43 seconds |
| Started | Aug 25 02:06:45 PM UTC 24 |
| Finished | Aug 25 02:07:19 PM UTC 24 |
| Peak memory | 257604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823862676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1823862676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.2432568543 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 939301766 ps |
| CPU time | 21.68 seconds |
| Started | Aug 25 02:06:45 PM UTC 24 |
| Finished | Aug 25 02:07:08 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432568543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2432568543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.1398778813 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 450450074 ps |
| CPU time | 6.3 seconds |
| Started | Aug 25 02:06:42 PM UTC 24 |
| Finished | Aug 25 02:06:49 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398778813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1398778813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.1071417691 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1547068554 ps |
| CPU time | 15.94 seconds |
| Started | Aug 25 02:06:42 PM UTC 24 |
| Finished | Aug 25 02:06:59 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071417691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1071417691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.2947473375 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4608476684 ps |
| CPU time | 19.18 seconds |
| Started | Aug 25 02:06:46 PM UTC 24 |
| Finished | Aug 25 02:07:07 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947473375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2947473375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.1486103087 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 473531054 ps |
| CPU time | 14.08 seconds |
| Started | Aug 25 02:06:39 PM UTC 24 |
| Finished | Aug 25 02:06:55 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486103087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.1486103087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.2588053938 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2119913573 ps |
| CPU time | 89.76 seconds |
| Started | Aug 25 02:06:48 PM UTC 24 |
| Finished | Aug 25 02:08:20 PM UTC 24 |
| Peak memory | 257756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588053938 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.2588053938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.3503123178 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 14230257538 ps |
| CPU time | 103.35 seconds |
| Started | Aug 25 02:06:48 PM UTC 24 |
| Finished | Aug 25 02:08:34 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3503123178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.otp_ctrl_stress_all_with_rand_reset.3503123178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.3442140516 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 633810293 ps |
| CPU time | 13.75 seconds |
| Started | Aug 25 02:06:48 PM UTC 24 |
| Finished | Aug 25 02:07:03 PM UTC 24 |
| Peak memory | 257452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442140516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3442140516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.3886749481 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 81689566 ps |
| CPU time | 3.28 seconds |
| Started | Aug 25 02:07:00 PM UTC 24 |
| Finished | Aug 25 02:07:05 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886749481 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3886749481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.501399504 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1082537618 ps |
| CPU time | 21.77 seconds |
| Started | Aug 25 02:06:53 PM UTC 24 |
| Finished | Aug 25 02:07:17 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501399504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.501399504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.164573567 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 472953231 ps |
| CPU time | 19.14 seconds |
| Started | Aug 25 02:06:52 PM UTC 24 |
| Finished | Aug 25 02:07:12 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164573567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.164573567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.1212149950 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 10077326190 ps |
| CPU time | 36.82 seconds |
| Started | Aug 25 02:06:52 PM UTC 24 |
| Finished | Aug 25 02:07:30 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212149950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1212149950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.614724712 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 174194588 ps |
| CPU time | 6.21 seconds |
| Started | Aug 25 02:06:51 PM UTC 24 |
| Finished | Aug 25 02:06:59 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614724712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.614724712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.2220899251 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 914965357 ps |
| CPU time | 9.65 seconds |
| Started | Aug 25 02:06:54 PM UTC 24 |
| Finished | Aug 25 02:07:05 PM UTC 24 |
| Peak memory | 257392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220899251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2220899251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1474733477 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 433850805 ps |
| CPU time | 19.42 seconds |
| Started | Aug 25 02:06:57 PM UTC 24 |
| Finished | Aug 25 02:07:18 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474733477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1474733477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.4013605166 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 700323886 ps |
| CPU time | 6.02 seconds |
| Started | Aug 25 02:06:52 PM UTC 24 |
| Finished | Aug 25 02:06:59 PM UTC 24 |
| Peak memory | 253204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013605166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.4013605166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.1724287019 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 582935469 ps |
| CPU time | 18.79 seconds |
| Started | Aug 25 02:06:51 PM UTC 24 |
| Finished | Aug 25 02:07:12 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724287019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1724287019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.1424921328 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 204373119 ps |
| CPU time | 9.53 seconds |
| Started | Aug 25 02:06:57 PM UTC 24 |
| Finished | Aug 25 02:07:08 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424921328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1424921328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1838992088 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 945029760 ps |
| CPU time | 14.8 seconds |
| Started | Aug 25 02:06:49 PM UTC 24 |
| Finished | Aug 25 02:07:06 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838992088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1838992088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.3461702756 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 12633336175 ps |
| CPU time | 249.73 seconds |
| Started | Aug 25 02:06:59 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461702756 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.3461702756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.4185784372 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 715772382 ps |
| CPU time | 22.8 seconds |
| Started | Aug 25 02:06:57 PM UTC 24 |
| Finished | Aug 25 02:07:21 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185784372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.4185784372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.1214705694 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 57616639 ps |
| CPU time | 2.71 seconds |
| Started | Aug 25 02:07:10 PM UTC 24 |
| Finished | Aug 25 02:07:14 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214705694 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1214705694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1062243616 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2659073701 ps |
| CPU time | 63.64 seconds |
| Started | Aug 25 02:07:04 PM UTC 24 |
| Finished | Aug 25 02:08:10 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062243616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1062243616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.3057713008 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1189124494 ps |
| CPU time | 22.32 seconds |
| Started | Aug 25 02:07:04 PM UTC 24 |
| Finished | Aug 25 02:07:28 PM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057713008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3057713008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.934829835 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1254893487 ps |
| CPU time | 37.95 seconds |
| Started | Aug 25 02:07:04 PM UTC 24 |
| Finished | Aug 25 02:07:44 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934829835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.934829835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.2800189352 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2889861568 ps |
| CPU time | 9.96 seconds |
| Started | Aug 25 02:07:01 PM UTC 24 |
| Finished | Aug 25 02:07:12 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800189352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2800189352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.729856145 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 386016223 ps |
| CPU time | 12.68 seconds |
| Started | Aug 25 02:07:06 PM UTC 24 |
| Finished | Aug 25 02:07:20 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729856145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.729856145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.1627606263 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1901523774 ps |
| CPU time | 30.56 seconds |
| Started | Aug 25 02:07:06 PM UTC 24 |
| Finished | Aug 25 02:07:38 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627606263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1627606263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.974031202 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 797651947 ps |
| CPU time | 15.01 seconds |
| Started | Aug 25 02:07:04 PM UTC 24 |
| Finished | Aug 25 02:07:20 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974031202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.974031202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.3979984278 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2916372911 ps |
| CPU time | 31.02 seconds |
| Started | Aug 25 02:07:01 PM UTC 24 |
| Finished | Aug 25 02:07:33 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979984278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.3979984278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.323812697 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 443976010 ps |
| CPU time | 14.77 seconds |
| Started | Aug 25 02:07:08 PM UTC 24 |
| Finished | Aug 25 02:07:24 PM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323812697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.323812697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.757161392 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 566860495 ps |
| CPU time | 6.89 seconds |
| Started | Aug 25 02:07:00 PM UTC 24 |
| Finished | Aug 25 02:07:08 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757161392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.757161392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1918958835 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 6926489076 ps |
| CPU time | 72.76 seconds |
| Started | Aug 25 02:07:08 PM UTC 24 |
| Finished | Aug 25 02:08:23 PM UTC 24 |
| Peak memory | 269848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918958835 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.1918958835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1576343109 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 46481396353 ps |
| CPU time | 197.77 seconds |
| Started | Aug 25 02:07:08 PM UTC 24 |
| Finished | Aug 25 02:10:30 PM UTC 24 |
| Peak memory | 274264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1576343109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.1576343109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.1538100262 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 423299276 ps |
| CPU time | 15.78 seconds |
| Started | Aug 25 02:07:08 PM UTC 24 |
| Finished | Aug 25 02:07:25 PM UTC 24 |
| Peak memory | 250208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538100262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1538100262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.3275961381 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 98604930 ps |
| CPU time | 2.61 seconds |
| Started | Aug 25 02:07:20 PM UTC 24 |
| Finished | Aug 25 02:07:23 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275961381 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.3275961381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.3080165434 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2100354049 ps |
| CPU time | 34.43 seconds |
| Started | Aug 25 02:07:14 PM UTC 24 |
| Finished | Aug 25 02:07:50 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080165434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3080165434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.884200315 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 654926399 ps |
| CPU time | 26.31 seconds |
| Started | Aug 25 02:07:14 PM UTC 24 |
| Finished | Aug 25 02:07:41 PM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884200315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.884200315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.3121663159 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 168054169 ps |
| CPU time | 5.75 seconds |
| Started | Aug 25 02:07:14 PM UTC 24 |
| Finished | Aug 25 02:07:20 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121663159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.3121663159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.2481413189 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 148287154 ps |
| CPU time | 5.78 seconds |
| Started | Aug 25 02:07:10 PM UTC 24 |
| Finished | Aug 25 02:07:17 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481413189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2481413189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.3533763077 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2452711313 ps |
| CPU time | 33.19 seconds |
| Started | Aug 25 02:07:15 PM UTC 24 |
| Finished | Aug 25 02:07:50 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533763077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.3533763077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.3420237286 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4974111273 ps |
| CPU time | 32.57 seconds |
| Started | Aug 25 02:07:19 PM UTC 24 |
| Finished | Aug 25 02:07:53 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420237286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3420237286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2408453366 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1170818534 ps |
| CPU time | 5.44 seconds |
| Started | Aug 25 02:07:12 PM UTC 24 |
| Finished | Aug 25 02:07:18 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408453366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2408453366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.3127931255 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1367324192 ps |
| CPU time | 28.97 seconds |
| Started | Aug 25 02:07:10 PM UTC 24 |
| Finished | Aug 25 02:07:41 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127931255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3127931255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.217856579 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 754887636 ps |
| CPU time | 10.29 seconds |
| Started | Aug 25 02:07:19 PM UTC 24 |
| Finished | Aug 25 02:07:31 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217856579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.217856579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.3318638789 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 624807093 ps |
| CPU time | 11.55 seconds |
| Started | Aug 25 02:07:10 PM UTC 24 |
| Finished | Aug 25 02:07:23 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318638789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3318638789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.82480614 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 38352771142 ps |
| CPU time | 177.97 seconds |
| Started | Aug 25 02:07:20 PM UTC 24 |
| Finished | Aug 25 02:10:21 PM UTC 24 |
| Peak memory | 261744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=82480614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.82480614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.846709597 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 7173942304 ps |
| CPU time | 15.35 seconds |
| Started | Aug 25 02:07:19 PM UTC 24 |
| Finished | Aug 25 02:07:36 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846709597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.846709597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.2616110338 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 170315370 ps |
| CPU time | 2.13 seconds |
| Started | Aug 25 02:07:33 PM UTC 24 |
| Finished | Aug 25 02:07:37 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616110338 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2616110338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.428429306 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 25059802976 ps |
| CPU time | 29.64 seconds |
| Started | Aug 25 02:07:24 PM UTC 24 |
| Finished | Aug 25 02:07:55 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428429306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.428429306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.1952466867 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 9250617849 ps |
| CPU time | 30.75 seconds |
| Started | Aug 25 02:07:22 PM UTC 24 |
| Finished | Aug 25 02:07:54 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952466867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1952466867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.1747063099 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1030631933 ps |
| CPU time | 17.76 seconds |
| Started | Aug 25 02:07:22 PM UTC 24 |
| Finished | Aug 25 02:07:41 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747063099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1747063099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.481138249 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 232240726 ps |
| CPU time | 6.69 seconds |
| Started | Aug 25 02:07:22 PM UTC 24 |
| Finished | Aug 25 02:07:30 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481138249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.481138249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.2385521287 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 546977108 ps |
| CPU time | 11.26 seconds |
| Started | Aug 25 02:07:24 PM UTC 24 |
| Finished | Aug 25 02:07:36 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385521287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2385521287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.2124986937 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 579746584 ps |
| CPU time | 19.23 seconds |
| Started | Aug 25 02:07:24 PM UTC 24 |
| Finished | Aug 25 02:07:44 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124986937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2124986937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.2879083602 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 348751631 ps |
| CPU time | 4.89 seconds |
| Started | Aug 25 02:07:22 PM UTC 24 |
| Finished | Aug 25 02:07:28 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879083602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2879083602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2339508939 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 559153596 ps |
| CPU time | 21.85 seconds |
| Started | Aug 25 02:07:22 PM UTC 24 |
| Finished | Aug 25 02:07:45 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339508939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2339508939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.2833214686 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 252977375 ps |
| CPU time | 8.27 seconds |
| Started | Aug 25 02:07:25 PM UTC 24 |
| Finished | Aug 25 02:07:35 PM UTC 24 |
| Peak memory | 251072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833214686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2833214686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.2313665296 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2794982182 ps |
| CPU time | 22.61 seconds |
| Started | Aug 25 02:07:20 PM UTC 24 |
| Finished | Aug 25 02:07:44 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313665296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2313665296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.3198952256 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 4822380929 ps |
| CPU time | 91.09 seconds |
| Started | Aug 25 02:07:33 PM UTC 24 |
| Finished | Aug 25 02:09:07 PM UTC 24 |
| Peak memory | 257568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198952256 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.3198952256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.487742695 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 4223012746 ps |
| CPU time | 192.78 seconds |
| Started | Aug 25 02:07:27 PM UTC 24 |
| Finished | Aug 25 02:10:44 PM UTC 24 |
| Peak memory | 268096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=487742695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.487742695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.644120419 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 865096455 ps |
| CPU time | 19.69 seconds |
| Started | Aug 25 02:07:25 PM UTC 24 |
| Finished | Aug 25 02:07:46 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644120419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.644120419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.4177280564 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 92729765 ps |
| CPU time | 2.94 seconds |
| Started | Aug 25 01:57:09 PM UTC 24 |
| Finished | Aug 25 01:57:13 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177280564 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.4177280564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.4140839047 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 22154960448 ps |
| CPU time | 56.3 seconds |
| Started | Aug 25 01:56:41 PM UTC 24 |
| Finished | Aug 25 01:57:39 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140839047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.4140839047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1492827450 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 976810004 ps |
| CPU time | 39.34 seconds |
| Started | Aug 25 01:56:48 PM UTC 24 |
| Finished | Aug 25 01:57:28 PM UTC 24 |
| Peak memory | 255348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492827450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1492827450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.1779422088 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 16706912109 ps |
| CPU time | 54.22 seconds |
| Started | Aug 25 01:56:48 PM UTC 24 |
| Finished | Aug 25 01:57:43 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779422088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1779422088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.629619930 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 512935788 ps |
| CPU time | 6.36 seconds |
| Started | Aug 25 01:56:41 PM UTC 24 |
| Finished | Aug 25 01:56:48 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629619930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.629619930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.1310575291 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1695062164 ps |
| CPU time | 26.77 seconds |
| Started | Aug 25 01:56:59 PM UTC 24 |
| Finished | Aug 25 01:57:27 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310575291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1310575291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.438682422 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1170839747 ps |
| CPU time | 26.36 seconds |
| Started | Aug 25 01:56:41 PM UTC 24 |
| Finished | Aug 25 01:57:08 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438682422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.438682422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.407900865 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1951329462 ps |
| CPU time | 9.41 seconds |
| Started | Aug 25 01:56:35 PM UTC 24 |
| Finished | Aug 25 01:56:45 PM UTC 24 |
| Peak memory | 257376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407900865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.407900865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.810137399 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 25533809734 ps |
| CPU time | 169.76 seconds |
| Started | Aug 25 01:57:05 PM UTC 24 |
| Finished | Aug 25 01:59:58 PM UTC 24 |
| Peak memory | 267956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=810137399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.810137399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.1406912100 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 216518707 ps |
| CPU time | 9.17 seconds |
| Started | Aug 25 01:57:02 PM UTC 24 |
| Finished | Aug 25 01:57:12 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406912100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1406912100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.171805145 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 531837394 ps |
| CPU time | 7.46 seconds |
| Started | Aug 25 02:07:33 PM UTC 24 |
| Finished | Aug 25 02:07:42 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171805145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.171805145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.1953331842 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1436597172 ps |
| CPU time | 29.81 seconds |
| Started | Aug 25 02:07:33 PM UTC 24 |
| Finished | Aug 25 02:08:05 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953331842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1953331842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1019922461 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 12076210353 ps |
| CPU time | 89.82 seconds |
| Started | Aug 25 02:07:33 PM UTC 24 |
| Finished | Aug 25 02:09:06 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1019922461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.1019922461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.650751508 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 338271274 ps |
| CPU time | 5.82 seconds |
| Started | Aug 25 02:07:33 PM UTC 24 |
| Finished | Aug 25 02:07:41 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650751508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.650751508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.2927357184 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 382471546 ps |
| CPU time | 15.13 seconds |
| Started | Aug 25 02:07:35 PM UTC 24 |
| Finished | Aug 25 02:07:51 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927357184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2927357184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.960610343 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 10676837894 ps |
| CPU time | 101.22 seconds |
| Started | Aug 25 02:07:37 PM UTC 24 |
| Finished | Aug 25 02:09:21 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=960610343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.960610343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.567121696 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 209147677 ps |
| CPU time | 3.97 seconds |
| Started | Aug 25 02:07:37 PM UTC 24 |
| Finished | Aug 25 02:07:42 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567121696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.567121696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.2550777612 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 595902840 ps |
| CPU time | 11.37 seconds |
| Started | Aug 25 02:07:37 PM UTC 24 |
| Finished | Aug 25 02:07:50 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550777612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2550777612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3473715998 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 8350166733 ps |
| CPU time | 105.11 seconds |
| Started | Aug 25 02:07:37 PM UTC 24 |
| Finished | Aug 25 02:09:25 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3473715998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 52.otp_ctrl_stress_all_with_rand_reset.3473715998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.1231296585 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 326304482 ps |
| CPU time | 5.6 seconds |
| Started | Aug 25 02:07:38 PM UTC 24 |
| Finished | Aug 25 02:07:44 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231296585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1231296585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.1129258642 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 194345862 ps |
| CPU time | 6.18 seconds |
| Started | Aug 25 02:07:38 PM UTC 24 |
| Finished | Aug 25 02:07:45 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129258642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1129258642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.1696930519 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 290733029 ps |
| CPU time | 5.78 seconds |
| Started | Aug 25 02:07:40 PM UTC 24 |
| Finished | Aug 25 02:07:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696930519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1696930519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.2306671674 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 10008020831 ps |
| CPU time | 22.96 seconds |
| Started | Aug 25 02:07:43 PM UTC 24 |
| Finished | Aug 25 02:08:08 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306671674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2306671674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.3659849780 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 300490015 ps |
| CPU time | 4.44 seconds |
| Started | Aug 25 02:07:43 PM UTC 24 |
| Finished | Aug 25 02:07:49 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659849780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3659849780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.769477042 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 263996203 ps |
| CPU time | 13.72 seconds |
| Started | Aug 25 02:07:43 PM UTC 24 |
| Finished | Aug 25 02:07:58 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769477042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.769477042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.226623309 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 327018004 ps |
| CPU time | 5.72 seconds |
| Started | Aug 25 02:07:43 PM UTC 24 |
| Finished | Aug 25 02:07:51 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226623309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.226623309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.171228081 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 232490844 ps |
| CPU time | 6.43 seconds |
| Started | Aug 25 02:07:46 PM UTC 24 |
| Finished | Aug 25 02:07:53 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171228081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.171228081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.2221610989 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 247302152 ps |
| CPU time | 4.41 seconds |
| Started | Aug 25 02:07:46 PM UTC 24 |
| Finished | Aug 25 02:07:51 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221610989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.2221610989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.1777121908 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2366104361 ps |
| CPU time | 17.91 seconds |
| Started | Aug 25 02:07:46 PM UTC 24 |
| Finished | Aug 25 02:08:05 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777121908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1777121908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3906250569 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 16182872159 ps |
| CPU time | 180.1 seconds |
| Started | Aug 25 02:07:46 PM UTC 24 |
| Finished | Aug 25 02:10:50 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3906250569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 57.otp_ctrl_stress_all_with_rand_reset.3906250569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.510026647 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 141999754 ps |
| CPU time | 5.55 seconds |
| Started | Aug 25 02:07:46 PM UTC 24 |
| Finished | Aug 25 02:07:52 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510026647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.510026647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.2127975265 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 6062824731 ps |
| CPU time | 31.54 seconds |
| Started | Aug 25 02:07:48 PM UTC 24 |
| Finished | Aug 25 02:08:21 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127975265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2127975265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.4124026555 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1700028815 ps |
| CPU time | 5.41 seconds |
| Started | Aug 25 02:07:50 PM UTC 24 |
| Finished | Aug 25 02:07:56 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124026555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.4124026555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2475700471 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 957112650 ps |
| CPU time | 4.1 seconds |
| Started | Aug 25 01:57:37 PM UTC 24 |
| Finished | Aug 25 01:57:42 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475700471 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2475700471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.3935954261 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 712481267 ps |
| CPU time | 18.77 seconds |
| Started | Aug 25 01:57:15 PM UTC 24 |
| Finished | Aug 25 01:57:35 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935954261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3935954261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.2939780032 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 194455385 ps |
| CPU time | 10.5 seconds |
| Started | Aug 25 01:57:24 PM UTC 24 |
| Finished | Aug 25 01:57:36 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939780032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2939780032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.2798148290 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 17221281597 ps |
| CPU time | 82.87 seconds |
| Started | Aug 25 01:57:24 PM UTC 24 |
| Finished | Aug 25 01:58:49 PM UTC 24 |
| Peak memory | 257396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798148290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2798148290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.1823854856 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 864783116 ps |
| CPU time | 33.02 seconds |
| Started | Aug 25 01:57:20 PM UTC 24 |
| Finished | Aug 25 01:57:55 PM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823854856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1823854856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.3315597446 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2470232694 ps |
| CPU time | 9.54 seconds |
| Started | Aug 25 01:57:14 PM UTC 24 |
| Finished | Aug 25 01:57:25 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315597446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3315597446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.2792474209 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 33845016772 ps |
| CPU time | 109.93 seconds |
| Started | Aug 25 01:57:25 PM UTC 24 |
| Finished | Aug 25 01:59:18 PM UTC 24 |
| Peak memory | 274296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792474209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2792474209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.48815430 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2509324514 ps |
| CPU time | 25.93 seconds |
| Started | Aug 25 01:57:29 PM UTC 24 |
| Finished | Aug 25 01:57:56 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48815430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.48815430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.2162415673 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 526066988 ps |
| CPU time | 19.04 seconds |
| Started | Aug 25 01:57:20 PM UTC 24 |
| Finished | Aug 25 01:57:40 PM UTC 24 |
| Peak memory | 253232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162415673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2162415673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.1553236733 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 323239914 ps |
| CPU time | 13.16 seconds |
| Started | Aug 25 01:57:15 PM UTC 24 |
| Finished | Aug 25 01:57:30 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553236733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1553236733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.9150284 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 559865162 ps |
| CPU time | 8.62 seconds |
| Started | Aug 25 01:57:14 PM UTC 24 |
| Finished | Aug 25 01:57:24 PM UTC 24 |
| Peak memory | 257372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9150284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.9150284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.4112665637 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1119772693 ps |
| CPU time | 21.41 seconds |
| Started | Aug 25 01:57:30 PM UTC 24 |
| Finished | Aug 25 01:57:53 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112665637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.4112665637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.3428678919 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 563822379 ps |
| CPU time | 6.82 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:06 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428678919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3428678919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1087504043 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 104983114 ps |
| CPU time | 5.72 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:05 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087504043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1087504043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2960562899 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 35400928924 ps |
| CPU time | 128.56 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:10:09 PM UTC 24 |
| Peak memory | 257636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2960562899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 60.otp_ctrl_stress_all_with_rand_reset.2960562899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.919774360 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 396926451 ps |
| CPU time | 4.98 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:04 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919774360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.919774360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.3434298677 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1029461555 ps |
| CPU time | 6.23 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:05 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434298677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3434298677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.369745429 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 51979478470 ps |
| CPU time | 295.12 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:12:58 PM UTC 24 |
| Peak memory | 270004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=369745429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.369745429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.1121375035 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 171501306 ps |
| CPU time | 6.81 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:06 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121375035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1121375035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.1511210741 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 207671176 ps |
| CPU time | 7.38 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:07 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511210741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1511210741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2596390394 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 7222377509 ps |
| CPU time | 118.75 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:10:00 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2596390394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 62.otp_ctrl_stress_all_with_rand_reset.2596390394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.3407573788 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 120137431 ps |
| CPU time | 6.03 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:05 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407573788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3407573788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.4229334055 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 482141306 ps |
| CPU time | 7.84 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:07 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229334055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.4229334055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.3081431928 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2205844586 ps |
| CPU time | 95.89 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:09:37 PM UTC 24 |
| Peak memory | 267884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3081431928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 63.otp_ctrl_stress_all_with_rand_reset.3081431928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.2106190823 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 550810565 ps |
| CPU time | 5.86 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:06 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106190823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2106190823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.2288745415 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 216812832 ps |
| CPU time | 4.48 seconds |
| Started | Aug 25 02:07:58 PM UTC 24 |
| Finished | Aug 25 02:08:04 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288745415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2288745415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.347081748 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 115028365 ps |
| CPU time | 5.79 seconds |
| Started | Aug 25 02:08:01 PM UTC 24 |
| Finished | Aug 25 02:08:08 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347081748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.347081748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.2627316297 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 468777838 ps |
| CPU time | 12.77 seconds |
| Started | Aug 25 02:08:05 PM UTC 24 |
| Finished | Aug 25 02:08:19 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627316297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2627316297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2923974238 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 29757066231 ps |
| CPU time | 207.32 seconds |
| Started | Aug 25 02:08:05 PM UTC 24 |
| Finished | Aug 25 02:11:37 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2923974238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.2923974238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.1784683416 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 261216077 ps |
| CPU time | 5.19 seconds |
| Started | Aug 25 02:08:05 PM UTC 24 |
| Finished | Aug 25 02:08:12 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784683416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1784683416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.378077395 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2097740371 ps |
| CPU time | 20.07 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:08:29 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378077395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.378077395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.52659036 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 23558556340 ps |
| CPU time | 169.79 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:11:01 PM UTC 24 |
| Peak memory | 272048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=52659036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.52659036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.1559189858 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 369157996 ps |
| CPU time | 6.38 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:08:15 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559189858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.1559189858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.1436395587 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 497682704 ps |
| CPU time | 12.74 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:08:22 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436395587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1436395587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.1498481584 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 4569892462 ps |
| CPU time | 199.1 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:11:31 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1498481584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 67.otp_ctrl_stress_all_with_rand_reset.1498481584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.2296889022 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 231472566 ps |
| CPU time | 4.27 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:08:13 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296889022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2296889022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.2332298628 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 876056120 ps |
| CPU time | 18.07 seconds |
| Started | Aug 25 02:08:08 PM UTC 24 |
| Finished | Aug 25 02:08:27 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332298628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.2332298628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.465393303 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 280969671 ps |
| CPU time | 6.47 seconds |
| Started | Aug 25 02:08:09 PM UTC 24 |
| Finished | Aug 25 02:08:17 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465393303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.465393303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.3318888028 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 843129546 ps |
| CPU time | 28.54 seconds |
| Started | Aug 25 02:08:09 PM UTC 24 |
| Finished | Aug 25 02:08:40 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318888028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.3318888028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.2799517390 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 98343447 ps |
| CPU time | 2.75 seconds |
| Started | Aug 25 01:57:57 PM UTC 24 |
| Finished | Aug 25 01:58:01 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799517390 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2799517390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.2145211587 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 633494307 ps |
| CPU time | 22.94 seconds |
| Started | Aug 25 01:57:40 PM UTC 24 |
| Finished | Aug 25 01:58:05 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145211587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2145211587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.720444050 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 866271807 ps |
| CPU time | 11.13 seconds |
| Started | Aug 25 01:57:44 PM UTC 24 |
| Finished | Aug 25 01:57:57 PM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720444050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.720444050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.478096566 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 368949824 ps |
| CPU time | 25.19 seconds |
| Started | Aug 25 01:57:44 PM UTC 24 |
| Finished | Aug 25 01:58:11 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478096566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.478096566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.2191444379 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2497642555 ps |
| CPU time | 11.45 seconds |
| Started | Aug 25 01:57:43 PM UTC 24 |
| Finished | Aug 25 01:57:56 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191444379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2191444379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.2515395866 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 226151588 ps |
| CPU time | 5.23 seconds |
| Started | Aug 25 01:57:37 PM UTC 24 |
| Finished | Aug 25 01:57:43 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515395866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2515395866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.61319147 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3170029169 ps |
| CPU time | 26.24 seconds |
| Started | Aug 25 01:57:49 PM UTC 24 |
| Finished | Aug 25 01:58:16 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61319147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.61319147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.2882596343 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 118097432 ps |
| CPU time | 5.24 seconds |
| Started | Aug 25 01:57:43 PM UTC 24 |
| Finished | Aug 25 01:57:49 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882596343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2882596343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.1605810891 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 706148485 ps |
| CPU time | 16.31 seconds |
| Started | Aug 25 01:57:42 PM UTC 24 |
| Finished | Aug 25 01:57:59 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605810891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1605810891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.2675816844 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 204104250 ps |
| CPU time | 4.43 seconds |
| Started | Aug 25 01:57:50 PM UTC 24 |
| Finished | Aug 25 01:57:55 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675816844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2675816844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.2264527822 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 290576840 ps |
| CPU time | 9.78 seconds |
| Started | Aug 25 01:57:37 PM UTC 24 |
| Finished | Aug 25 01:57:48 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264527822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2264527822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1896161411 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1850157419 ps |
| CPU time | 73.08 seconds |
| Started | Aug 25 01:57:56 PM UTC 24 |
| Finished | Aug 25 01:59:11 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1896161411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.1896161411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.1426773321 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1121693478 ps |
| CPU time | 21.53 seconds |
| Started | Aug 25 01:57:54 PM UTC 24 |
| Finished | Aug 25 01:58:17 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426773321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1426773321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.589933467 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 459819939 ps |
| CPU time | 6.36 seconds |
| Started | Aug 25 02:08:11 PM UTC 24 |
| Finished | Aug 25 02:08:19 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589933467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.589933467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.2000915140 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 147982076 ps |
| CPU time | 6.67 seconds |
| Started | Aug 25 02:08:12 PM UTC 24 |
| Finished | Aug 25 02:08:20 PM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000915140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2000915140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.4065217815 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1766971637 ps |
| CPU time | 11.2 seconds |
| Started | Aug 25 02:08:16 PM UTC 24 |
| Finished | Aug 25 02:08:28 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065217815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.4065217815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.3561062889 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 306863173 ps |
| CPU time | 6.41 seconds |
| Started | Aug 25 02:08:18 PM UTC 24 |
| Finished | Aug 25 02:08:25 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561062889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3561062889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2163597689 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1090024535 ps |
| CPU time | 42.91 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:09:10 PM UTC 24 |
| Peak memory | 257752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2163597689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.2163597689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.3380355040 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 288635076 ps |
| CPU time | 5.86 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:08:33 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380355040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3380355040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.1634684547 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 438412977 ps |
| CPU time | 12.45 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:08:40 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634684547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1634684547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.251071342 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 197245322 ps |
| CPU time | 5.65 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:08:33 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251071342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.251071342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.2558437349 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1288315373 ps |
| CPU time | 21.51 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:08:49 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558437349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2558437349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3679613667 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 5269468939 ps |
| CPU time | 146.16 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:10:55 PM UTC 24 |
| Peak memory | 267948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3679613667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.3679613667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1767951552 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 298856895 ps |
| CPU time | 6.03 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:08:33 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767951552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1767951552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.2072155427 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 171521449 ps |
| CPU time | 7.17 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:08:35 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072155427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2072155427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1484831191 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 3275206266 ps |
| CPU time | 138.14 seconds |
| Started | Aug 25 02:08:26 PM UTC 24 |
| Finished | Aug 25 02:10:47 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1484831191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 74.otp_ctrl_stress_all_with_rand_reset.1484831191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.3747643915 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 409610445 ps |
| CPU time | 6.37 seconds |
| Started | Aug 25 02:08:29 PM UTC 24 |
| Finished | Aug 25 02:08:37 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747643915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3747643915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.2741849594 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 428419199 ps |
| CPU time | 8.21 seconds |
| Started | Aug 25 02:08:29 PM UTC 24 |
| Finished | Aug 25 02:08:38 PM UTC 24 |
| Peak memory | 250992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741849594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2741849594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.1192942833 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1759135591 ps |
| CPU time | 8.73 seconds |
| Started | Aug 25 02:08:29 PM UTC 24 |
| Finished | Aug 25 02:08:39 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192942833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1192942833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.154349107 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4443579840 ps |
| CPU time | 22.22 seconds |
| Started | Aug 25 02:08:29 PM UTC 24 |
| Finished | Aug 25 02:08:53 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154349107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.154349107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.1625004939 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1823497325 ps |
| CPU time | 8.87 seconds |
| Started | Aug 25 02:08:34 PM UTC 24 |
| Finished | Aug 25 02:08:44 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625004939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1625004939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.1003109510 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1040244395 ps |
| CPU time | 31.57 seconds |
| Started | Aug 25 02:08:34 PM UTC 24 |
| Finished | Aug 25 02:09:07 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003109510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1003109510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.3596237369 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 127602763 ps |
| CPU time | 5.82 seconds |
| Started | Aug 25 02:08:35 PM UTC 24 |
| Finished | Aug 25 02:08:42 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596237369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3596237369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.1819917437 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 5875087924 ps |
| CPU time | 22.97 seconds |
| Started | Aug 25 02:08:36 PM UTC 24 |
| Finished | Aug 25 02:09:00 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819917437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1819917437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.3252352399 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 134494804 ps |
| CPU time | 6.81 seconds |
| Started | Aug 25 02:08:38 PM UTC 24 |
| Finished | Aug 25 02:08:46 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252352399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.3252352399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.356976513 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 175926263 ps |
| CPU time | 7.57 seconds |
| Started | Aug 25 02:08:39 PM UTC 24 |
| Finished | Aug 25 02:08:48 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356976513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.356976513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.874478278 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6796118021 ps |
| CPU time | 69.79 seconds |
| Started | Aug 25 02:08:41 PM UTC 24 |
| Finished | Aug 25 02:09:53 PM UTC 24 |
| Peak memory | 257752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=874478278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.874478278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.393314239 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 797521509 ps |
| CPU time | 2.69 seconds |
| Started | Aug 25 01:58:18 PM UTC 24 |
| Finished | Aug 25 01:58:22 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393314239 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.393314239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.1528554972 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 703236577 ps |
| CPU time | 18.57 seconds |
| Started | Aug 25 01:58:00 PM UTC 24 |
| Finished | Aug 25 01:58:20 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528554972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1528554972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.1042412307 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1317098980 ps |
| CPU time | 42.31 seconds |
| Started | Aug 25 01:58:07 PM UTC 24 |
| Finished | Aug 25 01:58:51 PM UTC 24 |
| Peak memory | 253624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042412307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1042412307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.4180943123 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 17609016824 ps |
| CPU time | 82.58 seconds |
| Started | Aug 25 01:58:06 PM UTC 24 |
| Finished | Aug 25 01:59:31 PM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180943123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.4180943123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.994418942 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 10513954245 ps |
| CPU time | 53.31 seconds |
| Started | Aug 25 01:58:06 PM UTC 24 |
| Finished | Aug 25 01:59:01 PM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994418942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.994418942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.1710401149 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 506093272 ps |
| CPU time | 6.76 seconds |
| Started | Aug 25 01:57:57 PM UTC 24 |
| Finished | Aug 25 01:58:05 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710401149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1710401149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.3451652189 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 420018173 ps |
| CPU time | 19.94 seconds |
| Started | Aug 25 01:58:13 PM UTC 24 |
| Finished | Aug 25 01:58:34 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451652189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3451652189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.3606327166 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2173331381 ps |
| CPU time | 28.01 seconds |
| Started | Aug 25 01:58:13 PM UTC 24 |
| Finished | Aug 25 01:58:42 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606327166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3606327166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.3390324590 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1216025762 ps |
| CPU time | 23.14 seconds |
| Started | Aug 25 01:58:01 PM UTC 24 |
| Finished | Aug 25 01:58:26 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390324590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.3390324590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.2994896651 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 305741185 ps |
| CPU time | 13.63 seconds |
| Started | Aug 25 01:58:14 PM UTC 24 |
| Finished | Aug 25 01:58:29 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994896651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2994896651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.1009578391 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1280468722 ps |
| CPU time | 13.7 seconds |
| Started | Aug 25 01:57:57 PM UTC 24 |
| Finished | Aug 25 01:58:12 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009578391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1009578391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.2836498859 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 244033736 ps |
| CPU time | 13.15 seconds |
| Started | Aug 25 01:58:18 PM UTC 24 |
| Finished | Aug 25 01:58:33 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836498859 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.2836498859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.1971221261 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2781816479 ps |
| CPU time | 26.97 seconds |
| Started | Aug 25 01:58:18 PM UTC 24 |
| Finished | Aug 25 01:58:47 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971221261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1971221261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.4237538710 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 390747008 ps |
| CPU time | 5.16 seconds |
| Started | Aug 25 02:08:41 PM UTC 24 |
| Finished | Aug 25 02:08:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237538710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.4237538710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.2904356746 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 288071031 ps |
| CPU time | 10.72 seconds |
| Started | Aug 25 02:08:41 PM UTC 24 |
| Finished | Aug 25 02:08:53 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904356746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2904356746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1837750106 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 20343898024 ps |
| CPU time | 127.03 seconds |
| Started | Aug 25 02:08:43 PM UTC 24 |
| Finished | Aug 25 02:10:53 PM UTC 24 |
| Peak memory | 257748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1837750106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 80.otp_ctrl_stress_all_with_rand_reset.1837750106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.441900206 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 404493433 ps |
| CPU time | 5.06 seconds |
| Started | Aug 25 02:08:43 PM UTC 24 |
| Finished | Aug 25 02:08:50 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441900206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.441900206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.4288386937 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 720420400 ps |
| CPU time | 16.93 seconds |
| Started | Aug 25 02:08:45 PM UTC 24 |
| Finished | Aug 25 02:09:03 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288386937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.4288386937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.317125664 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 147176897 ps |
| CPU time | 5.67 seconds |
| Started | Aug 25 02:08:46 PM UTC 24 |
| Finished | Aug 25 02:08:53 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317125664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.317125664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.3541681514 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 222175831 ps |
| CPU time | 12.54 seconds |
| Started | Aug 25 02:08:48 PM UTC 24 |
| Finished | Aug 25 02:09:01 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541681514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3541681514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.2218438872 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2296627826 ps |
| CPU time | 74.78 seconds |
| Started | Aug 25 02:08:48 PM UTC 24 |
| Finished | Aug 25 02:10:05 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2218438872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 82.otp_ctrl_stress_all_with_rand_reset.2218438872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.2172233093 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 97221259 ps |
| CPU time | 5.77 seconds |
| Started | Aug 25 02:08:49 PM UTC 24 |
| Finished | Aug 25 02:08:56 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172233093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2172233093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.1617119276 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 145467264 ps |
| CPU time | 7.34 seconds |
| Started | Aug 25 02:08:49 PM UTC 24 |
| Finished | Aug 25 02:08:58 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617119276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.1617119276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2843904096 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 8554690154 ps |
| CPU time | 139.21 seconds |
| Started | Aug 25 02:08:51 PM UTC 24 |
| Finished | Aug 25 02:11:13 PM UTC 24 |
| Peak memory | 267948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2843904096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 83.otp_ctrl_stress_all_with_rand_reset.2843904096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2293035082 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2158447511 ps |
| CPU time | 11.65 seconds |
| Started | Aug 25 02:08:51 PM UTC 24 |
| Finished | Aug 25 02:09:03 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293035082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2293035082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3270557829 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1999981448 ps |
| CPU time | 13.78 seconds |
| Started | Aug 25 02:08:56 PM UTC 24 |
| Finished | Aug 25 02:09:11 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270557829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3270557829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2503089437 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 3675582458 ps |
| CPU time | 169.92 seconds |
| Started | Aug 25 02:08:56 PM UTC 24 |
| Finished | Aug 25 02:11:49 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2503089437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 84.otp_ctrl_stress_all_with_rand_reset.2503089437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.157095218 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2473956060 ps |
| CPU time | 9.01 seconds |
| Started | Aug 25 02:08:56 PM UTC 24 |
| Finished | Aug 25 02:09:06 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157095218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.157095218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.1431375223 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 202879900 ps |
| CPU time | 14.14 seconds |
| Started | Aug 25 02:08:56 PM UTC 24 |
| Finished | Aug 25 02:09:11 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431375223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1431375223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4046629963 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2282486343 ps |
| CPU time | 94.84 seconds |
| Started | Aug 25 02:08:56 PM UTC 24 |
| Finished | Aug 25 02:10:34 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4046629963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 85.otp_ctrl_stress_all_with_rand_reset.4046629963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.3060658982 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 432197045 ps |
| CPU time | 6.21 seconds |
| Started | Aug 25 02:08:57 PM UTC 24 |
| Finished | Aug 25 02:09:05 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060658982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3060658982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.1912109880 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 786623946 ps |
| CPU time | 11.45 seconds |
| Started | Aug 25 02:09:00 PM UTC 24 |
| Finished | Aug 25 02:09:12 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912109880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1912109880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.4110708987 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 220046804 ps |
| CPU time | 5.78 seconds |
| Started | Aug 25 02:09:01 PM UTC 24 |
| Finished | Aug 25 02:09:08 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110708987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.4110708987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.2696335567 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2827599361 ps |
| CPU time | 19.14 seconds |
| Started | Aug 25 02:09:01 PM UTC 24 |
| Finished | Aug 25 02:09:22 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696335567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2696335567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3153449265 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 14200990053 ps |
| CPU time | 118.21 seconds |
| Started | Aug 25 02:09:02 PM UTC 24 |
| Finished | Aug 25 02:11:04 PM UTC 24 |
| Peak memory | 257616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3153449265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 87.otp_ctrl_stress_all_with_rand_reset.3153449265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.1110779439 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 456798933 ps |
| CPU time | 7.33 seconds |
| Started | Aug 25 02:09:02 PM UTC 24 |
| Finished | Aug 25 02:09:11 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110779439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1110779439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.3901362845 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 316209925 ps |
| CPU time | 9.94 seconds |
| Started | Aug 25 02:09:05 PM UTC 24 |
| Finished | Aug 25 02:09:16 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901362845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3901362845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.3378327829 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 247737162 ps |
| CPU time | 5.55 seconds |
| Started | Aug 25 02:09:06 PM UTC 24 |
| Finished | Aug 25 02:09:13 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378327829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3378327829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.1470050754 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 92745057 ps |
| CPU time | 3.79 seconds |
| Started | Aug 25 02:09:07 PM UTC 24 |
| Finished | Aug 25 02:09:13 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470050754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1470050754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.1736197956 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 123142725 ps |
| CPU time | 3.2 seconds |
| Started | Aug 25 01:58:44 PM UTC 24 |
| Finished | Aug 25 01:58:48 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736197956 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1736197956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.3879795361 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 396603242 ps |
| CPU time | 16.95 seconds |
| Started | Aug 25 01:58:23 PM UTC 24 |
| Finished | Aug 25 01:58:41 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879795361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3879795361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.600004584 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1721112385 ps |
| CPU time | 39.27 seconds |
| Started | Aug 25 01:58:30 PM UTC 24 |
| Finished | Aug 25 01:59:12 PM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600004584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.600004584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.4282222180 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 16101050222 ps |
| CPU time | 75.23 seconds |
| Started | Aug 25 01:58:30 PM UTC 24 |
| Finished | Aug 25 01:59:48 PM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282222180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.4282222180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.4027656678 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3952117374 ps |
| CPU time | 47.66 seconds |
| Started | Aug 25 01:58:34 PM UTC 24 |
| Finished | Aug 25 01:59:24 PM UTC 24 |
| Peak memory | 267760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027656678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.4027656678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1481452160 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 818769065 ps |
| CPU time | 27.7 seconds |
| Started | Aug 25 01:58:34 PM UTC 24 |
| Finished | Aug 25 01:59:04 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481452160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1481452160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.637409824 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 108884969 ps |
| CPU time | 4.54 seconds |
| Started | Aug 25 01:58:28 PM UTC 24 |
| Finished | Aug 25 01:58:34 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637409824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.637409824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.3996162839 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1964013747 ps |
| CPU time | 24.14 seconds |
| Started | Aug 25 01:58:28 PM UTC 24 |
| Finished | Aug 25 01:58:54 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996162839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3996162839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.2713601062 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 547325339 ps |
| CPU time | 8.29 seconds |
| Started | Aug 25 01:58:36 PM UTC 24 |
| Finished | Aug 25 01:58:45 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713601062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2713601062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2628882824 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 249522288 ps |
| CPU time | 6.55 seconds |
| Started | Aug 25 01:58:21 PM UTC 24 |
| Finished | Aug 25 01:58:28 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628882824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2628882824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.2538317929 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2318995192 ps |
| CPU time | 26.78 seconds |
| Started | Aug 25 01:58:36 PM UTC 24 |
| Finished | Aug 25 01:59:04 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538317929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2538317929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.121598839 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 136127583 ps |
| CPU time | 4.31 seconds |
| Started | Aug 25 02:09:11 PM UTC 24 |
| Finished | Aug 25 02:09:16 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121598839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.121598839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.752882608 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3864454935 ps |
| CPU time | 13.08 seconds |
| Started | Aug 25 02:09:11 PM UTC 24 |
| Finished | Aug 25 02:09:25 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752882608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.752882608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.864282571 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 20496866049 ps |
| CPU time | 290.44 seconds |
| Started | Aug 25 02:09:11 PM UTC 24 |
| Finished | Aug 25 02:14:06 PM UTC 24 |
| Peak memory | 274100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=864282571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.864282571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.1283976971 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 220079603 ps |
| CPU time | 5.22 seconds |
| Started | Aug 25 02:09:11 PM UTC 24 |
| Finished | Aug 25 02:09:17 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283976971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1283976971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.3981298397 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 192578578 ps |
| CPU time | 8.84 seconds |
| Started | Aug 25 02:09:11 PM UTC 24 |
| Finished | Aug 25 02:09:21 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981298397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3981298397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.3084749657 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 553699787 ps |
| CPU time | 6.94 seconds |
| Started | Aug 25 02:09:13 PM UTC 24 |
| Finished | Aug 25 02:09:22 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084749657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3084749657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.609888110 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 84423133 ps |
| CPU time | 3.88 seconds |
| Started | Aug 25 02:09:13 PM UTC 24 |
| Finished | Aug 25 02:09:18 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609888110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.609888110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.1244419008 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2025039625 ps |
| CPU time | 6.03 seconds |
| Started | Aug 25 02:09:14 PM UTC 24 |
| Finished | Aug 25 02:09:21 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244419008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1244419008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.3729524866 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 705738794 ps |
| CPU time | 21.03 seconds |
| Started | Aug 25 02:09:14 PM UTC 24 |
| Finished | Aug 25 02:09:36 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729524866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3729524866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1626726580 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 29981304841 ps |
| CPU time | 199.52 seconds |
| Started | Aug 25 02:09:14 PM UTC 24 |
| Finished | Aug 25 02:12:37 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1626726580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 93.otp_ctrl_stress_all_with_rand_reset.1626726580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.2285779700 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1926781910 ps |
| CPU time | 5.65 seconds |
| Started | Aug 25 02:09:15 PM UTC 24 |
| Finished | Aug 25 02:09:22 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285779700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2285779700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.3530143099 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 713732767 ps |
| CPU time | 24.45 seconds |
| Started | Aug 25 02:09:15 PM UTC 24 |
| Finished | Aug 25 02:09:41 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530143099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3530143099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.996475119 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 362992365 ps |
| CPU time | 5.92 seconds |
| Started | Aug 25 02:09:17 PM UTC 24 |
| Finished | Aug 25 02:09:24 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996475119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.996475119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.436624180 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 168487858 ps |
| CPU time | 10.86 seconds |
| Started | Aug 25 02:09:17 PM UTC 24 |
| Finished | Aug 25 02:09:29 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436624180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.436624180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.2292819867 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 196794364 ps |
| CPU time | 4.78 seconds |
| Started | Aug 25 02:09:20 PM UTC 24 |
| Finished | Aug 25 02:09:26 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292819867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2292819867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.4068309554 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 166622983 ps |
| CPU time | 10.2 seconds |
| Started | Aug 25 02:09:22 PM UTC 24 |
| Finished | Aug 25 02:09:34 PM UTC 24 |
| Peak memory | 253204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068309554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.4068309554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.4189535840 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 296603629 ps |
| CPU time | 5.47 seconds |
| Started | Aug 25 02:09:22 PM UTC 24 |
| Finished | Aug 25 02:09:29 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189535840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.4189535840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.3638820851 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 769678823 ps |
| CPU time | 13.8 seconds |
| Started | Aug 25 02:09:22 PM UTC 24 |
| Finished | Aug 25 02:09:38 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638820851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3638820851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.989584366 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 192449414 ps |
| CPU time | 5.53 seconds |
| Started | Aug 25 02:09:22 PM UTC 24 |
| Finished | Aug 25 02:09:30 PM UTC 24 |
| Peak memory | 253276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989584366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.989584366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.3284249554 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 543757853 ps |
| CPU time | 9.38 seconds |
| Started | Aug 25 02:09:25 PM UTC 24 |
| Finished | Aug 25 02:09:35 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284249554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3284249554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1017398414 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 56746264973 ps |
| CPU time | 132.23 seconds |
| Started | Aug 25 02:09:26 PM UTC 24 |
| Finished | Aug 25 02:11:41 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1017398414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.1017398414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.2467025096 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 114377117 ps |
| CPU time | 4.49 seconds |
| Started | Aug 25 02:09:26 PM UTC 24 |
| Finished | Aug 25 02:09:32 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467025096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2467025096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.3199540841 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 964248675 ps |
| CPU time | 12.95 seconds |
| Started | Aug 25 02:09:26 PM UTC 24 |
| Finished | Aug 25 02:09:40 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199540841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3199540841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |