Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5239220

1

T1

16

T2

631

T3

1204

full_word

2475997

1

T1

3

T2

198

T3

575

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7714897	1			T1	19		T2	829		T3	1779
auto[TlIntgErrCmd]	102	1			T305	3		T306	3		T307	3
auto[TlIntgErrData]	121	1			T305	5		T306	3		T307	4
auto[TlIntgErrBoth]	97	1			T305	2		T306	4		T307	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5711192

1

T1

4

T2

582

T3

1612

auto[1]

2004025

1

T1

15

T2

247

T3

167

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3807832	1			T1	3		T2	484		T3	1103
auto[TlIntgErrNone]	partial	auto[1]	1431099	1			T1	13		T2	147		T3	101
auto[TlIntgErrNone]	full_word	auto[0]	1903227	1			T1	1		T2	98		T3	509
auto[TlIntgErrNone]	full_word	auto[1]	572739	1			T1	2		T2	100		T3	66
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T316	2		T410	2		T415	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T305	2		T306	3		T307	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T307	1		T316	1		T413	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T305	1		T410	1		T415	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T305	2		T306	1		T307	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T305	3		T306	2		T307	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T409	1		T413	1		T415	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T307	1		T409	1		T415	2
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T305	1		T306	2		T307	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T305	1		T306	2		T307	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T410	1		T418	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T411	1		T418	1		-	-