Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.85		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	88827426	429465	0	0
check_regwen_rd_A	88827426	1814	0	0
check_timeout_rd_A	88827426	1394	0	0
check_trigger_regwen_rd_A	88827426	1774	0	0
consistency_check_period_rd_A	88827426	1779	0	0
creator_sw_cfg_read_lock_rd_A	88827426	1295	0	0
direct_access_address_rd_A	88827426	580	0	0
direct_access_wdata_0_rd_A	88827426	95	0	0
direct_access_wdata_1_rd_A	88827426	94	0	0
integrity_check_period_rd_A	88827426	1688	0	0
intr_enable_rd_A	88827426	2587	0	0
owner_sw_cfg_read_lock_rd_A	88827426	1379	0	0
rot_creator_auth_codesign_read_lock_rd_A	88827426	1316	0	0
rot_creator_auth_state_read_lock_rd_A	88827426	1333	0	0
vendor_test_read_lock_rd_A	88827426	1373	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	429465	0	0
T14	148027	2909	0	0
T15	0	3366	0	0
T16	0	550	0	0
T21	0	6785	0	0
T25	0	2702	0	0
T26	0	7061	0	0
T58	162444	0	0	0
T170	0	1862	0	0
T198	55321	0	0	0
T265	19624	0	0	0
T277	0	5056	0	0
T321	0	3404	0	0
T322	0	7599	0	0
T323	4275	0	0	0
T324	11800	0	0	0
T325	46855	0	0	0
T326	12736	0	0	0
T327	135219	0	0	0
T328	41110	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1814	0	0
T15	190590	48	0	0
T16	0	11	0	0
T25	0	24	0	0
T65	16703	0	0	0
T92	0	56	0	0
T192	134331	0	0	0
T210	0	39	0	0
T321	0	25	0	0
T364	0	33	0	0
T365	0	34	0	0
T366	0	15	0	0
T367	0	5	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1394	0	0
T15	190590	50	0	0
T16	0	10	0	0
T25	0	13	0	0
T65	16703	0	0	0
T92	0	42	0	0
T192	134331	0	0	0
T210	0	66	0	0
T321	0	24	0	0
T364	0	28	0	0
T365	0	26	0	0
T366	0	12	0	0
T367	0	14	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1774	0	0
T15	190590	35	0	0
T16	0	6	0	0
T25	0	20	0	0
T65	16703	0	0	0
T92	0	42	0	0
T192	134331	0	0	0
T210	0	28	0	0
T321	0	19	0	0
T364	0	17	0	0
T365	0	16	0	0
T366	0	11	0	0
T367	0	4	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1779	0	0
T15	190590	35	0	0
T16	0	7	0	0
T25	0	22	0	0
T65	16703	0	0	0
T92	0	74	0	0
T192	134331	0	0	0
T210	0	33	0	0
T321	0	13	0	0
T364	0	33	0	0
T365	0	19	0	0
T366	0	8	0	0
T367	0	23	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1295	0	0
T15	190590	41	0	0
T25	0	23	0	0
T65	16703	0	0	0
T92	0	51	0	0
T192	134331	0	0	0
T210	0	46	0	0
T321	0	35	0	0
T364	0	31	0	0
T365	0	24	0	0
T366	0	5	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0
T375	0	17	0	0
T376	0	26	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	580	0	0
T15	190590	28	0	0
T16	0	15	0	0
T25	0	27	0	0
T65	16703	0	0	0
T92	0	39	0	0
T192	134331	0	0	0
T210	0	48	0	0
T321	0	30	0	0
T364	0	31	0	0
T365	0	30	0	0
T367	0	4	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0
T375	0	14	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	95	0	0
T23	0	8	0	0
T92	567663	16	0	0
T98	498836	0	0	0
T292	48266	0	0	0
T364	0	12	0	0
T365	0	5	0	0
T366	0	10	0	0
T376	0	7	0	0
T377	0	4	0	0
T378	0	2	0	0
T379	0	2	0	0
T380	0	4	0	0
T381	157780	0	0	0
T382	231842	0	0	0
T383	27131	0	0	0
T384	31135	0	0	0
T385	79239	0	0	0
T386	10889	0	0	0
T387	99990	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	94	0	0
T15	190590	1	0	0
T23	0	8	0	0
T65	16703	0	0	0
T92	0	13	0	0
T153	0	14	0	0
T192	134331	0	0	0
T210	0	7	0	0
T364	0	13	0	0
T367	0	4	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0
T379	0	6	0	0
T380	0	15	0	0
T388	0	13	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1688	0	0
T15	190590	36	0	0
T16	0	7	0	0
T25	0	16	0	0
T65	16703	0	0	0
T92	0	44	0	0
T192	134331	0	0	0
T210	0	29	0	0
T321	0	5	0	0
T364	0	20	0	0
T365	0	37	0	0
T366	0	7	0	0
T367	0	10	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	2587	0	0
T9	323458	39	0	0
T15	0	68	0	0
T16	0	6	0	0
T20	38967	0	0	0
T25	0	34	0	0
T92	0	83	0	0
T119	41536	0	0	0
T175	44943	0	0	0
T184	11368	0	0	0
T260	0	37	0	0
T315	4812	0	0	0
T321	0	22	0	0
T389	0	33	0	0
T390	0	23	0	0
T391	0	10	0	0
T392	32282	0	0	0
T393	24569	0	0	0
T394	12173	0	0	0
T395	19040	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1379	0	0
T15	190590	56	0	0
T16	0	10	0	0
T25	0	30	0	0
T65	16703	0	0	0
T92	0	60	0	0
T192	134331	0	0	0
T210	0	38	0	0
T321	0	12	0	0
T364	0	25	0	0
T365	0	17	0	0
T366	0	9	0	0
T367	0	15	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1316	0	0
T15	190590	60	0	0
T25	0	21	0	0
T65	16703	0	0	0
T92	0	46	0	0
T192	134331	0	0	0
T210	0	24	0	0
T321	0	10	0	0
T364	0	12	0	0
T365	0	15	0	0
T366	0	4	0	0
T367	0	26	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0
T375	0	28	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1333	0	0
T15	190590	17	0	0
T16	0	8	0	0
T25	0	23	0	0
T65	16703	0	0	0
T92	0	43	0	0
T192	134331	0	0	0
T210	0	43	0	0
T321	0	22	0	0
T364	0	34	0	0
T365	0	27	0	0
T366	0	2	0	0
T367	0	17	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88827426	1373	0	0
T15	190590	35	0	0
T16	0	3	0	0
T25	0	33	0	0
T65	16703	0	0	0
T92	0	45	0	0
T192	134331	0	0	0
T210	0	34	0	0
T321	0	35	0	0
T364	0	16	0	0
T365	0	23	0	0
T366	0	10	0	0
T367	0	11	0	0
T368	353819	0	0	0
T369	38679	0	0	0
T370	5203	0	0	0
T371	122529	0	0	0
T372	67427	0	0	0
T373	15570	0	0	0
T374	6164	0	0	0