Unified Coverage Report :: Module :: otp_ctrl_ecc_reg

Module : otp_ctrl_ecc_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.23	100.00	100.00		90.00	100.00	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.75	100.00	97.06		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.82	97.64	95.24		92.00	96.36	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.76	98.00	93.75		97.22	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.20	98.00	93.75		94.44	95.38	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.92	100.00		75.67		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.90	96.91	100.00		95.24	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	76.47			76.47
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	77.94			77.94
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	77.94			77.94
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	69.12			69.12
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	68.38			68.38
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	89.71			89.71
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	75.00			75.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	68.38			68.38
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	69.12			69.12
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	66.18			66.18
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	69.85			69.85
u_prim_secded_inv_72_64_enc	100.00			100.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=9,Aw=4,EccWidth=8 + Width=64,Depth=2,Aw=1,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                        MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

45                          always_comb begin : p_write
46         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
47         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
48         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
49                      
50         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
51         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
52         1/1                  rdata_o = data_q[0];
           Tests:       T1 T2 T3 
53         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
54         1/1                    {ecc_d[0], data_d[0]} = ecc_enc;
           Tests:       T1 T2 T3 
55                              end
                        MISSING_ELSE
56                            end
                   ==>  MISSING_ELSE
57                          end
58                        end else begin : gen_multiple_words
59                          always_comb begin : p_write
60                            data_o = data_q;
61                            data_d = data_q;
62                            ecc_d  = ecc_q;
63                      
64                            rdata_o = '0;
65                            if (32'(addr_i) < Depth) begin
66                              rdata_o = data_q[addr_i];
67                              if (wren_i) begin
68                                {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
69                              end
70                            end
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T29

---

Assert Coverage for Module : otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	942461630	933447570	0	0
DataOutKnown_A	942461630	933447570	0	0
EccErrKnown_A	942461630	933447570	0	0
EccKnown_A	942461630	933447570	0	0
RDataOutKnown_A	942461630	933447570	0	0
WidthMustBe64bit_A	12463	12463	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942461630	933447570	0	0
T1	52547	51744	0	0
T2	193666	191048	0	0
T3	458854	454454	0	0
T4	180851	178145	0	0
T5	485111	484418	0	0
T6	843414	827926	0	0
T7	303765	297968	0	0
T11	657855	656788	0	0
T12	1340559	1329592	0	0
T13	50127	49390	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942461630	933447570	0	0
T1	52547	51744	0	0
T2	193666	191048	0	0
T3	458854	454454	0	0
T4	180851	178145	0	0
T5	485111	484418	0	0
T6	843414	827926	0	0
T7	303765	297968	0	0
T11	657855	656788	0	0
T12	1340559	1329592	0	0
T13	50127	49390	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942461630	933447570	0	0
T1	52547	51744	0	0
T2	193666	191048	0	0
T3	458854	454454	0	0
T4	180851	178145	0	0
T5	485111	484418	0	0
T6	843414	827926	0	0
T7	303765	297968	0	0
T11	657855	656788	0	0
T12	1340559	1329592	0	0
T13	50127	49390	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942461630	933447570	0	0
T1	52547	51744	0	0
T2	193666	191048	0	0
T3	458854	454454	0	0
T4	180851	178145	0	0
T5	485111	484418	0	0
T6	843414	827926	0	0
T7	303765	297968	0	0
T11	657855	656788	0	0
T12	1340559	1329592	0	0
T13	50127	49390	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942461630	933447570	0	0
T1	52547	51744	0	0
T2	193666	191048	0	0
T3	458854	454454	0	0
T4	180851	178145	0	0
T5	485111	484418	0	0
T6	843414	827926	0	0
T7	303765	297968	0	0
T11	657855	656788	0	0
T12	1340559	1329592	0	0
T13	50127	49390	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12463	12463	0	0
T1	11	11	0	0
T2	11	11	0	0
T3	11	11	0	0
T4	11	11	0	0
T5	11	11	0	0
T6	11	11	0	0
T7	11	11	0	0
T11	11	11	0	0
T12	11	11	0	0
T13	11	11	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

45                          always_comb begin : p_write
46         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
47         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
48         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
49                      
50         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
51         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
52         1/1                  rdata_o = data_q[0];
           Tests:       T1 T2 T3 
53         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
54         1/1                    {ecc_d[0], data_d[0]} = ecc_enc;
           Tests:       T1 T2 T3 
55                              end
                        MISSING_ELSE
56                            end
                   ==>  MISSING_ELSE
57                          end
58                        end else begin : gen_multiple_words
59                          always_comb begin : p_write
60                            data_o = data_q;
61                            data_d = data_q;
62                            ecc_d  = ecc_q;
63                      
64                            rdata_o = '0;
65                            if (32'(addr_i) < Depth) begin
66                              rdata_o = data_q[addr_i];
67                              if (wren_i) begin
68                                {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
69                              end
70                            end
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

45                          always_comb begin : p_write
46         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
47         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
48         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
49                      
50         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
51         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
52         1/1                  rdata_o = data_q[0];
           Tests:       T1 T2 T3 
53         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
54         1/1                    {ecc_d[0], data_d[0]} = ecc_enc;
           Tests:       T1 T2 T3 
55                              end
                        MISSING_ELSE
56                            end
                   ==>  MISSING_ELSE
57                          end
58                        end else begin : gen_multiple_words
59                          always_comb begin : p_write
60                            data_o = data_q;
61                            data_d = data_q;
62                            ecc_d  = ecc_q;
63                      
64                            rdata_o = '0;
65                            if (32'(addr_i) < Depth) begin
66                              rdata_o = data_q[addr_i];
67                              if (wren_i) begin
68                                {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
69                              end
70                            end
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

45                          always_comb begin : p_write
46         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
47         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
48         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
49                      
50         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
51         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
52         1/1                  rdata_o = data_q[0];
           Tests:       T1 T2 T3 
53         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
54         1/1                    {ecc_d[0], data_d[0]} = ecc_enc;
           Tests:       T1 T2 T3 
55                              end
                        MISSING_ELSE
56                            end
                   ==>  MISSING_ELSE
57                          end
58                        end else begin : gen_multiple_words
59                          always_comb begin : p_write
60                            data_o = data_q;
61                            data_d = data_q;
62                            ecc_d  = ecc_q;
63                      
64                            rdata_o = '0;
65                            if (32'(addr_i) < Depth) begin
66                              rdata_o = data_q[addr_i];
67                              if (wren_i) begin
68                                {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
69                              end
70                            end
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

45                          always_comb begin : p_write
46         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
47         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
48         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
49                      
50         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
51         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
52         1/1                  rdata_o = data_q[0];
           Tests:       T1 T2 T3 
53         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
54         1/1                    {ecc_d[0], data_d[0]} = ecc_enc;
           Tests:       T1 T2 T3 
55                              end
                        MISSING_ELSE
56                            end
                   ==>  MISSING_ELSE
57                          end
58                        end else begin : gen_multiple_words
59                          always_comb begin : p_write
60                            data_o = data_q;
61                            data_d = data_q;
62                            ecc_d  = ecc_q;
63                      
64                            rdata_o = '0;
65                            if (32'(addr_i) < Depth) begin
66                              rdata_o = data_q[addr_i];
67                              if (wren_i) begin
68                                {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
69                              end
70                            end
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

45                          always_comb begin : p_write
46         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
47         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
48         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
49                      
50         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
51         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
52         1/1                  rdata_o = data_q[0];
           Tests:       T1 T2 T3 
53         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
54         1/1                    {ecc_d[0], data_d[0]} = ecc_enc;
           Tests:       T1 T2 T3 
55                              end
                        MISSING_ELSE
56                            end
                   ==>  MISSING_ELSE
57                          end
58                        end else begin : gen_multiple_words
59                          always_comb begin : p_write
60                            data_o = data_q;
61                            data_d = data_q;
62                            ecc_d  = ecc_q;
63                      
64                            rdata_o = '0;
65                            if (32'(addr_i) < Depth) begin
66                              rdata_o = data_q[addr_i];
67                              if (wren_i) begin
68                                {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
69                              end
70                            end
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                        MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T29

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                   ==>  MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	90	2	2	100.00
IF	65	2	2	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Excluded		VC_COV_UNR

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                        MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T29

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                        MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T29

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                        MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T29

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

59                          always_comb begin : p_write
60         1/1                data_o = data_q;
           Tests:       T1 T2 T3 
61         1/1                data_d = data_q;
           Tests:       T1 T2 T3 
62         1/1                ecc_d  = ecc_q;
           Tests:       T1 T2 T3 
63                      
64         1/1                rdata_o = '0;
           Tests:       T1 T2 T3 
65         1/1                if (32'(addr_i) < Depth) begin
           Tests:       T1 T2 T3 
66         1/1                  rdata_o = data_q[addr_i];
           Tests:       T1 T2 T3 
67         1/1                  if (wren_i) begin
           Tests:       T1 T2 T3 
68         1/1                    {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
                        MISSING_ELSE
71                          end
72                        end
73                      
74                        // Concurrent ECC checks.
75                        logic [Depth-1:0][1:0] err;
76                        for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec
77                          prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec (
78                            .data_i({ecc_q[k], data_q[k]}),
79                            // We only rely on the error detection mechanism,
80                            // and not on error correction.
81                            .data_o(),
82                            .syndrome_o(),
83                            .err_o(err[k])
84                          );
85                        end
86                      
87         1/1            assign ecc_err_o = |err;
           Tests:       T1 T2 T3 
88                      
89                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
90         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
91         1/1                ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
           Tests:       T1 T2 T3 
92         1/1                data_q <= '0;
           Tests:       T1 T2 T3 
93                          end else begin
94         1/1                ecc_q  <= ecc_d;
           Tests:       T1 T2 T3 
95         1/1                data_q <= data_d;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

90             if (!rst_ni) begin
               -1-  
91               ecc_q  <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}};
                 ==>
92               data_q <= '0;
93             end else begin
94               ecc_q  <= ecc_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

65               if (32'(addr_i) < Depth) begin
                 -1-  
66                 rdata_o = data_q[addr_i];
67                 if (wren_i) begin
                   -2-  
68                   {ecc_d[addr_i], data_d[addr_i]} = ecc_enc;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T29

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85678330	84858870	0	0
DataOutKnown_A	85678330	84858870	0	0
EccErrKnown_A	85678330	84858870	0	0
EccKnown_A	85678330	84858870	0	0
RDataOutKnown_A	85678330	84858870	0	0
WidthMustBe64bit_A	1133	1133	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85678330	84858870	0	0
T1	4777	4704	0	0
T2	17606	17368	0	0
T3	41714	41314	0	0
T4	16441	16195	0	0
T5	44101	44038	0	0
T6	76674	75266	0	0
T7	27615	27088	0	0
T11	59805	59708	0	0
T12	121869	120872	0	0
T13	4557	4490	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1133	1133	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0