Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_count
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.20 99.20

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ 93.60 93.60
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty 93.60 93.60
tb.dut.u_otp_ctrl_scrmbl.u_prim_count 100.00 100.00
tb.dut.u_otp_ctrl_dai.u_prim_count 100.00 100.00
tb.dut.u_otp_ctrl_lci.u_prim_count 100.00 100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_seed 100.00 100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count 100.00 100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count 100.00 100.00


Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.60 93.60


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.60 93.60


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.16 100.00 89.61 100.00 91.18 100.00 u_otp_ctrl_lfsr_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.60 93.60


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.60 93.60


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.16 100.00 89.61 100.00 91.18 100.00 u_otp_ctrl_lfsr_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 91.67 100.00 100.00 100.00 100.00 u_otp_ctrl_scrmbl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.38 95.88 95.06 85.96 90.00 100.00 u_otp_ctrl_dai


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_otp_ctrl_lci


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.27 99.32 100.00 90.91 91.11 100.00 u_otp_ctrl_kdi


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.27 99.32 100.00 90.91 91.11 100.00 u_otp_ctrl_kdi


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.82 97.64 95.24 92.00 96.36 82.86 gen_partitions[5].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.75 95.45 92.86 91.67 90.91 82.86 gen_partitions[6].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.76 98.00 93.75 97.22 95.38 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.20 98.00 93.75 94.44 95.38 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.90 96.91 100.00 95.24 100.00 82.35 gen_partitions[10].gen_lifecycle.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=8,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_otp_ctrl_dai.u_prim_count

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 42 42 100.00
Total Bits 0->1 21 21 100.00
Total Bits 1->0 21 21 100.00

Ports 7 7 100.00
Port Bits 42 42 100.00
Port Bits 0->1 21 21 100.00
Port Bits 1->0 21 21 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[7:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[7:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

SCORETOGGLE
100.00 100.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 22 22 100.00
Total Bits 0->1 11 11 100.00
Total Bits 1->0 11 11 100.00

Ports 7 7 100.00
Port Bits 22 22 100.00
Port Bits 0->1 11 11 100.00
Port Bits 1->0 11 11 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Module : prim_count ( parameter Width=40,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
93.60 93.60
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

SCORETOGGLE
93.60 93.60
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

TotalCoveredPercent
Totals 8 7 87.50
Total Bits 250 234 93.60
Total Bits 0->1 125 117 93.60
Total Bits 1->0 125 117 93.60

Ports 8 7 87.50
Port Bits 250 234 93.60
Port Bits 0->1 125 117 93.60
Port Bits 1->0 125 117 93.60

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T4,T6 Yes T3,T4,T6 INPUT
set_cnt_i[31:0] Yes Yes *T4,T6,*T7 Yes T4,T6,T7 INPUT
set_cnt_i[39:32] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T3,T4,T6 Yes T3,T4,T6 INPUT
step_i[39:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[39:0] Yes Yes T3,T4,T6 Yes T3,T4,T6 OUTPUT
cnt_after_commit_o[39:0] Yes Yes T3,T4,T6 Yes T3,T4,T6 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Module : prim_count ( parameter Width=4,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Module : prim_count ( parameter Width=6,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_otp_ctrl_lci.u_prim_count

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 7 7 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[5:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[5:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[5:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
cnt_after_commit_o[5:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_count

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 7 7 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[4:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Module : prim_count ( parameter Width=1,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 250 234 93.60
Total Bits 0->1 125 117 93.60
Total Bits 1->0 125 117 93.60

Ports 8 7 87.50
Port Bits 250 234 93.60
Port Bits 0->1 125 117 93.60
Port Bits 1->0 125 117 93.60

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T3,T4,T6 Yes T3,T4,T6 INPUT
set_cnt_i[31:0] Yes Yes *T4,T6,*T7 Yes T4,T6,T7 INPUT
set_cnt_i[39:32] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T3,T4,T6 Yes T3,T4,T6 INPUT
step_i[39:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[39:0] Yes Yes T3,T4,T6 Yes T3,T4,T6 OUTPUT
cnt_after_commit_o[39:0] Yes Yes T3,T4,T6 Yes T3,T4,T6 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 250 234 93.60
Total Bits 0->1 125 117 93.60
Total Bits 1->0 125 117 93.60

Ports 8 7 87.50
Port Bits 250 234 93.60
Port Bits 0->1 125 117 93.60
Port Bits 1->0 125 117 93.60

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T4,T6,T7 Yes T4,T6,T7 INPUT
set_cnt_i[31:0] Yes Yes *T4,T6,*T7 Yes T4,T6,T7 INPUT
set_cnt_i[39:32] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T4,T6,T7 Yes T4,T6,T7 INPUT
step_i[39:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[39:0] Yes Yes T4,T6,T7 Yes T4,T6,T7 OUTPUT
cnt_after_commit_o[39:0] Yes Yes T4,T6,T7 Yes T4,T6,T7 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 7 7 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[4:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 42 42 100.00
Total Bits 0->1 21 21 100.00
Total Bits 1->0 21 21 100.00

Ports 7 7 100.00
Port Bits 42 42 100.00
Port Bits 0->1 21 21 100.00
Port Bits 1->0 21 21 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[7:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[7:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 7 7 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[5:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[5:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[5:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
cnt_after_commit_o[5:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T3,T6,T7 Yes T3,T6,T7 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 22 22 100.00
Total Bits 0->1 11 11 100.00
Total Bits 1->0 11 11 100.00

Ports 7 7 100.00
Port Bits 22 22 100.00
Port Bits 0->1 11 11 100.00
Port Bits 1->0 11 11 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 26 26 100.00
Total Bits 0->1 13 13 100.00
Total Bits 1->0 13 13 100.00

Ports 7 7 100.00
Port Bits 26 26 100.00
Port Bits 0->1 13 13 100.00
Port Bits 1->0 13 13 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clr_i Yes Yes T4,T6,T7 Yes T4,T6,T7 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[3:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT

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