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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.95 93.81 96.18 95.63 92.36 97.10 96.34 93.21


Total test records in report: 1308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1259 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.408508403 Aug 27 03:12:08 PM UTC 24 Aug 27 03:12:16 PM UTC 24 303774183 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.322614771 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:16 PM UTC 24 552159202 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4010871992 Aug 27 03:12:08 PM UTC 24 Aug 27 03:12:16 PM UTC 24 195067097 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.710341378 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:16 PM UTC 24 90888904 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1145029227 Aug 27 03:12:02 PM UTC 24 Aug 27 03:12:16 PM UTC 24 6777983503 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3701957299 Aug 27 03:11:55 PM UTC 24 Aug 27 03:12:16 PM UTC 24 4876574955 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.658533531 Aug 27 03:12:05 PM UTC 24 Aug 27 03:12:16 PM UTC 24 1245695858 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1392680848 Aug 27 03:12:05 PM UTC 24 Aug 27 03:12:16 PM UTC 24 2584199094 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3285719935 Aug 27 03:12:09 PM UTC 24 Aug 27 03:12:16 PM UTC 24 325481735 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.4007426196 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:16 PM UTC 24 1009473358 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.3670709437 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:16 PM UTC 24 51105645 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1976350051 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 38981399 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.998607177 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:17 PM UTC 24 1060834462 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3620632541 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 75705588 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1006665294 Aug 27 03:12:06 PM UTC 24 Aug 27 03:12:17 PM UTC 24 688833591 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.928247729 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 51735853 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.4284988325 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 528209470 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1869253483 Aug 27 03:12:10 PM UTC 24 Aug 27 03:12:17 PM UTC 24 195797473 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3726377566 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 513767032 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1920191836 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 169824418 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2932451465 Aug 27 03:12:09 PM UTC 24 Aug 27 03:12:17 PM UTC 24 2924609211 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.527187199 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:17 PM UTC 24 263323485 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1502507236 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:18 PM UTC 24 1237939169 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.334338923 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:18 PM UTC 24 1901563975 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2260657293 Aug 27 03:12:11 PM UTC 24 Aug 27 03:12:18 PM UTC 24 651589944 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1050277792 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:18 PM UTC 24 38066078 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2167897404 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:18 PM UTC 24 140667916 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2126226074 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 529867212 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2746543276 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:19 PM UTC 24 144151449 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3464753072 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 72719140 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1756896323 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 74394657 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.2606415366 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 566099216 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2494556336 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 56396904 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3607412163 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 97118319 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.447804503 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 76233172 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2618346458 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 136020502 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3639269410 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 143121859 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1557786336 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 73937932 ps
T1294 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.1262204074 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 137500541 ps
T1295 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2202184883 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:19 PM UTC 24 573297655 ps
T1296 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1716490702 Aug 27 03:12:16 PM UTC 24 Aug 27 03:12:22 PM UTC 24 70923910 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.636110717 Aug 27 03:12:05 PM UTC 24 Aug 27 03:12:22 PM UTC 24 1974615105 ps
T1297 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3421871874 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:23 PM UTC 24 134146209 ps
T1298 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.1951308305 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:23 PM UTC 24 54902746 ps
T1299 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2964932510 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:23 PM UTC 24 150740956 ps
T1300 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2859750270 Aug 27 03:12:14 PM UTC 24 Aug 27 03:12:24 PM UTC 24 1160208556 ps
T1301 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.54800144 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:26 PM UTC 24 43031604 ps
T1302 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.17986280 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:26 PM UTC 24 39046300 ps
T1303 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.797105528 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:26 PM UTC 24 74473346 ps
T1304 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3828813029 Aug 27 03:12:21 PM UTC 24 Aug 27 03:12:26 PM UTC 24 38181768 ps
T1305 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3125439645 Aug 27 03:12:08 PM UTC 24 Aug 27 03:12:27 PM UTC 24 1311276463 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.694884344 Aug 27 03:12:09 PM UTC 24 Aug 27 03:12:27 PM UTC 24 4104961973 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1537382487 Aug 27 03:12:10 PM UTC 24 Aug 27 03:12:28 PM UTC 24 2416507318 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.881155705 Aug 27 03:12:07 PM UTC 24 Aug 27 03:12:29 PM UTC 24 1642940438 ps
T1306 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4089659995 Aug 27 03:12:01 PM UTC 24 Aug 27 03:12:29 PM UTC 24 20107144870 ps
T1307 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2544319343 Aug 27 03:12:12 PM UTC 24 Aug 27 03:12:31 PM UTC 24 1275839106 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1124941785 Aug 27 03:12:11 PM UTC 24 Aug 27 03:12:31 PM UTC 24 2220431288 ps
T1308 /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1338110483 Aug 27 03:12:20 PM UTC 24 Aug 27 03:12:36 PM UTC 24 47272759 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.2270050730
Short name T12
Test name
Test status
Simulation time 2437420003 ps
CPU time 22.23 seconds
Started Aug 27 03:02:56 PM UTC 24
Finished Aug 27 03:03:19 PM UTC 24
Peak memory 253684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270050730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2270050730
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.4071267078
Short name T19
Test name
Test status
Simulation time 1265589049 ps
CPU time 12.15 seconds
Started Aug 27 03:03:29 PM UTC 24
Finished Aug 27 03:03:42 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071267078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.4071267078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.3798114811
Short name T26
Test name
Test status
Simulation time 10464438733 ps
CPU time 150.13 seconds
Started Aug 27 03:03:47 PM UTC 24
Finished Aug 27 03:06:20 PM UTC 24
Peak memory 266888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3798114811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.otp_ctrl_stress_all_with_rand_reset.3798114811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.1031948736
Short name T117
Test name
Test status
Simulation time 1726202952 ps
CPU time 31.19 seconds
Started Aug 27 03:03:17 PM UTC 24
Finished Aug 27 03:03:49 PM UTC 24
Peak memory 253364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031948736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1031948736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.3978149521
Short name T70
Test name
Test status
Simulation time 733331059 ps
CPU time 10.92 seconds
Started Aug 27 03:03:24 PM UTC 24
Finished Aug 27 03:03:36 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978149521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.3978149521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.2890973682
Short name T9
Test name
Test status
Simulation time 3369489954 ps
CPU time 40.48 seconds
Started Aug 27 03:03:18 PM UTC 24
Finished Aug 27 03:04:00 PM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890973682 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.2890973682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.881292046
Short name T368
Test name
Test status
Simulation time 20032615158 ps
CPU time 84.88 seconds
Started Aug 27 03:03:34 PM UTC 24
Finished Aug 27 03:05:01 PM UTC 24
Peak memory 255572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881292046 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.881292046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.3031922788
Short name T67
Test name
Test status
Simulation time 127995412 ps
CPU time 3.73 seconds
Started Aug 27 03:03:18 PM UTC 24
Finished Aug 27 03:03:23 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031922788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3031922788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.3387446703
Short name T179
Test name
Test status
Simulation time 158921080 ps
CPU time 4.76 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387446703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3387446703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.381681329
Short name T29
Test name
Test status
Simulation time 10423303397 ps
CPU time 180.99 seconds
Started Aug 27 03:03:47 PM UTC 24
Finished Aug 27 03:06:51 PM UTC 24
Peak memory 298268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381681329 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.381681329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.1233469289
Short name T36
Test name
Test status
Simulation time 935757795 ps
CPU time 19.47 seconds
Started Aug 27 03:03:44 PM UTC 24
Finished Aug 27 03:04:04 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233469289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.1233469289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3722507429
Short name T199
Test name
Test status
Simulation time 180553466 ps
CPU time 7.95 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:15 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722507429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3722507429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.2565007376
Short name T255
Test name
Test status
Simulation time 761994516 ps
CPU time 24.21 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:04:20 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565007376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2565007376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.2733338626
Short name T280
Test name
Test status
Simulation time 16641327904 ps
CPU time 114.71 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:05:54 PM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733338626 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.2733338626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.2679703096
Short name T98
Test name
Test status
Simulation time 19953512250 ps
CPU time 165.67 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:07:18 PM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679703096 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.2679703096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1634201323
Short name T58
Test name
Test status
Simulation time 1692206740 ps
CPU time 31.39 seconds
Started Aug 27 03:04:21 PM UTC 24
Finished Aug 27 03:04:53 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634201323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1634201323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.1926911802
Short name T171
Test name
Test status
Simulation time 4151769303 ps
CPU time 19.51 seconds
Started Aug 27 03:04:02 PM UTC 24
Finished Aug 27 03:04:23 PM UTC 24
Peak memory 255736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926911802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1926911802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.1088206800
Short name T119
Test name
Test status
Simulation time 546568540 ps
CPU time 15.28 seconds
Started Aug 27 03:03:46 PM UTC 24
Finished Aug 27 03:04:03 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088206800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1088206800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3701957299
Short name T415
Test name
Test status
Simulation time 4876574955 ps
CPU time 19.69 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701957299 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.3701957299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1177844354
Short name T30
Test name
Test status
Simulation time 220443482 ps
CPU time 3.97 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:31 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177844354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1177844354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1473406474
Short name T15
Test name
Test status
Simulation time 31371717574 ps
CPU time 55.69 seconds
Started Aug 27 03:04:03 PM UTC 24
Finished Aug 27 03:05:00 PM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1473406474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.otp_ctrl_stress_all_with_rand_reset.1473406474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.1550605238
Short name T158
Test name
Test status
Simulation time 8704149953 ps
CPU time 95.38 seconds
Started Aug 27 03:05:37 PM UTC 24
Finished Aug 27 03:07:15 PM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550605238 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.1550605238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3624540679
Short name T22
Test name
Test status
Simulation time 7048237648 ps
CPU time 117.05 seconds
Started Aug 27 03:05:30 PM UTC 24
Finished Aug 27 03:07:29 PM UTC 24
Peak memory 274288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3624540679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.otp_ctrl_stress_all_with_rand_reset.3624540679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.18110349
Short name T81
Test name
Test status
Simulation time 2343631995 ps
CPU time 23.75 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:22 PM UTC 24
Peak memory 255744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18110349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.18110349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.2611692697
Short name T130
Test name
Test status
Simulation time 2593943390 ps
CPU time 21.43 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:11 PM UTC 24
Peak memory 257424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611692697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2611692697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.4235405209
Short name T192
Test name
Test status
Simulation time 22388959239 ps
CPU time 35.71 seconds
Started Aug 27 03:04:24 PM UTC 24
Finished Aug 27 03:05:02 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235405209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.4235405209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.1678443196
Short name T77
Test name
Test status
Simulation time 145476261 ps
CPU time 4 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678443196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1678443196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.2813144771
Short name T315
Test name
Test status
Simulation time 192555310 ps
CPU time 2.9 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:01 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813144771 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2813144771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.1605115617
Short name T2
Test name
Test status
Simulation time 183434372 ps
CPU time 3.2 seconds
Started Aug 27 03:02:56 PM UTC 24
Finished Aug 27 03:03:00 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605115617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1605115617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.3608916143
Short name T200
Test name
Test status
Simulation time 331509190 ps
CPU time 7.19 seconds
Started Aug 27 03:03:40 PM UTC 24
Finished Aug 27 03:03:49 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608916143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3608916143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4218486881
Short name T309
Test name
Test status
Simulation time 49296020 ps
CPU time 1.54 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:57 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218486881 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.4218486881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.3157625897
Short name T64
Test name
Test status
Simulation time 303610609 ps
CPU time 5.06 seconds
Started Aug 27 03:06:15 PM UTC 24
Finished Aug 27 03:06:21 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157625897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3157625897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.4078616638
Short name T94
Test name
Test status
Simulation time 3937034913 ps
CPU time 25.32 seconds
Started Aug 27 03:03:01 PM UTC 24
Finished Aug 27 03:03:28 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078616638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.4078616638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2930553455
Short name T322
Test name
Test status
Simulation time 2662761465 ps
CPU time 88.72 seconds
Started Aug 27 03:05:44 PM UTC 24
Finished Aug 27 03:07:15 PM UTC 24
Peak memory 268176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2930553455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.otp_ctrl_stress_all_with_rand_reset.2930553455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.3376246435
Short name T439
Test name
Test status
Simulation time 1510553120 ps
CPU time 31.31 seconds
Started Aug 27 03:04:34 PM UTC 24
Finished Aug 27 03:05:06 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376246435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3376246435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.2958878023
Short name T193
Test name
Test status
Simulation time 1354727348 ps
CPU time 3.75 seconds
Started Aug 27 03:11:13 PM UTC 24
Finished Aug 27 03:11:17 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958878023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2958878023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.3396997335
Short name T298
Test name
Test status
Simulation time 3948479873 ps
CPU time 8.77 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:03:59 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396997335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3396997335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.1162340875
Short name T100
Test name
Test status
Simulation time 1393938406 ps
CPU time 5.47 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:29 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162340875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1162340875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.930785956
Short name T389
Test name
Test status
Simulation time 23493270102 ps
CPU time 104.48 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:06:25 PM UTC 24
Peak memory 255420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930785956 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.930785956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.3311241563
Short name T44
Test name
Test status
Simulation time 128316818 ps
CPU time 4.28 seconds
Started Aug 27 03:08:08 PM UTC 24
Finished Aug 27 03:08:13 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311241563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3311241563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.1122950886
Short name T84
Test name
Test status
Simulation time 155846778 ps
CPU time 3.71 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:03:59 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122950886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1122950886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.1501471571
Short name T76
Test name
Test status
Simulation time 2923033533 ps
CPU time 6.69 seconds
Started Aug 27 03:10:38 PM UTC 24
Finished Aug 27 03:10:46 PM UTC 24
Peak memory 251124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501471571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1501471571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.2585827268
Short name T1028
Test name
Test status
Simulation time 2229604964 ps
CPU time 4.93 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585827268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2585827268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3932944805
Short name T127
Test name
Test status
Simulation time 115488197 ps
CPU time 3.82 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:03:54 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932944805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3932944805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2103703825
Short name T390
Test name
Test status
Simulation time 6415870227 ps
CPU time 144.49 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:06:53 PM UTC 24
Peak memory 292588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103703825 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.2103703825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.2763968287
Short name T48
Test name
Test status
Simulation time 2496857276 ps
CPU time 31.91 seconds
Started Aug 27 03:06:34 PM UTC 24
Finished Aug 27 03:07:07 PM UTC 24
Peak memory 253492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763968287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2763968287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.3547541556
Short name T189
Test name
Test status
Simulation time 1022585308 ps
CPU time 23.63 seconds
Started Aug 27 03:05:14 PM UTC 24
Finished Aug 27 03:05:39 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547541556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3547541556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.844516383
Short name T998
Test name
Test status
Simulation time 2496371587 ps
CPU time 105.41 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:11:17 PM UTC 24
Peak memory 267824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=844516383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
70.otp_ctrl_stress_all_with_rand_reset.844516383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.3997892703
Short name T151
Test name
Test status
Simulation time 3665421973 ps
CPU time 11.34 seconds
Started Aug 27 03:07:15 PM UTC 24
Finished Aug 27 03:07:28 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997892703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3997892703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.4143235174
Short name T304
Test name
Test status
Simulation time 717622831 ps
CPU time 7.36 seconds
Started Aug 27 03:10:44 PM UTC 24
Finished Aug 27 03:10:52 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143235174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.4143235174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.4290550508
Short name T229
Test name
Test status
Simulation time 12960176381 ps
CPU time 130.75 seconds
Started Aug 27 03:05:45 PM UTC 24
Finished Aug 27 03:07:58 PM UTC 24
Peak memory 267968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290550508 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.4290550508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.3228645319
Short name T299
Test name
Test status
Simulation time 1127052882 ps
CPU time 10.12 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:17 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228645319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3228645319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3752006372
Short name T332
Test name
Test status
Simulation time 244511573 ps
CPU time 5.59 seconds
Started Aug 27 03:11:56 PM UTC 24
Finished Aug 27 03:12:03 PM UTC 24
Peak memory 252888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752006372 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.3752006372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.1940082662
Short name T6
Test name
Test status
Simulation time 1564789959 ps
CPU time 16.61 seconds
Started Aug 27 03:02:58 PM UTC 24
Finished Aug 27 03:03:16 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940082662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1940082662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.599284408
Short name T87
Test name
Test status
Simulation time 181634861 ps
CPU time 3.8 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:20 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599284408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.599284408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.616256002
Short name T163
Test name
Test status
Simulation time 212949821 ps
CPU time 5.99 seconds
Started Aug 27 03:10:30 PM UTC 24
Finished Aug 27 03:10:38 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616256002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.616256002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.267776289
Short name T166
Test name
Test status
Simulation time 303233437 ps
CPU time 8.15 seconds
Started Aug 27 03:09:39 PM UTC 24
Finished Aug 27 03:09:48 PM UTC 24
Peak memory 257300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267776289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.267776289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3053039113
Short name T153
Test name
Test status
Simulation time 16030850962 ps
CPU time 119.55 seconds
Started Aug 27 03:10:02 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 274264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3053039113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 87.otp_ctrl_stress_all_with_rand_reset.3053039113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.549203633
Short name T154
Test name
Test status
Simulation time 181308959 ps
CPU time 7.27 seconds
Started Aug 27 03:06:09 PM UTC 24
Finished Aug 27 03:06:17 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549203633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.549203633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.1155399043
Short name T157
Test name
Test status
Simulation time 3122802590 ps
CPU time 78.01 seconds
Started Aug 27 03:04:17 PM UTC 24
Finished Aug 27 03:05:37 PM UTC 24
Peak memory 271896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155399043 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.1155399043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1124941785
Short name T418
Test name
Test status
Simulation time 2220431288 ps
CPU time 18.67 seconds
Started Aug 27 03:12:11 PM UTC 24
Finished Aug 27 03:12:31 PM UTC 24
Peak memory 256936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124941785 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.1124941785
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2219255592
Short name T131
Test name
Test status
Simulation time 227362540 ps
CPU time 3.57 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219255592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2219255592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.2858166367
Short name T140
Test name
Test status
Simulation time 248892810 ps
CPU time 7.51 seconds
Started Aug 27 03:06:17 PM UTC 24
Finished Aug 27 03:06:26 PM UTC 24
Peak memory 253748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858166367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2858166367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.479114987
Short name T164
Test name
Test status
Simulation time 533593021 ps
CPU time 19.78 seconds
Started Aug 27 03:10:35 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479114987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.479114987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.3342748011
Short name T135
Test name
Test status
Simulation time 662396506 ps
CPU time 6.51 seconds
Started Aug 27 03:04:33 PM UTC 24
Finished Aug 27 03:04:41 PM UTC 24
Peak memory 250640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342748011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3342748011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.195213091
Short name T90
Test name
Test status
Simulation time 209511316 ps
CPU time 4.04 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195213091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.195213091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.3876495404
Short name T99
Test name
Test status
Simulation time 227924652 ps
CPU time 7.08 seconds
Started Aug 27 03:09:20 PM UTC 24
Finished Aug 27 03:09:29 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876495404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3876495404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.2249145795
Short name T288
Test name
Test status
Simulation time 957443880 ps
CPU time 12.6 seconds
Started Aug 27 03:09:33 PM UTC 24
Finished Aug 27 03:09:47 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249145795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2249145795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.2001074725
Short name T547
Test name
Test status
Simulation time 526105602 ps
CPU time 9.7 seconds
Started Aug 27 03:05:44 PM UTC 24
Finished Aug 27 03:05:55 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001074725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2001074725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2173131146
Short name T359
Test name
Test status
Simulation time 1239721062 ps
CPU time 4.33 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173131146 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.2173131146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3207747588
Short name T14
Test name
Test status
Simulation time 1542030955 ps
CPU time 46.33 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:45 PM UTC 24
Peak memory 257896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3207747588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.otp_ctrl_stress_all_with_rand_reset.3207747588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.1959923606
Short name T114
Test name
Test status
Simulation time 1514297722 ps
CPU time 9.73 seconds
Started Aug 27 03:03:23 PM UTC 24
Finished Aug 27 03:03:34 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959923606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1959923606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.3416290204
Short name T112
Test name
Test status
Simulation time 12987668585 ps
CPU time 34.48 seconds
Started Aug 27 03:03:59 PM UTC 24
Finished Aug 27 03:04:35 PM UTC 24
Peak memory 253328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416290204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3416290204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.2610507495
Short name T7
Test name
Test status
Simulation time 1150677741 ps
CPU time 7.32 seconds
Started Aug 27 03:03:09 PM UTC 24
Finished Aug 27 03:03:18 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610507495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2610507495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.694884344
Short name T412
Test name
Test status
Simulation time 4104961973 ps
CPU time 16.35 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:27 PM UTC 24
Peak memory 257056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694884344 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.694884344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.2175582542
Short name T501
Test name
Test status
Simulation time 4475638226 ps
CPU time 28.35 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:56 PM UTC 24
Peak memory 253348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175582542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2175582542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1777335799
Short name T92
Test name
Test status
Simulation time 13916464200 ps
CPU time 164.42 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:07:17 PM UTC 24
Peak memory 284336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1777335799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.otp_ctrl_stress_all_with_rand_reset.1777335799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.89355856
Short name T419
Test name
Test status
Simulation time 816015990 ps
CPU time 6.31 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:22 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89355856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ot
p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.89355856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.2183102704
Short name T49
Test name
Test status
Simulation time 666393084 ps
CPU time 13.81 seconds
Started Aug 27 03:06:09 PM UTC 24
Finished Aug 27 03:06:24 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183102704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2183102704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.3335461575
Short name T37
Test name
Test status
Simulation time 2180272155 ps
CPU time 26.86 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:17 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335461575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3335461575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.1553810183
Short name T500
Test name
Test status
Simulation time 2447045422 ps
CPU time 15.72 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:56 PM UTC 24
Peak memory 251740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553810183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1553810183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.3401727167
Short name T53
Test name
Test status
Simulation time 424059468 ps
CPU time 3.92 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:10:21 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401727167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3401727167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.740112136
Short name T110
Test name
Test status
Simulation time 78769645 ps
CPU time 3.02 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:04:34 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740112136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.740112136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.1201070665
Short name T35
Test name
Test status
Simulation time 287336091 ps
CPU time 4.54 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201070665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1201070665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.3143839393
Short name T186
Test name
Test status
Simulation time 585642716 ps
CPU time 4.64 seconds
Started Aug 27 03:04:50 PM UTC 24
Finished Aug 27 03:04:56 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143839393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3143839393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.1687696806
Short name T194
Test name
Test status
Simulation time 2264789303 ps
CPU time 7.04 seconds
Started Aug 27 03:05:47 PM UTC 24
Finished Aug 27 03:05:55 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687696806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1687696806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.3021793713
Short name T219
Test name
Test status
Simulation time 1274823791 ps
CPU time 13.17 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:05:56 PM UTC 24
Peak memory 253536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021793713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3021793713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.3583688412
Short name T303
Test name
Test status
Simulation time 16385334810 ps
CPU time 149.18 seconds
Started Aug 27 03:05:53 PM UTC 24
Finished Aug 27 03:08:25 PM UTC 24
Peak memory 257728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583688412 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.3583688412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2373980634
Short name T261
Test name
Test status
Simulation time 887563169 ps
CPU time 6.11 seconds
Started Aug 27 03:04:02 PM UTC 24
Finished Aug 27 03:04:10 PM UTC 24
Peak memory 251008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373980634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2373980634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.4065881713
Short name T413
Test name
Test status
Simulation time 2670235051 ps
CPU time 18.86 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:15 PM UTC 24
Peak memory 258988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065881713 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.4065881713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3052219894
Short name T310
Test name
Test status
Simulation time 92461375 ps
CPU time 2.98 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 252736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052219894 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.3052219894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.221827008
Short name T270
Test name
Test status
Simulation time 22857993667 ps
CPU time 160.3 seconds
Started Aug 27 03:03:51 PM UTC 24
Finished Aug 27 03:06:34 PM UTC 24
Peak memory 271860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221827008 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.221827008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.1969350193
Short name T1
Test name
Test status
Simulation time 199087496 ps
CPU time 1.53 seconds
Started Aug 27 03:02:53 PM UTC 24
Finished Aug 27 03:02:55 PM UTC 24
Peak memory 250576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969350193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1969350193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.3179479157
Short name T121
Test name
Test status
Simulation time 358751136 ps
CPU time 3.7 seconds
Started Aug 27 03:03:17 PM UTC 24
Finished Aug 27 03:03:22 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179479157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3179479157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.1752054002
Short name T148
Test name
Test status
Simulation time 46501601931 ps
CPU time 254.99 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:09:20 PM UTC 24
Peak memory 273884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752054002 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.1752054002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.3210184882
Short name T277
Test name
Test status
Simulation time 10592703103 ps
CPU time 88.12 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:06:31 PM UTC 24
Peak memory 274224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3210184882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.otp_ctrl_stress_all_with_rand_reset.3210184882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1537382487
Short name T313
Test name
Test status
Simulation time 2416507318 ps
CPU time 16.65 seconds
Started Aug 27 03:12:10 PM UTC 24
Finished Aug 27 03:12:28 PM UTC 24
Peak memory 252848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537382487 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.1537382487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3648563125
Short name T278
Test name
Test status
Simulation time 506631384 ps
CPU time 3.63 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648563125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3648563125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.370798380
Short name T459
Test name
Test status
Simulation time 590122119 ps
CPU time 15.25 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:42 PM UTC 24
Peak memory 257360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370798380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.370798380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.2552179320
Short name T297
Test name
Test status
Simulation time 137913105 ps
CPU time 4.86 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552179320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.2552179320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1603733106
Short name T227
Test name
Test status
Simulation time 559506523 ps
CPU time 10.97 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:04:06 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603733106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1603733106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.2009398717
Short name T59
Test name
Test status
Simulation time 5161164189 ps
CPU time 36.11 seconds
Started Aug 27 03:04:29 PM UTC 24
Finished Aug 27 03:05:07 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009398717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2009398717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2843766323
Short name T105
Test name
Test status
Simulation time 382899290 ps
CPU time 3.37 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:49 PM UTC 24
Peak memory 250988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843766323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2843766323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.2598422702
Short name T89
Test name
Test status
Simulation time 481391619 ps
CPU time 3.4 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:21 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598422702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2598422702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.3935275247
Short name T88
Test name
Test status
Simulation time 322412073 ps
CPU time 6.71 seconds
Started Aug 27 03:07:05 PM UTC 24
Finished Aug 27 03:07:13 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935275247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3935275247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.2729300279
Short name T124
Test name
Test status
Simulation time 267179979 ps
CPU time 7.27 seconds
Started Aug 27 03:03:29 PM UTC 24
Finished Aug 27 03:03:37 PM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729300279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2729300279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.957056165
Short name T265
Test name
Test status
Simulation time 338350815 ps
CPU time 5.49 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:04:50 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957056165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.957056165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.360007460
Short name T331
Test name
Test status
Simulation time 165417379 ps
CPU time 5.77 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:02 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360007460 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.360007460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2540241196
Short name T311
Test name
Test status
Simulation time 403259613 ps
CPU time 3.41 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 252768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540241196 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.2540241196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1203199990
Short name T312
Test name
Test status
Simulation time 272750081 ps
CPU time 3.46 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 259048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1203199990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs
r_mem_rw_with_rand_reset.1203199990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2997463465
Short name T1183
Test name
Test status
Simulation time 79812125 ps
CPU time 1.29 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:57 PM UTC 24
Peak memory 241860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997463465 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2997463465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1459900578
Short name T1184
Test name
Test status
Simulation time 74339693 ps
CPU time 1.23 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:57 PM UTC 24
Peak memory 240272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459900578 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.1459900578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1954070209
Short name T1187
Test name
Test status
Simulation time 513384648 ps
CPU time 2.3 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:58 PM UTC 24
Peak memory 241716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954070209 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.1954070209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2551567814
Short name T1190
Test name
Test status
Simulation time 149090406 ps
CPU time 4.91 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 258956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551567814 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2551567814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1896638908
Short name T1209
Test name
Test status
Simulation time 382542411 ps
CPU time 9.13 seconds
Started Aug 27 03:11:56 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 242344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896638908 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.1896638908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4277748822
Short name T344
Test name
Test status
Simulation time 179925928 ps
CPU time 2.4 seconds
Started Aug 27 03:11:56 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 252880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277748822 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.4277748822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1004404516
Short name T427
Test name
Test status
Simulation time 182794547 ps
CPU time 2.94 seconds
Started Aug 27 03:11:57 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 258948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1004404516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs
r_mem_rw_with_rand_reset.1004404516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2712417382
Short name T358
Test name
Test status
Simulation time 79405276 ps
CPU time 1.83 seconds
Started Aug 27 03:11:56 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712417382 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2712417382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.704660369
Short name T1186
Test name
Test status
Simulation time 75612895 ps
CPU time 1.97 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:58 PM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704660369 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.704660369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.824497311
Short name T1188
Test name
Test status
Simulation time 135683969 ps
CPU time 1.49 seconds
Started Aug 27 03:11:56 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 240544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824497311 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.824497311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2164884362
Short name T1185
Test name
Test status
Simulation time 71414488 ps
CPU time 1.61 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:11:58 PM UTC 24
Peak memory 240336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164884362 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.2164884362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1930362844
Short name T352
Test name
Test status
Simulation time 548890579 ps
CPU time 4.21 seconds
Started Aug 27 03:11:56 PM UTC 24
Finished Aug 27 03:12:02 PM UTC 24
Peak memory 252800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930362844 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.1930362844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3407020848
Short name T1189
Test name
Test status
Simulation time 222414000 ps
CPU time 3.96 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 259084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407020848 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3407020848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3769616687
Short name T1236
Test name
Test status
Simulation time 1728711930 ps
CPU time 3.1 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:12 PM UTC 24
Peak memory 258876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3769616687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c
sr_mem_rw_with_rand_reset.3769616687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1148014215
Short name T1226
Test name
Test status
Simulation time 46276763 ps
CPU time 1.5 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:10 PM UTC 24
Peak memory 251716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148014215 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1148014215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.570449647
Short name T1221
Test name
Test status
Simulation time 524286949 ps
CPU time 1.61 seconds
Started Aug 27 03:12:06 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 241132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570449647 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.570449647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.4001447530
Short name T1234
Test name
Test status
Simulation time 99098380 ps
CPU time 2.16 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 252516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001447530 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.4001447530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1434363562
Short name T1246
Test name
Test status
Simulation time 804151728 ps
CPU time 6.61 seconds
Started Aug 27 03:12:06 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 259048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434363562 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1434363562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1006665294
Short name T1270
Test name
Test status
Simulation time 688833591 ps
CPU time 9.74 seconds
Started Aug 27 03:12:06 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 252836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006665294 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.1006665294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1701326709
Short name T1244
Test name
Test status
Simulation time 112172830 ps
CPU time 4.19 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 258840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1701326709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c
sr_mem_rw_with_rand_reset.1701326709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.4139968257
Short name T1231
Test name
Test status
Simulation time 55512402 ps
CPU time 1.87 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 253844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139968257 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.4139968257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.2219991431
Short name T1232
Test name
Test status
Simulation time 43718126 ps
CPU time 1.57 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 241640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219991431 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2219991431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.644843551
Short name T1251
Test name
Test status
Simulation time 1697198265 ps
CPU time 5.07 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 254772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644843551 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.644843551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3964128467
Short name T1252
Test name
Test status
Simulation time 1919672201 ps
CPU time 5.2 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 259016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964128467 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3964128467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.881155705
Short name T417
Test name
Test status
Simulation time 1642940438 ps
CPU time 19.69 seconds
Started Aug 27 03:12:07 PM UTC 24
Finished Aug 27 03:12:29 PM UTC 24
Peak memory 256800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881155705 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.881155705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.4249414044
Short name T1235
Test name
Test status
Simulation time 69224304 ps
CPU time 2.07 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 257048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4249414044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c
sr_mem_rw_with_rand_reset.4249414044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.834079503
Short name T314
Test name
Test status
Simulation time 152377717 ps
CPU time 1.57 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 251828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834079503 -assert nopostproc +UVM_TESTNAME=otp_
ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.834079503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.2466188515
Short name T1208
Test name
Test status
Simulation time 575911745 ps
CPU time 1.61 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 241640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466188515 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2466188515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1117694031
Short name T1238
Test name
Test status
Simulation time 1241801254 ps
CPU time 2.9 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:12 PM UTC 24
Peak memory 252480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117694031 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.1117694031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4010871992
Short name T1261
Test name
Test status
Simulation time 195067097 ps
CPU time 6.22 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 258792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010871992 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.4010871992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1235368883
Short name T307
Test name
Test status
Simulation time 688455468 ps
CPU time 9.82 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 256616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235368883 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.1235368883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3532119633
Short name T1242
Test name
Test status
Simulation time 165889974 ps
CPU time 2.5 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 258916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3532119633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c
sr_mem_rw_with_rand_reset.3532119633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3815305254
Short name T348
Test name
Test status
Simulation time 630298222 ps
CPU time 2.09 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 254888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815305254 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3815305254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.3127481150
Short name T1228
Test name
Test status
Simulation time 554425130 ps
CPU time 1.42 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127481150 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3127481150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2710403129
Short name T1253
Test name
Test status
Simulation time 1302831360 ps
CPU time 4.07 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:15 PM UTC 24
Peak memory 252684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710403129 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.2710403129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.408508403
Short name T1259
Test name
Test status
Simulation time 303774183 ps
CPU time 6.1 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 258956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408508403 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.408508403
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3125439645
Short name T1305
Test name
Test status
Simulation time 1311276463 ps
CPU time 17.2 seconds
Started Aug 27 03:12:08 PM UTC 24
Finished Aug 27 03:12:27 PM UTC 24
Peak memory 252624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125439645 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.3125439645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.338698061
Short name T1245
Test name
Test status
Simulation time 154179525 ps
CPU time 2.55 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 256924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=338698061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_cs
r_mem_rw_with_rand_reset.338698061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1934212606
Short name T1237
Test name
Test status
Simulation time 44066670 ps
CPU time 1.55 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:12 PM UTC 24
Peak memory 253972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934212606 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1934212606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.1896576796
Short name T1240
Test name
Test status
Simulation time 42374677 ps
CPU time 1.68 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 241464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896576796 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1896576796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2934691553
Short name T1243
Test name
Test status
Simulation time 75486286 ps
CPU time 2.19 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 254684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934691553 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.2934691553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2932451465
Short name T1276
Test name
Test status
Simulation time 2924609211 ps
CPU time 6.77 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 259096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932451465 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2932451465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.633150476
Short name T306
Test name
Test status
Simulation time 623482606 ps
CPU time 8.6 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 252708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633150476 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.633150476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1164328869
Short name T1247
Test name
Test status
Simulation time 70088268 ps
CPU time 2.46 seconds
Started Aug 27 03:12:10 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 257024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1164328869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c
sr_mem_rw_with_rand_reset.1164328869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2542247379
Short name T349
Test name
Test status
Simulation time 57645802 ps
CPU time 1.85 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 250868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542247379 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2542247379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.3862569698
Short name T1239
Test name
Test status
Simulation time 137399035 ps
CPU time 1.3 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:12 PM UTC 24
Peak memory 241464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862569698 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3862569698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.158167722
Short name T1249
Test name
Test status
Simulation time 98968750 ps
CPU time 2.78 seconds
Started Aug 27 03:12:10 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 252900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158167722 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.158167722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3285719935
Short name T1264
Test name
Test status
Simulation time 325481735 ps
CPU time 5.3 seconds
Started Aug 27 03:12:09 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 259112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285719935 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.3285719935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1135762360
Short name T1254
Test name
Test status
Simulation time 110001450 ps
CPU time 2.59 seconds
Started Aug 27 03:12:11 PM UTC 24
Finished Aug 27 03:12:15 PM UTC 24
Peak memory 258852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1135762360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c
sr_mem_rw_with_rand_reset.1135762360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.529385328
Short name T1248
Test name
Test status
Simulation time 97161158 ps
CPU time 1.57 seconds
Started Aug 27 03:12:11 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 254024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529385328 -assert nopostproc +UVM_TESTNAME=otp_
ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.529385328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.1189220474
Short name T1241
Test name
Test status
Simulation time 45042665 ps
CPU time 1.4 seconds
Started Aug 27 03:12:10 PM UTC 24
Finished Aug 27 03:12:13 PM UTC 24
Peak memory 241080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189220474 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1189220474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2048291304
Short name T1250
Test name
Test status
Simulation time 75404081 ps
CPU time 2.04 seconds
Started Aug 27 03:12:11 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 254732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048291304 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.2048291304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1869253483
Short name T1273
Test name
Test status
Simulation time 195797473 ps
CPU time 5.79 seconds
Started Aug 27 03:12:10 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 259036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869253483 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1869253483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.710341378
Short name T1262
Test name
Test status
Simulation time 90888904 ps
CPU time 2.08 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=710341378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_cs
r_mem_rw_with_rand_reset.710341378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.62926057
Short name T351
Test name
Test status
Simulation time 114302513 ps
CPU time 1.64 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:15 PM UTC 24
Peak memory 254028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62926057 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.62926057
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.322614771
Short name T1260
Test name
Test status
Simulation time 552159202 ps
CPU time 2.14 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 242476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322614771 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.322614771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.998607177
Short name T1268
Test name
Test status
Simulation time 1060834462 ps
CPU time 3.15 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 252796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998607177 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.998607177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2260657293
Short name T1280
Test name
Test status
Simulation time 651589944 ps
CPU time 5.36 seconds
Started Aug 27 03:12:11 PM UTC 24
Finished Aug 27 03:12:18 PM UTC 24
Peak memory 259036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260657293 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.2260657293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.4007426196
Short name T1265
Test name
Test status
Simulation time 1009473358 ps
CPU time 2.47 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 256920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4007426196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c
sr_mem_rw_with_rand_reset.4007426196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3261893465
Short name T350
Test name
Test status
Simulation time 46149851 ps
CPU time 1.6 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 252024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261893465 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3261893465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.1097330569
Short name T1255
Test name
Test status
Simulation time 42962452 ps
CPU time 1.48 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:15 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097330569 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1097330569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.334338923
Short name T1279
Test name
Test status
Simulation time 1901563975 ps
CPU time 3.73 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:18 PM UTC 24
Peak memory 252684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334338923 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.334338923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1502507236
Short name T1278
Test name
Test status
Simulation time 1237939169 ps
CPU time 3.91 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:18 PM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502507236 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1502507236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2544319343
Short name T1307
Test name
Test status
Simulation time 1275839106 ps
CPU time 16.7 seconds
Started Aug 27 03:12:12 PM UTC 24
Finished Aug 27 03:12:31 PM UTC 24
Peak memory 252776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544319343 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.2544319343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1920191836
Short name T1275
Test name
Test status
Simulation time 169824418 ps
CPU time 2.35 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 258980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1920191836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c
sr_mem_rw_with_rand_reset.1920191836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.4284988325
Short name T1272
Test name
Test status
Simulation time 528209470 ps
CPU time 1.88 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 253908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284988325 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.4284988325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3726377566
Short name T1274
Test name
Test status
Simulation time 513767032 ps
CPU time 2.11 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 242468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726377566 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3726377566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.527187199
Short name T1277
Test name
Test status
Simulation time 263323485 ps
CPU time 2.46 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 252768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527187199 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.527187199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2746543276
Short name T1284
Test name
Test status
Simulation time 144151449 ps
CPU time 3.61 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 259076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746543276 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2746543276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2859750270
Short name T1300
Test name
Test status
Simulation time 1160208556 ps
CPU time 9.11 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:24 PM UTC 24
Peak memory 256904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859750270 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.2859750270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3615175703
Short name T429
Test name
Test status
Simulation time 109598000 ps
CPU time 2.84 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 252696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615175703 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.3615175703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1250357855
Short name T1219
Test name
Test status
Simulation time 283214786 ps
CPU time 5.56 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 252712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250357855 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.1250357855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1891007617
Short name T330
Test name
Test status
Simulation time 100772708 ps
CPU time 1.69 seconds
Started Aug 27 03:11:59 PM UTC 24
Finished Aug 27 03:12:02 PM UTC 24
Peak memory 251980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891007617 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.1891007617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.861215300
Short name T428
Test name
Test status
Simulation time 135502270 ps
CPU time 1.83 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 255988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=861215300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr
_mem_rw_with_rand_reset.861215300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3265189107
Short name T329
Test name
Test status
Simulation time 52768793 ps
CPU time 1.54 seconds
Started Aug 27 03:11:59 PM UTC 24
Finished Aug 27 03:12:02 PM UTC 24
Peak memory 251960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265189107 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3265189107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.3566720347
Short name T1191
Test name
Test status
Simulation time 40129537 ps
CPU time 1.38 seconds
Started Aug 27 03:11:59 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566720347 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3566720347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1934495406
Short name T1192
Test name
Test status
Simulation time 38246424 ps
CPU time 1.3 seconds
Started Aug 27 03:11:59 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 240272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934495406 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.1934495406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1458646250
Short name T1193
Test name
Test status
Simulation time 49659853 ps
CPU time 1.41 seconds
Started Aug 27 03:11:59 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 241820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458646250 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.1458646250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2359716983
Short name T354
Test name
Test status
Simulation time 1091097491 ps
CPU time 2.47 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 252732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359716983 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.2359716983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.752919507
Short name T1194
Test name
Test status
Simulation time 144728606 ps
CPU time 2.73 seconds
Started Aug 27 03:11:58 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 258908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752919507 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.752919507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1069080036
Short name T305
Test name
Test status
Simulation time 2934195336 ps
CPU time 9.28 seconds
Started Aug 27 03:11:58 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 256860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069080036 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.1069080036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.3670709437
Short name T1266
Test name
Test status
Simulation time 51105645 ps
CPU time 1.38 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670709437 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3670709437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1976350051
Short name T1267
Test name
Test status
Simulation time 38981399 ps
CPU time 1.45 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976350051 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1976350051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.928247729
Short name T1271
Test name
Test status
Simulation time 51735853 ps
CPU time 1.52 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928247729 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.928247729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3620632541
Short name T1269
Test name
Test status
Simulation time 75705588 ps
CPU time 1.37 seconds
Started Aug 27 03:12:14 PM UTC 24
Finished Aug 27 03:12:17 PM UTC 24
Peak memory 241692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620632541 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3620632541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2167897404
Short name T1282
Test name
Test status
Simulation time 140667916 ps
CPU time 1.5 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:18 PM UTC 24
Peak memory 241116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167897404 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2167897404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1050277792
Short name T1281
Test name
Test status
Simulation time 38066078 ps
CPU time 1.25 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:18 PM UTC 24
Peak memory 241116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050277792 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1050277792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2126226074
Short name T1283
Test name
Test status
Simulation time 529867212 ps
CPU time 1.4 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126226074 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2126226074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3464753072
Short name T1285
Test name
Test status
Simulation time 72719140 ps
CPU time 1.36 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464753072 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3464753072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2494556336
Short name T1288
Test name
Test status
Simulation time 56396904 ps
CPU time 1.56 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 240632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494556336 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2494556336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1756896323
Short name T1286
Test name
Test status
Simulation time 74394657 ps
CPU time 1.31 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 240728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756896323 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1756896323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1983866764
Short name T347
Test name
Test status
Simulation time 465807799 ps
CPU time 5.58 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:09 PM UTC 24
Peak memory 252744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983866764 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.1983866764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.194449423
Short name T361
Test name
Test status
Simulation time 222780240 ps
CPU time 3.32 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:06 PM UTC 24
Peak memory 252688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194449423 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.194449423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1060102612
Short name T334
Test name
Test status
Simulation time 102363721 ps
CPU time 2.2 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 252692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060102612 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.1060102612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2034794323
Short name T1204
Test name
Test status
Simulation time 268062293 ps
CPU time 2.25 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:06 PM UTC 24
Peak memory 256788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2034794323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs
r_mem_rw_with_rand_reset.2034794323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.85516229
Short name T360
Test name
Test status
Simulation time 88063273 ps
CPU time 1.48 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 253960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85516229 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.85516229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.3485381506
Short name T1197
Test name
Test status
Simulation time 39551789 ps
CPU time 1.3 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 240880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485381506 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3485381506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.172009410
Short name T1195
Test name
Test status
Simulation time 46328304 ps
CPU time 1.19 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 240240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172009410 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.172009410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.637015566
Short name T1198
Test name
Test status
Simulation time 129989071 ps
CPU time 1.38 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 240280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637015566 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.637015566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3854362149
Short name T336
Test name
Test status
Simulation time 236637530 ps
CPU time 2.31 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 254680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854362149 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.3854362149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.970337664
Short name T1205
Test name
Test status
Simulation time 73337373 ps
CPU time 3.19 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:06 PM UTC 24
Peak memory 259012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970337664 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.970337664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4089659995
Short name T1306
Test name
Test status
Simulation time 20107144870 ps
CPU time 26.59 seconds
Started Aug 27 03:12:01 PM UTC 24
Finished Aug 27 03:12:29 PM UTC 24
Peak memory 257120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089659995 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.4089659995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2202184883
Short name T1295
Test name
Test status
Simulation time 573297655 ps
CPU time 1.72 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202184883 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2202184883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.2606415366
Short name T1287
Test name
Test status
Simulation time 566099216 ps
CPU time 1.44 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606415366 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2606415366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3639269410
Short name T1292
Test name
Test status
Simulation time 143121859 ps
CPU time 1.47 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639269410 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.3639269410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1376220062
Short name T1233
Test name
Test status
Simulation time 45135292 ps
CPU time 1.45 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376220062 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1376220062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.447804503
Short name T1290
Test name
Test status
Simulation time 76233172 ps
CPU time 1.34 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447804503 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.447804503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3607412163
Short name T1289
Test name
Test status
Simulation time 97118319 ps
CPU time 1.31 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607412163 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3607412163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.1262204074
Short name T1294
Test name
Test status
Simulation time 137500541 ps
CPU time 1.29 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262204074 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1262204074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.2128468599
Short name T1257
Test name
Test status
Simulation time 97324019 ps
CPU time 1.36 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 240808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128468599 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2128468599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1557786336
Short name T1293
Test name
Test status
Simulation time 73937932 ps
CPU time 1.33 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557786336 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1557786336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2618346458
Short name T1291
Test name
Test status
Simulation time 136020502 ps
CPU time 1.33 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:19 PM UTC 24
Peak memory 241352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618346458 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2618346458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.367153269
Short name T1211
Test name
Test status
Simulation time 303963451 ps
CPU time 3.76 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 252788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367153269 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.367153269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1145029227
Short name T1263
Test name
Test status
Simulation time 6777983503 ps
CPU time 12.24 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 252772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145029227 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.1145029227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1582091845
Short name T335
Test name
Test status
Simulation time 129323592 ps
CPU time 1.57 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 252024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582091845 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1582091845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2264126504
Short name T1207
Test name
Test status
Simulation time 173321980 ps
CPU time 2.62 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:06 PM UTC 24
Peak memory 259104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2264126504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs
r_mem_rw_with_rand_reset.2264126504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.941193924
Short name T333
Test name
Test status
Simulation time 41564832 ps
CPU time 1.4 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 251912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941193924 -assert nopostproc +UVM_TESTNAME=otp_
ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.941193924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.1114650363
Short name T1199
Test name
Test status
Simulation time 143874431 ps
CPU time 1.39 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114650363 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1114650363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.727243862
Short name T1201
Test name
Test status
Simulation time 560293816 ps
CPU time 1.23 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 240276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727243862 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.727243862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.745877467
Short name T1200
Test name
Test status
Simulation time 46599169 ps
CPU time 1.2 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 240332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745877467 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.745877467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2843178334
Short name T355
Test name
Test status
Simulation time 670665647 ps
CPU time 2.41 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:06 PM UTC 24
Peak memory 254804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843178334 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.2843178334
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.215645072
Short name T1210
Test name
Test status
Simulation time 357691030 ps
CPU time 3.4 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 259096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215645072 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.215645072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.4092508724
Short name T316
Test name
Test status
Simulation time 726179502 ps
CPU time 10.03 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 256872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092508724 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.4092508724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.539961878
Short name T1258
Test name
Test status
Simulation time 48828258 ps
CPU time 1.32 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:22 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539961878 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.539961878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1716490702
Short name T1296
Test name
Test status
Simulation time 70923910 ps
CPU time 1.3 seconds
Started Aug 27 03:12:16 PM UTC 24
Finished Aug 27 03:12:22 PM UTC 24
Peak memory 241640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716490702 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1716490702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2964932510
Short name T1299
Test name
Test status
Simulation time 150740956 ps
CPU time 1.25 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:23 PM UTC 24
Peak memory 240868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964932510 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2964932510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3421871874
Short name T1297
Test name
Test status
Simulation time 134146209 ps
CPU time 1.2 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:23 PM UTC 24
Peak memory 241308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421871874 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3421871874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.1951308305
Short name T1298
Test name
Test status
Simulation time 54902746 ps
CPU time 1.25 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:23 PM UTC 24
Peak memory 241232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951308305 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.1951308305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.797105528
Short name T1303
Test name
Test status
Simulation time 74473346 ps
CPU time 1.23 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:26 PM UTC 24
Peak memory 241452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797105528 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.797105528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.54800144
Short name T1301
Test name
Test status
Simulation time 43031604 ps
CPU time 1.26 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:26 PM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54800144 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.54800144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.17986280
Short name T1302
Test name
Test status
Simulation time 39046300 ps
CPU time 1.19 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:26 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17986280 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.17986280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1338110483
Short name T1308
Test name
Test status
Simulation time 47272759 ps
CPU time 1.33 seconds
Started Aug 27 03:12:20 PM UTC 24
Finished Aug 27 03:12:36 PM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338110483 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1338110483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3828813029
Short name T1304
Test name
Test status
Simulation time 38181768 ps
CPU time 1.27 seconds
Started Aug 27 03:12:21 PM UTC 24
Finished Aug 27 03:12:26 PM UTC 24
Peak memory 241640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828813029 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3828813029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2525830637
Short name T1206
Test name
Test status
Simulation time 139917758 ps
CPU time 2.22 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:06 PM UTC 24
Peak memory 258908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2525830637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs
r_mem_rw_with_rand_reset.2525830637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1510223506
Short name T1203
Test name
Test status
Simulation time 72867994 ps
CPU time 1.55 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 258008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510223506 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1510223506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.2434487142
Short name T1202
Test name
Test status
Simulation time 68080720 ps
CPU time 1.27 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:05 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434487142 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2434487142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.4003220556
Short name T356
Test name
Test status
Simulation time 954844723 ps
CPU time 3.01 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003220556 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.4003220556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2539541819
Short name T1213
Test name
Test status
Simulation time 123059246 ps
CPU time 3.57 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 259196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539541819 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2539541819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2428396428
Short name T409
Test name
Test status
Simulation time 2592816258 ps
CPU time 16.01 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:20 PM UTC 24
Peak memory 252776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428396428 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2428396428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2409942153
Short name T1223
Test name
Test status
Simulation time 298492165 ps
CPU time 2.93 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:09 PM UTC 24
Peak memory 258948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2409942153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs
r_mem_rw_with_rand_reset.2409942153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2544845396
Short name T345
Test name
Test status
Simulation time 52091198 ps
CPU time 1.71 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 253956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544845396 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2544845396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.2954496
Short name T1212
Test name
Test status
Simulation time 40402501 ps
CPU time 1.29 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 241224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2954496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2104961080
Short name T1216
Test name
Test status
Simulation time 87062511 ps
CPU time 1.96 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 251912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104961080 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.2104961080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.742151258
Short name T1214
Test name
Test status
Simulation time 205280044 ps
CPU time 3.57 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:07 PM UTC 24
Peak memory 259084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742151258 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.742151258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3990999834
Short name T410
Test name
Test status
Simulation time 1211783645 ps
CPU time 16.01 seconds
Started Aug 27 03:12:02 PM UTC 24
Finished Aug 27 03:12:20 PM UTC 24
Peak memory 256800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990999834 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.3990999834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3467359405
Short name T1196
Test name
Test status
Simulation time 75221996 ps
CPU time 2.13 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 258888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3467359405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs
r_mem_rw_with_rand_reset.3467359405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3014650772
Short name T357
Test name
Test status
Simulation time 81078123 ps
CPU time 1.4 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 251976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014650772 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3014650772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3561328991
Short name T1215
Test name
Test status
Simulation time 595945510 ps
CPU time 1.56 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561328991 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3561328991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3342558151
Short name T1217
Test name
Test status
Simulation time 51257593 ps
CPU time 1.74 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 253904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342558151 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.3342558151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3850863492
Short name T1230
Test name
Test status
Simulation time 1876687312 ps
CPU time 4.78 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 259004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850863492 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3850863492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1392680848
Short name T416
Test name
Test status
Simulation time 2584199094 ps
CPU time 9.89 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 252820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392680848 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.1392680848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1247415383
Short name T1222
Test name
Test status
Simulation time 72737240 ps
CPU time 2.13 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:09 PM UTC 24
Peak memory 258852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1247415383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs
r_mem_rw_with_rand_reset.1247415383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2160283913
Short name T346
Test name
Test status
Simulation time 102345059 ps
CPU time 1.47 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 253908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160283913 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2160283913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.4162027687
Short name T1220
Test name
Test status
Simulation time 569668249 ps
CPU time 1.77 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162027687 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.4162027687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3307198433
Short name T1227
Test name
Test status
Simulation time 1938610142 ps
CPU time 4.07 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 254812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307198433 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.3307198433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.4116064911
Short name T1225
Test name
Test status
Simulation time 111213316 ps
CPU time 3.74 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:10 PM UTC 24
Peak memory 258956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116064911 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.4116064911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.636110717
Short name T411
Test name
Test status
Simulation time 1974615105 ps
CPU time 15.98 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:22 PM UTC 24
Peak memory 252708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636110717 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.636110717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4245439593
Short name T1229
Test name
Test status
Simulation time 403648260 ps
CPU time 4.03 seconds
Started Aug 27 03:12:06 PM UTC 24
Finished Aug 27 03:12:11 PM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4245439593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs
r_mem_rw_with_rand_reset.4245439593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2516558926
Short name T353
Test name
Test status
Simulation time 51114188 ps
CPU time 1.64 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 251864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516558926 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2516558926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.2965167700
Short name T1218
Test name
Test status
Simulation time 129322941 ps
CPU time 1.35 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:08 PM UTC 24
Peak memory 241752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965167700 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2965167700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.151393571
Short name T1224
Test name
Test status
Simulation time 128898901 ps
CPU time 3.3 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:10 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151393571 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.151393571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3746514650
Short name T1256
Test name
Test status
Simulation time 3233984825 ps
CPU time 8.67 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:15 PM UTC 24
Peak memory 259060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746514650 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3746514650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.658533531
Short name T414
Test name
Test status
Simulation time 1245695858 ps
CPU time 9.29 seconds
Started Aug 27 03:12:05 PM UTC 24
Finished Aug 27 03:12:16 PM UTC 24
Peak memory 256952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658533531 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.658533531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.3637789923
Short name T13
Test name
Test status
Simulation time 189931298 ps
CPU time 1.41 seconds
Started Aug 27 03:03:18 PM UTC 24
Finished Aug 27 03:03:20 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637789923 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3637789923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.3104002700
Short name T8
Test name
Test status
Simulation time 653263026 ps
CPU time 15.88 seconds
Started Aug 27 03:03:06 PM UTC 24
Finished Aug 27 03:03:23 PM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104002700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3104002700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.1620129189
Short name T5
Test name
Test status
Simulation time 7335651259 ps
CPU time 9.59 seconds
Started Aug 27 03:02:55 PM UTC 24
Finished Aug 27 03:03:05 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620129189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1620129189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.1139588427
Short name T134
Test name
Test status
Simulation time 4359652330 ps
CPU time 24.26 seconds
Started Aug 27 03:03:09 PM UTC 24
Finished Aug 27 03:03:35 PM UTC 24
Peak memory 255544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139588427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1139588427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.2428501486
Short name T4
Test name
Test status
Simulation time 2740516138 ps
CPU time 5.87 seconds
Started Aug 27 03:03:01 PM UTC 24
Finished Aug 27 03:03:08 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428501486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2428501486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.1980172683
Short name T11
Test name
Test status
Simulation time 610274172 ps
CPU time 13.64 seconds
Started Aug 27 03:02:54 PM UTC 24
Finished Aug 27 03:03:09 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980172683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1980172683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.4158976165
Short name T28
Test name
Test status
Simulation time 15323027223 ps
CPU time 194.13 seconds
Started Aug 27 03:03:18 PM UTC 24
Finished Aug 27 03:06:35 PM UTC 24
Peak memory 285920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158976165 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.4158976165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.2992290140
Short name T3
Test name
Test status
Simulation time 834328954 ps
CPU time 6.68 seconds
Started Aug 27 03:02:53 PM UTC 24
Finished Aug 27 03:03:01 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992290140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.2992290140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.2847497950
Short name T17
Test name
Test status
Simulation time 6893568899 ps
CPU time 15.01 seconds
Started Aug 27 03:03:17 PM UTC 24
Finished Aug 27 03:03:33 PM UTC 24
Peak memory 253724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847497950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2847497950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.407297697
Short name T18
Test name
Test status
Simulation time 181667970 ps
CPU time 1.84 seconds
Started Aug 27 03:03:37 PM UTC 24
Finished Aug 27 03:03:40 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407297697 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.407297697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.3102079431
Short name T116
Test name
Test status
Simulation time 1398441970 ps
CPU time 19.68 seconds
Started Aug 27 03:03:19 PM UTC 24
Finished Aug 27 03:03:40 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102079431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3102079431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.3566228583
Short name T146
Test name
Test status
Simulation time 3701488857 ps
CPU time 12.63 seconds
Started Aug 27 03:03:24 PM UTC 24
Finished Aug 27 03:03:38 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566228583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3566228583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.607193096
Short name T216
Test name
Test status
Simulation time 4689186272 ps
CPU time 61.09 seconds
Started Aug 27 03:03:24 PM UTC 24
Finished Aug 27 03:04:27 PM UTC 24
Peak memory 268020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607193096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.607193096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.2802850572
Short name T282
Test name
Test status
Simulation time 20590943967 ps
CPU time 52.57 seconds
Started Aug 27 03:03:25 PM UTC 24
Finished Aug 27 03:04:20 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802850572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2802850572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3230113256
Short name T95
Test name
Test status
Simulation time 485848199 ps
CPU time 4.98 seconds
Started Aug 27 03:03:21 PM UTC 24
Finished Aug 27 03:03:28 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230113256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3230113256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.1843210642
Short name T115
Test name
Test status
Simulation time 621864897 ps
CPU time 13.79 seconds
Started Aug 27 03:03:20 PM UTC 24
Finished Aug 27 03:03:35 PM UTC 24
Peak memory 257624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843210642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1843210642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3036633705
Short name T27
Test name
Test status
Simulation time 19444803401 ps
CPU time 174.2 seconds
Started Aug 27 03:03:37 PM UTC 24
Finished Aug 27 03:06:34 PM UTC 24
Peak memory 296052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036633705 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3036633705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.1859131742
Short name T122
Test name
Test status
Simulation time 283432533 ps
CPU time 4.5 seconds
Started Aug 27 03:03:18 PM UTC 24
Finished Aug 27 03:03:24 PM UTC 24
Peak memory 251612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859131742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1859131742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.186756451
Short name T493
Test name
Test status
Simulation time 288414661 ps
CPU time 5.24 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:04:36 PM UTC 24
Peak memory 251132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186756451 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.186756451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.1406748921
Short name T444
Test name
Test status
Simulation time 5981070636 ps
CPU time 11.13 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:38 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406748921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1406748921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.2706287873
Short name T191
Test name
Test status
Simulation time 2707506333 ps
CPU time 12.65 seconds
Started Aug 27 03:04:29 PM UTC 24
Finished Aug 27 03:04:43 PM UTC 24
Peak memory 257504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706287873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2706287873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.1586537001
Short name T325
Test name
Test status
Simulation time 488117666 ps
CPU time 18.09 seconds
Started Aug 27 03:04:29 PM UTC 24
Finished Aug 27 03:04:49 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586537001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1586537001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1264177310
Short name T169
Test name
Test status
Simulation time 6393140078 ps
CPU time 16.7 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:44 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264177310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1264177310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.2706062589
Short name T263
Test name
Test status
Simulation time 282669441 ps
CPU time 6.62 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:04:38 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706062589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2706062589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.1794904153
Short name T108
Test name
Test status
Simulation time 249737983 ps
CPU time 5.48 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:32 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794904153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1794904153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.3325573458
Short name T337
Test name
Test status
Simulation time 1273362462 ps
CPU time 24.06 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:04:55 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325573458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3325573458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.3359385847
Short name T904
Test name
Test status
Simulation time 2302871724 ps
CPU time 6.2 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:36 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359385847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3359385847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.4033971492
Short name T901
Test name
Test status
Simulation time 193894307 ps
CPU time 5.41 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:35 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033971492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.4033971492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.2506162035
Short name T868
Test name
Test status
Simulation time 242253257 ps
CPU time 4.15 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:34 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506162035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2506162035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.3532744127
Short name T915
Test name
Test status
Simulation time 929253900 ps
CPU time 12.43 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:42 PM UTC 24
Peak memory 253212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532744127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.3532744127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.3389727085
Short name T902
Test name
Test status
Simulation time 137632632 ps
CPU time 5.47 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:35 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389727085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3389727085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.879473115
Short name T909
Test name
Test status
Simulation time 510494461 ps
CPU time 10.71 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:41 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879473115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.879473115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.1950632608
Short name T899
Test name
Test status
Simulation time 536474648 ps
CPU time 4.72 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:10:35 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950632608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1950632608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.1432349989
Short name T905
Test name
Test status
Simulation time 687971081 ps
CPU time 5.39 seconds
Started Aug 27 03:10:30 PM UTC 24
Finished Aug 27 03:10:37 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432349989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1432349989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.2003543584
Short name T923
Test name
Test status
Simulation time 250243061 ps
CPU time 13.48 seconds
Started Aug 27 03:10:31 PM UTC 24
Finished Aug 27 03:10:45 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003543584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2003543584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.223496994
Short name T903
Test name
Test status
Simulation time 94486857 ps
CPU time 3.93 seconds
Started Aug 27 03:10:31 PM UTC 24
Finished Aug 27 03:10:36 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223496994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.223496994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.460129602
Short name T916
Test name
Test status
Simulation time 470769835 ps
CPU time 9.24 seconds
Started Aug 27 03:10:33 PM UTC 24
Finished Aug 27 03:10:44 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460129602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.460129602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3459107792
Short name T911
Test name
Test status
Simulation time 506091899 ps
CPU time 5.02 seconds
Started Aug 27 03:10:35 PM UTC 24
Finished Aug 27 03:10:42 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459107792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3459107792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.2514887568
Short name T908
Test name
Test status
Simulation time 122692398 ps
CPU time 3.33 seconds
Started Aug 27 03:10:36 PM UTC 24
Finished Aug 27 03:10:40 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514887568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2514887568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.4140530303
Short name T912
Test name
Test status
Simulation time 123250004 ps
CPU time 5.19 seconds
Started Aug 27 03:10:36 PM UTC 24
Finished Aug 27 03:10:42 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140530303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.4140530303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.4065586807
Short name T910
Test name
Test status
Simulation time 108321782 ps
CPU time 4.48 seconds
Started Aug 27 03:10:36 PM UTC 24
Finished Aug 27 03:10:41 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065586807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.4065586807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.3356455568
Short name T913
Test name
Test status
Simulation time 193438512 ps
CPU time 5.14 seconds
Started Aug 27 03:10:36 PM UTC 24
Finished Aug 27 03:10:42 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356455568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3356455568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.2536613963
Short name T914
Test name
Test status
Simulation time 2170251162 ps
CPU time 5.13 seconds
Started Aug 27 03:10:36 PM UTC 24
Finished Aug 27 03:10:42 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536613963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2536613963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2178864587
Short name T927
Test name
Test status
Simulation time 702834614 ps
CPU time 9.24 seconds
Started Aug 27 03:10:38 PM UTC 24
Finished Aug 27 03:10:48 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178864587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2178864587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.520398746
Short name T495
Test name
Test status
Simulation time 109461734 ps
CPU time 1.73 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:42 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520398746 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.520398746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.4237161201
Short name T47
Test name
Test status
Simulation time 17375909568 ps
CPU time 35.37 seconds
Started Aug 27 03:04:33 PM UTC 24
Finished Aug 27 03:05:10 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237161201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.4237161201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.618280318
Short name T496
Test name
Test status
Simulation time 357649650 ps
CPU time 8.47 seconds
Started Aug 27 03:04:33 PM UTC 24
Finished Aug 27 03:04:43 PM UTC 24
Peak memory 251108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618280318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.618280318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.1878604577
Short name T473
Test name
Test status
Simulation time 2186990523 ps
CPU time 24.55 seconds
Started Aug 27 03:04:33 PM UTC 24
Finished Aug 27 03:04:59 PM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878604577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1878604577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.3278199194
Short name T198
Test name
Test status
Simulation time 1152517606 ps
CPU time 20.17 seconds
Started Aug 27 03:04:33 PM UTC 24
Finished Aug 27 03:04:55 PM UTC 24
Peak memory 255256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278199194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3278199194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.3132526715
Short name T436
Test name
Test status
Simulation time 650316561 ps
CPU time 22.73 seconds
Started Aug 27 03:04:34 PM UTC 24
Finished Aug 27 03:04:58 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132526715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3132526715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.4126603769
Short name T396
Test name
Test status
Simulation time 261830175 ps
CPU time 5.61 seconds
Started Aug 27 03:04:33 PM UTC 24
Finished Aug 27 03:04:40 PM UTC 24
Peak memory 250864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126603769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.4126603769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.4200996392
Short name T420
Test name
Test status
Simulation time 260910159 ps
CPU time 6.1 seconds
Started Aug 27 03:04:34 PM UTC 24
Finished Aug 27 03:04:41 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200996392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.4200996392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.1383490031
Short name T494
Test name
Test status
Simulation time 1849446851 ps
CPU time 5.72 seconds
Started Aug 27 03:04:30 PM UTC 24
Finished Aug 27 03:04:37 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383490031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1383490031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.1070633413
Short name T935
Test name
Test status
Simulation time 421667160 ps
CPU time 10.72 seconds
Started Aug 27 03:10:38 PM UTC 24
Finished Aug 27 03:10:50 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070633413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1070633413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.1966923400
Short name T918
Test name
Test status
Simulation time 1756255524 ps
CPU time 5.56 seconds
Started Aug 27 03:10:38 PM UTC 24
Finished Aug 27 03:10:44 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966923400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1966923400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.2798163174
Short name T963
Test name
Test status
Simulation time 8032183412 ps
CPU time 24.25 seconds
Started Aug 27 03:10:38 PM UTC 24
Finished Aug 27 03:11:04 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798163174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2798163174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.544411992
Short name T920
Test name
Test status
Simulation time 155521650 ps
CPU time 5.94 seconds
Started Aug 27 03:10:38 PM UTC 24
Finished Aug 27 03:10:45 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544411992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.544411992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.3484528141
Short name T362
Test name
Test status
Simulation time 297599158 ps
CPU time 7.24 seconds
Started Aug 27 03:10:41 PM UTC 24
Finished Aug 27 03:10:50 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484528141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3484528141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.1549060178
Short name T928
Test name
Test status
Simulation time 2285592306 ps
CPU time 5.97 seconds
Started Aug 27 03:10:41 PM UTC 24
Finished Aug 27 03:10:48 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549060178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1549060178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.3195965595
Short name T924
Test name
Test status
Simulation time 773920933 ps
CPU time 5.2 seconds
Started Aug 27 03:10:41 PM UTC 24
Finished Aug 27 03:10:48 PM UTC 24
Peak memory 257260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195965595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3195965595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.421166595
Short name T926
Test name
Test status
Simulation time 144246113 ps
CPU time 5.3 seconds
Started Aug 27 03:10:41 PM UTC 24
Finished Aug 27 03:10:48 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421166595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.421166595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.3616270985
Short name T936
Test name
Test status
Simulation time 762565113 ps
CPU time 7.86 seconds
Started Aug 27 03:10:41 PM UTC 24
Finished Aug 27 03:10:50 PM UTC 24
Peak memory 257336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616270985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3616270985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.1865413371
Short name T929
Test name
Test status
Simulation time 243783333 ps
CPU time 3.78 seconds
Started Aug 27 03:10:43 PM UTC 24
Finished Aug 27 03:10:48 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865413371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1865413371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.4074416612
Short name T938
Test name
Test status
Simulation time 323766891 ps
CPU time 8.18 seconds
Started Aug 27 03:10:43 PM UTC 24
Finished Aug 27 03:10:53 PM UTC 24
Peak memory 251080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074416612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.4074416612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.2124268928
Short name T932
Test name
Test status
Simulation time 488085927 ps
CPU time 4.53 seconds
Started Aug 27 03:10:43 PM UTC 24
Finished Aug 27 03:10:49 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124268928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2124268928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.462820703
Short name T934
Test name
Test status
Simulation time 147268145 ps
CPU time 4.7 seconds
Started Aug 27 03:10:44 PM UTC 24
Finished Aug 27 03:10:49 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462820703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.462820703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.1171809447
Short name T930
Test name
Test status
Simulation time 504823697 ps
CPU time 3.77 seconds
Started Aug 27 03:10:44 PM UTC 24
Finished Aug 27 03:10:49 PM UTC 24
Peak memory 251064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171809447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1171809447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.3200185552
Short name T941
Test name
Test status
Simulation time 1027777095 ps
CPU time 11.36 seconds
Started Aug 27 03:10:44 PM UTC 24
Finished Aug 27 03:10:56 PM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200185552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3200185552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.3792859753
Short name T933
Test name
Test status
Simulation time 247876887 ps
CPU time 4.22 seconds
Started Aug 27 03:10:44 PM UTC 24
Finished Aug 27 03:10:49 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792859753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3792859753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.505100547
Short name T86
Test name
Test status
Simulation time 142518322 ps
CPU time 4.58 seconds
Started Aug 27 03:10:44 PM UTC 24
Finished Aug 27 03:10:50 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505100547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.505100547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.1819082664
Short name T937
Test name
Test status
Simulation time 96021027 ps
CPU time 4.55 seconds
Started Aug 27 03:10:46 PM UTC 24
Finished Aug 27 03:10:51 PM UTC 24
Peak memory 251044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819082664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1819082664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.3147738069
Short name T323
Test name
Test status
Simulation time 171066398 ps
CPU time 1.57 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:04:46 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147738069 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.3147738069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.2295906877
Short name T82
Test name
Test status
Simulation time 2494407467 ps
CPU time 15.22 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:56 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295906877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2295906877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.1474913123
Short name T403
Test name
Test status
Simulation time 1101094649 ps
CPU time 17.37 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:58 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474913123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1474913123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.2061755681
Short name T371
Test name
Test status
Simulation time 1263167356 ps
CPU time 21.31 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:05:02 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061755681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2061755681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1324754852
Short name T182
Test name
Test status
Simulation time 414446723 ps
CPU time 3.95 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:44 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324754852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1324754852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.1113611690
Short name T188
Test name
Test status
Simulation time 112886961 ps
CPU time 3.28 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:44 PM UTC 24
Peak memory 257400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113611690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.1113611690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.1563532247
Short name T372
Test name
Test status
Simulation time 2809539489 ps
CPU time 21.01 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:05:02 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563532247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1563532247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.627088904
Short name T483
Test name
Test status
Simulation time 4847362439 ps
CPU time 13.59 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:54 PM UTC 24
Peak memory 251244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627088904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.627088904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.1114292844
Short name T328
Test name
Test status
Simulation time 587326794 ps
CPU time 10.92 seconds
Started Aug 27 03:04:39 PM UTC 24
Finished Aug 27 03:04:51 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114292844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1114292844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.4015051289
Short name T326
Test name
Test status
Simulation time 127394175 ps
CPU time 5.38 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:04:50 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015051289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.4015051289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.3119943070
Short name T708
Test name
Test status
Simulation time 35741370283 ps
CPU time 206.95 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:08:13 PM UTC 24
Peak memory 273980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119943070 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.3119943070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.282027871
Short name T449
Test name
Test status
Simulation time 19113473769 ps
CPU time 186.23 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:07:52 PM UTC 24
Peak memory 274012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=282027871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
12.otp_ctrl_stress_all_with_rand_reset.282027871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.1440278090
Short name T324
Test name
Test status
Simulation time 437064085 ps
CPU time 4.31 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:04:49 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440278090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1440278090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.258021944
Short name T939
Test name
Test status
Simulation time 2035252030 ps
CPU time 6.13 seconds
Started Aug 27 03:10:46 PM UTC 24
Finished Aug 27 03:10:53 PM UTC 24
Peak memory 250860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258021944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.258021944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.1609899223
Short name T945
Test name
Test status
Simulation time 434328201 ps
CPU time 10.28 seconds
Started Aug 27 03:10:46 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609899223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.1609899223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.760522243
Short name T43
Test name
Test status
Simulation time 525490924 ps
CPU time 3.47 seconds
Started Aug 27 03:10:46 PM UTC 24
Finished Aug 27 03:10:50 PM UTC 24
Peak memory 251404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760522243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.760522243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.2688636042
Short name T168
Test name
Test status
Simulation time 341972668 ps
CPU time 7.92 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:01 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688636042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2688636042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.2588325496
Short name T947
Test name
Test status
Simulation time 521050035 ps
CPU time 4.88 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588325496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2588325496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.115181907
Short name T940
Test name
Test status
Simulation time 311229887 ps
CPU time 2.7 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:56 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115181907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.115181907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.3874448664
Short name T943
Test name
Test status
Simulation time 96648479 ps
CPU time 3.79 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874448664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3874448664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.2980300283
Short name T922
Test name
Test status
Simulation time 521528961 ps
CPU time 7.71 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:01 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980300283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2980300283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.3997403369
Short name T54
Test name
Test status
Simulation time 180090957 ps
CPU time 4.3 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997403369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3997403369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.3507511864
Short name T958
Test name
Test status
Simulation time 2426828056 ps
CPU time 7.75 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:01 PM UTC 24
Peak memory 257372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507511864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3507511864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.1999962769
Short name T921
Test name
Test status
Simulation time 1630949715 ps
CPU time 7.39 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:00 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999962769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1999962769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.1357835218
Short name T949
Test name
Test status
Simulation time 142778967 ps
CPU time 4.92 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357835218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1357835218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.164758784
Short name T944
Test name
Test status
Simulation time 423963906 ps
CPU time 3.93 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164758784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.164758784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.2530462321
Short name T954
Test name
Test status
Simulation time 451426138 ps
CPU time 5.4 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:59 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530462321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2530462321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.1932266599
Short name T952
Test name
Test status
Simulation time 416401801 ps
CPU time 5.47 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:59 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932266599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1932266599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.3034323859
Short name T942
Test name
Test status
Simulation time 150687239 ps
CPU time 3.38 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034323859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3034323859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.3154173761
Short name T957
Test name
Test status
Simulation time 278386341 ps
CPU time 7.26 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:01 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154173761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3154173761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.2142452284
Short name T950
Test name
Test status
Simulation time 168873095 ps
CPU time 4.89 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142452284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2142452284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.343234559
Short name T996
Test name
Test status
Simulation time 1023772155 ps
CPU time 22.77 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:17 PM UTC 24
Peak memory 250700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343234559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.343234559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1763935228
Short name T498
Test name
Test status
Simulation time 50633810 ps
CPU time 2.23 seconds
Started Aug 27 03:04:50 PM UTC 24
Finished Aug 27 03:04:54 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763935228 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1763935228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.1953440799
Short name T497
Test name
Test status
Simulation time 200606626 ps
CPU time 4.29 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:04:54 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953440799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1953440799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3580601229
Short name T147
Test name
Test status
Simulation time 3123619675 ps
CPU time 44.9 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:05:35 PM UTC 24
Peak memory 263456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580601229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3580601229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.1070307631
Short name T438
Test name
Test status
Simulation time 831716003 ps
CPU time 16.92 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:05:07 PM UTC 24
Peak memory 257452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070307631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1070307631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.1917486414
Short name T63
Test name
Test status
Simulation time 2120499574 ps
CPU time 9.65 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:04:54 PM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917486414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.1917486414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.4019419547
Short name T222
Test name
Test status
Simulation time 18522724749 ps
CPU time 182.79 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:07:54 PM UTC 24
Peak memory 257632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019419547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.4019419547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.805726705
Short name T369
Test name
Test status
Simulation time 6446802622 ps
CPU time 11.72 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:05:01 PM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805726705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.805726705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.1413523913
Short name T294
Test name
Test status
Simulation time 567503218 ps
CPU time 4.21 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:04:54 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413523913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1413523913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.330658807
Short name T440
Test name
Test status
Simulation time 10761118095 ps
CPU time 26.99 seconds
Started Aug 27 03:04:43 PM UTC 24
Finished Aug 27 03:05:12 PM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330658807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.330658807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.3055765161
Short name T499
Test name
Test status
Simulation time 297003147 ps
CPU time 6.01 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:04:56 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055765161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3055765161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.292085126
Short name T450
Test name
Test status
Simulation time 28748684169 ps
CPU time 190.31 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:08:02 PM UTC 24
Peak memory 302680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292085126 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.292085126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.4043897392
Short name T321
Test name
Test status
Simulation time 14805174930 ps
CPU time 80.91 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:06:11 PM UTC 24
Peak memory 257672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4043897392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.otp_ctrl_stress_all_with_rand_reset.4043897392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.1171241146
Short name T434
Test name
Test status
Simulation time 7202846264 ps
CPU time 22.85 seconds
Started Aug 27 03:04:48 PM UTC 24
Finished Aug 27 03:05:13 PM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171241146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1171241146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.634919350
Short name T948
Test name
Test status
Simulation time 1663527395 ps
CPU time 3.89 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634919350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.634919350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.4294470900
Short name T978
Test name
Test status
Simulation time 3525509662 ps
CPU time 17.33 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:11:11 PM UTC 24
Peak memory 251240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294470900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.4294470900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1711490024
Short name T955
Test name
Test status
Simulation time 312022773 ps
CPU time 5.31 seconds
Started Aug 27 03:10:52 PM UTC 24
Finished Aug 27 03:10:59 PM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711490024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1711490024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.31811417
Short name T889
Test name
Test status
Simulation time 2457290942 ps
CPU time 7.09 seconds
Started Aug 27 03:10:53 PM UTC 24
Finished Aug 27 03:11:01 PM UTC 24
Peak memory 251244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31811417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.31811417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.1656895613
Short name T951
Test name
Test status
Simulation time 142044512 ps
CPU time 4.74 seconds
Started Aug 27 03:10:53 PM UTC 24
Finished Aug 27 03:10:59 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656895613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1656895613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.1614812805
Short name T962
Test name
Test status
Simulation time 335947050 ps
CPU time 7.92 seconds
Started Aug 27 03:10:54 PM UTC 24
Finished Aug 27 03:11:03 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614812805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1614812805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.1018329588
Short name T959
Test name
Test status
Simulation time 1990623592 ps
CPU time 5.81 seconds
Started Aug 27 03:10:54 PM UTC 24
Finished Aug 27 03:11:01 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018329588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1018329588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.1472103959
Short name T907
Test name
Test status
Simulation time 197296909 ps
CPU time 5.13 seconds
Started Aug 27 03:10:54 PM UTC 24
Finished Aug 27 03:11:00 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472103959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1472103959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.1744757095
Short name T960
Test name
Test status
Simulation time 2344282930 ps
CPU time 5.17 seconds
Started Aug 27 03:10:56 PM UTC 24
Finished Aug 27 03:11:03 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744757095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1744757095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.2700045461
Short name T961
Test name
Test status
Simulation time 141424418 ps
CPU time 2.4 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:03 PM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700045461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2700045461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.3601723975
Short name T973
Test name
Test status
Simulation time 1856947175 ps
CPU time 6.3 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:07 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601723975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3601723975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.1013700576
Short name T972
Test name
Test status
Simulation time 240949992 ps
CPU time 5.54 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:06 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013700576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1013700576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.390846795
Short name T964
Test name
Test status
Simulation time 241342264 ps
CPU time 3.32 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:04 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390846795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.390846795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.3684460066
Short name T969
Test name
Test status
Simulation time 704576678 ps
CPU time 4.37 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:05 PM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684460066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.3684460066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.2336349937
Short name T967
Test name
Test status
Simulation time 533639915 ps
CPU time 3.97 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:05 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336349937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2336349937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.3744473727
Short name T966
Test name
Test status
Simulation time 149519686 ps
CPU time 3.92 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:05 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744473727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3744473727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.3367780690
Short name T974
Test name
Test status
Simulation time 2658167460 ps
CPU time 6.26 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:07 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367780690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3367780690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.3572321894
Short name T247
Test name
Test status
Simulation time 1050356293 ps
CPU time 12.96 seconds
Started Aug 27 03:10:59 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572321894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3572321894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.2832142423
Short name T968
Test name
Test status
Simulation time 143102454 ps
CPU time 3.95 seconds
Started Aug 27 03:11:00 PM UTC 24
Finished Aug 27 03:11:05 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832142423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2832142423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.2114098252
Short name T971
Test name
Test status
Simulation time 358855916 ps
CPU time 4.96 seconds
Started Aug 27 03:11:00 PM UTC 24
Finished Aug 27 03:11:06 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114098252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2114098252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.848714047
Short name T370
Test name
Test status
Simulation time 108406735 ps
CPU time 2.68 seconds
Started Aug 27 03:04:57 PM UTC 24
Finished Aug 27 03:05:02 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848714047 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.848714047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.1437577478
Short name T503
Test name
Test status
Simulation time 555369784 ps
CPU time 5.5 seconds
Started Aug 27 03:04:53 PM UTC 24
Finished Aug 27 03:05:00 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437577478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1437577478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.3277704097
Short name T373
Test name
Test status
Simulation time 622903680 ps
CPU time 8.86 seconds
Started Aug 27 03:04:53 PM UTC 24
Finished Aug 27 03:05:03 PM UTC 24
Peak memory 251072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277704097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3277704097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.791956789
Short name T524
Test name
Test status
Simulation time 2834596655 ps
CPU time 36.3 seconds
Started Aug 27 03:04:51 PM UTC 24
Finished Aug 27 03:05:28 PM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791956789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.791956789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1841492387
Short name T235
Test name
Test status
Simulation time 13724526096 ps
CPU time 31.04 seconds
Started Aug 27 03:04:55 PM UTC 24
Finished Aug 27 03:05:27 PM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841492387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1841492387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.92572958
Short name T266
Test name
Test status
Simulation time 1912890066 ps
CPU time 15.89 seconds
Started Aug 27 03:04:55 PM UTC 24
Finished Aug 27 03:05:12 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92572958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.92572958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.1242015795
Short name T101
Test name
Test status
Simulation time 493160454 ps
CPU time 6.42 seconds
Started Aug 27 03:04:51 PM UTC 24
Finished Aug 27 03:04:58 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242015795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1242015795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.21028771
Short name T437
Test name
Test status
Simulation time 531950582 ps
CPU time 13.27 seconds
Started Aug 27 03:04:50 PM UTC 24
Finished Aug 27 03:05:05 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21028771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.21028771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.730727344
Short name T506
Test name
Test status
Simulation time 4417364543 ps
CPU time 13.51 seconds
Started Aug 27 03:04:55 PM UTC 24
Finished Aug 27 03:05:10 PM UTC 24
Peak memory 251244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730727344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.730727344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.3530801549
Short name T502
Test name
Test status
Simulation time 1773838483 ps
CPU time 5.05 seconds
Started Aug 27 03:04:50 PM UTC 24
Finished Aug 27 03:04:57 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530801549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3530801549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2202037692
Short name T1101
Test name
Test status
Simulation time 137134343681 ps
CPU time 405.18 seconds
Started Aug 27 03:04:55 PM UTC 24
Finished Aug 27 03:11:46 PM UTC 24
Peak memory 275788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202037692 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2202037692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.3760965678
Short name T25
Test name
Test status
Simulation time 3974633320 ps
CPU time 52.28 seconds
Started Aug 27 03:04:55 PM UTC 24
Finished Aug 27 03:05:49 PM UTC 24
Peak memory 257756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3760965678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.otp_ctrl_stress_all_with_rand_reset.3760965678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.3728094043
Short name T472
Test name
Test status
Simulation time 2158007025 ps
CPU time 18.03 seconds
Started Aug 27 03:04:55 PM UTC 24
Finished Aug 27 03:05:14 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728094043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3728094043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.2290051477
Short name T965
Test name
Test status
Simulation time 293790358 ps
CPU time 3.13 seconds
Started Aug 27 03:11:00 PM UTC 24
Finished Aug 27 03:11:04 PM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290051477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2290051477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.922701322
Short name T975
Test name
Test status
Simulation time 401081009 ps
CPU time 8.31 seconds
Started Aug 27 03:11:00 PM UTC 24
Finished Aug 27 03:11:09 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922701322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.922701322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.223522229
Short name T976
Test name
Test status
Simulation time 137813206 ps
CPU time 3.16 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:11 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223522229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.223522229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.3695402083
Short name T1027
Test name
Test status
Simulation time 1959046447 ps
CPU time 19.59 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695402083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3695402083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3698627742
Short name T977
Test name
Test status
Simulation time 210715625 ps
CPU time 3.26 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:11 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698627742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3698627742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.1774600987
Short name T1075
Test name
Test status
Simulation time 1340910318 ps
CPU time 30.78 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:39 PM UTC 24
Peak memory 253304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774600987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1774600987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.723519789
Short name T985
Test name
Test status
Simulation time 406780744 ps
CPU time 4.66 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723519789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.723519789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.3616273200
Short name T363
Test name
Test status
Simulation time 392985736 ps
CPU time 4.54 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616273200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3616273200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.1584836770
Short name T1008
Test name
Test status
Simulation time 487413028 ps
CPU time 12.14 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:20 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584836770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1584836770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.908851372
Short name T32
Test name
Test status
Simulation time 543762846 ps
CPU time 5.58 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908851372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.908851372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.2749720491
Short name T999
Test name
Test status
Simulation time 318021963 ps
CPU time 9.05 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:17 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749720491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2749720491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.2322775726
Short name T980
Test name
Test status
Simulation time 1561193179 ps
CPU time 3.59 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:12 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322775726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2322775726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2000813076
Short name T240
Test name
Test status
Simulation time 104777295 ps
CPU time 4.75 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000813076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2000813076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1738062468
Short name T981
Test name
Test status
Simulation time 414827043 ps
CPU time 3.84 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:12 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738062468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1738062468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.1804007406
Short name T1039
Test name
Test status
Simulation time 1775251261 ps
CPU time 23.99 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:33 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804007406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1804007406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.65995588
Short name T66
Test name
Test status
Simulation time 227817404 ps
CPU time 3.14 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:12 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65995588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.65995588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.31718199
Short name T1017
Test name
Test status
Simulation time 544395437 ps
CPU time 13.33 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:22 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31718199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.31718199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.896535932
Short name T987
Test name
Test status
Simulation time 329735997 ps
CPU time 4.47 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896535932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.896535932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.2324625862
Short name T241
Test name
Test status
Simulation time 102839463 ps
CPU time 4.48 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324625862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2324625862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.783319417
Short name T374
Test name
Test status
Simulation time 1027757932 ps
CPU time 2.07 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:05:04 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783319417 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.783319417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.3319428854
Short name T443
Test name
Test status
Simulation time 28543813799 ps
CPU time 33.62 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:33 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319428854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3319428854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.945287009
Short name T526
Test name
Test status
Simulation time 5381541003 ps
CPU time 31.87 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:31 PM UTC 24
Peak memory 257532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945287009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.945287009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.40655594
Short name T531
Test name
Test status
Simulation time 2617502934 ps
CPU time 35.01 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:34 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40655594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.40655594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.2167844337
Short name T65
Test name
Test status
Simulation time 668164508 ps
CPU time 4.82 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:04 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167844337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2167844337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.211906527
Short name T510
Test name
Test status
Simulation time 6014405197 ps
CPU time 12.14 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:05:14 PM UTC 24
Peak memory 253532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211906527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.211906527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.3977150017
Short name T442
Test name
Test status
Simulation time 5204227864 ps
CPU time 21.72 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:05:24 PM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977150017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3977150017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.2004558704
Short name T231
Test name
Test status
Simulation time 314434852 ps
CPU time 6.56 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:06 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004558704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2004558704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.3781027918
Short name T504
Test name
Test status
Simulation time 836840431 ps
CPU time 7.77 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:07 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781027918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3781027918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.1464981703
Short name T426
Test name
Test status
Simulation time 874529283 ps
CPU time 7.69 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:05:10 PM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464981703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1464981703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.1697332893
Short name T505
Test name
Test status
Simulation time 301817568 ps
CPU time 8.82 seconds
Started Aug 27 03:04:58 PM UTC 24
Finished Aug 27 03:05:08 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697332893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1697332893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.409996386
Short name T471
Test name
Test status
Simulation time 1340758129 ps
CPU time 8.34 seconds
Started Aug 27 03:05:01 PM UTC 24
Finished Aug 27 03:05:11 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409996386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.409996386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.22374098
Short name T984
Test name
Test status
Simulation time 2547805157 ps
CPU time 3.99 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22374098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.22374098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.1610099599
Short name T989
Test name
Test status
Simulation time 861256524 ps
CPU time 13.6 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:22 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610099599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1610099599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.4239991167
Short name T983
Test name
Test status
Simulation time 453511618 ps
CPU time 3.94 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239991167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.4239991167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.3877333550
Short name T1002
Test name
Test status
Simulation time 625001252 ps
CPU time 10.32 seconds
Started Aug 27 03:11:07 PM UTC 24
Finished Aug 27 03:11:19 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877333550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3877333550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.4093474492
Short name T242
Test name
Test status
Simulation time 1737126939 ps
CPU time 4.76 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093474492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.4093474492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.1464191331
Short name T244
Test name
Test status
Simulation time 457450906 ps
CPU time 4.91 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464191331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1464191331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.978718722
Short name T246
Test name
Test status
Simulation time 287036223 ps
CPU time 4.94 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978718722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.978718722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.2380712894
Short name T1000
Test name
Test status
Simulation time 363754227 ps
CPU time 9.2 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:18 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380712894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2380712894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.101429033
Short name T982
Test name
Test status
Simulation time 114522771 ps
CPU time 3.34 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:12 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101429033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.101429033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.2880591211
Short name T992
Test name
Test status
Simulation time 1735164414 ps
CPU time 5.5 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880591211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2880591211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.577162976
Short name T986
Test name
Test status
Simulation time 145826043 ps
CPU time 3.89 seconds
Started Aug 27 03:11:08 PM UTC 24
Finished Aug 27 03:11:13 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577162976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.577162976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.4148100479
Short name T997
Test name
Test status
Simulation time 285579815 ps
CPU time 6.4 seconds
Started Aug 27 03:11:09 PM UTC 24
Finished Aug 27 03:11:17 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148100479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.4148100479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.2873477748
Short name T245
Test name
Test status
Simulation time 299497961 ps
CPU time 3.34 seconds
Started Aug 27 03:11:09 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873477748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2873477748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.136654705
Short name T1052
Test name
Test status
Simulation time 3620649327 ps
CPU time 23.91 seconds
Started Aug 27 03:11:09 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136654705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.136654705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.4274234319
Short name T995
Test name
Test status
Simulation time 583462239 ps
CPU time 4.03 seconds
Started Aug 27 03:11:11 PM UTC 24
Finished Aug 27 03:11:16 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274234319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.4274234319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.2576016884
Short name T1001
Test name
Test status
Simulation time 735675790 ps
CPU time 5.39 seconds
Started Aug 27 03:11:13 PM UTC 24
Finished Aug 27 03:11:19 PM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576016884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2576016884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.919294373
Short name T1003
Test name
Test status
Simulation time 2093513423 ps
CPU time 5.89 seconds
Started Aug 27 03:11:13 PM UTC 24
Finished Aug 27 03:11:19 PM UTC 24
Peak memory 251136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919294373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.919294373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.642438767
Short name T1009
Test name
Test status
Simulation time 947170944 ps
CPU time 6.96 seconds
Started Aug 27 03:11:13 PM UTC 24
Finished Aug 27 03:11:21 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642438767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.642438767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.2677010698
Short name T1064
Test name
Test status
Simulation time 1230045835 ps
CPU time 22.9 seconds
Started Aug 27 03:11:13 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677010698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2677010698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.3325352447
Short name T507
Test name
Test status
Simulation time 45949559 ps
CPU time 1.78 seconds
Started Aug 27 03:05:09 PM UTC 24
Finished Aug 27 03:05:11 PM UTC 24
Peak memory 251212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325352447 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3325352447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.162803299
Short name T71
Test name
Test status
Simulation time 1305404276 ps
CPU time 16.77 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:23 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162803299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.162803299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1526669753
Short name T404
Test name
Test status
Simulation time 578761413 ps
CPU time 19.19 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:25 PM UTC 24
Peak memory 250928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526669753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1526669753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.3821167000
Short name T518
Test name
Test status
Simulation time 2134043445 ps
CPU time 18.6 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:24 PM UTC 24
Peak memory 251036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821167000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3821167000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2086304480
Short name T52
Test name
Test status
Simulation time 723478912 ps
CPU time 6.36 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:12 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086304480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2086304480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.2751796817
Short name T517
Test name
Test status
Simulation time 8289056577 ps
CPU time 16.92 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:23 PM UTC 24
Peak memory 255580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751796817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2751796817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.1669650095
Short name T519
Test name
Test status
Simulation time 2394979213 ps
CPU time 17.51 seconds
Started Aug 27 03:05:06 PM UTC 24
Finished Aug 27 03:05:25 PM UTC 24
Peak memory 257452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669650095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.1669650095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.1895417742
Short name T232
Test name
Test status
Simulation time 287546231 ps
CPU time 5.32 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:11 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895417742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.1895417742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.3125573712
Short name T514
Test name
Test status
Simulation time 2010539353 ps
CPU time 14.38 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:20 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125573712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3125573712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.700338395
Short name T509
Test name
Test status
Simulation time 157666116 ps
CPU time 6.61 seconds
Started Aug 27 03:05:06 PM UTC 24
Finished Aug 27 03:05:14 PM UTC 24
Peak memory 251372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700338395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.700338395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.162101571
Short name T508
Test name
Test status
Simulation time 1278681011 ps
CPU time 7.38 seconds
Started Aug 27 03:05:04 PM UTC 24
Finished Aug 27 03:05:13 PM UTC 24
Peak memory 251680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162101571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.162101571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.560950772
Short name T398
Test name
Test status
Simulation time 672967191 ps
CPU time 16.56 seconds
Started Aug 27 03:05:09 PM UTC 24
Finished Aug 27 03:05:26 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560950772 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.560950772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.968760564
Short name T441
Test name
Test status
Simulation time 1148300883 ps
CPU time 18.78 seconds
Started Aug 27 03:05:06 PM UTC 24
Finished Aug 27 03:05:26 PM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968760564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.968760564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.4107509961
Short name T79
Test name
Test status
Simulation time 2204826674 ps
CPU time 5.51 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:22 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107509961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4107509961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1010160413
Short name T1023
Test name
Test status
Simulation time 1284844658 ps
CPU time 10.61 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:27 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010160413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1010160413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.801603093
Short name T1012
Test name
Test status
Simulation time 567162322 ps
CPU time 4.38 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:21 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801603093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.801603093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.3079285672
Short name T1062
Test name
Test status
Simulation time 1865067959 ps
CPU time 18.9 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079285672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3079285672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.223186257
Short name T1018
Test name
Test status
Simulation time 2711207711 ps
CPU time 6.61 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:23 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223186257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.223186257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.4151004304
Short name T1042
Test name
Test status
Simulation time 7591030247 ps
CPU time 16.77 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:33 PM UTC 24
Peak memory 251240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151004304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.4151004304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.4129238430
Short name T1007
Test name
Test status
Simulation time 230908121 ps
CPU time 3.99 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:20 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129238430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.4129238430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.3846801152
Short name T1011
Test name
Test status
Simulation time 1909875782 ps
CPU time 4 seconds
Started Aug 27 03:11:15 PM UTC 24
Finished Aug 27 03:11:21 PM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846801152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3846801152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.2213486112
Short name T1040
Test name
Test status
Simulation time 3640281444 ps
CPU time 16.05 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:33 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213486112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2213486112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.997948719
Short name T1014
Test name
Test status
Simulation time 226528576 ps
CPU time 4.76 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:21 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997948719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.997948719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3144315510
Short name T1004
Test name
Test status
Simulation time 215012005 ps
CPU time 3.24 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:20 PM UTC 24
Peak memory 253236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144315510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3144315510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.3159455461
Short name T1005
Test name
Test status
Simulation time 125903726 ps
CPU time 3.4 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:20 PM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159455461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3159455461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1306095366
Short name T1013
Test name
Test status
Simulation time 165583693 ps
CPU time 4.35 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:21 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306095366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1306095366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.2095016312
Short name T988
Test name
Test status
Simulation time 448529198 ps
CPU time 5 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:22 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095016312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2095016312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.733682325
Short name T1035
Test name
Test status
Simulation time 3381743832 ps
CPU time 12.7 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733682325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.733682325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.1271334159
Short name T1010
Test name
Test status
Simulation time 248108051 ps
CPU time 3.58 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:21 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271334159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1271334159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.952236674
Short name T1030
Test name
Test status
Simulation time 865365624 ps
CPU time 11.74 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:29 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952236674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.952236674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.2146705343
Short name T1016
Test name
Test status
Simulation time 2435289420 ps
CPU time 4.66 seconds
Started Aug 27 03:11:16 PM UTC 24
Finished Aug 27 03:11:22 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146705343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2146705343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.2301947311
Short name T993
Test name
Test status
Simulation time 100391800 ps
CPU time 3.64 seconds
Started Aug 27 03:11:21 PM UTC 24
Finished Aug 27 03:11:26 PM UTC 24
Peak memory 251100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301947311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2301947311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.4097115569
Short name T512
Test name
Test status
Simulation time 46987096 ps
CPU time 2.49 seconds
Started Aug 27 03:05:15 PM UTC 24
Finished Aug 27 03:05:18 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097115569 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4097115569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.1076820564
Short name T511
Test name
Test status
Simulation time 655505503 ps
CPU time 5.47 seconds
Started Aug 27 03:05:11 PM UTC 24
Finished Aug 27 03:05:18 PM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076820564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1076820564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.484780585
Short name T535
Test name
Test status
Simulation time 1029626864 ps
CPU time 26.85 seconds
Started Aug 27 03:05:11 PM UTC 24
Finished Aug 27 03:05:39 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484780585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.484780585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.877229689
Short name T267
Test name
Test status
Simulation time 1008337082 ps
CPU time 19.45 seconds
Started Aug 27 03:05:11 PM UTC 24
Finished Aug 27 03:05:32 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877229689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.877229689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.3823397222
Short name T181
Test name
Test status
Simulation time 127153725 ps
CPU time 3.76 seconds
Started Aug 27 03:05:09 PM UTC 24
Finished Aug 27 03:05:14 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823397222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3823397222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.2278309507
Short name T516
Test name
Test status
Simulation time 394517891 ps
CPU time 6.48 seconds
Started Aug 27 03:05:14 PM UTC 24
Finished Aug 27 03:05:22 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278309507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2278309507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.1010047875
Short name T401
Test name
Test status
Simulation time 153750807 ps
CPU time 5.45 seconds
Started Aug 27 03:05:11 PM UTC 24
Finished Aug 27 03:05:18 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010047875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1010047875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.411047855
Short name T515
Test name
Test status
Simulation time 1841068218 ps
CPU time 7.68 seconds
Started Aug 27 03:05:11 PM UTC 24
Finished Aug 27 03:05:20 PM UTC 24
Peak memory 257300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411047855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.411047855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.456574439
Short name T520
Test name
Test status
Simulation time 934476165 ps
CPU time 9.21 seconds
Started Aug 27 03:05:14 PM UTC 24
Finished Aug 27 03:05:25 PM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456574439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.456574439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.333293633
Short name T513
Test name
Test status
Simulation time 747152122 ps
CPU time 9.67 seconds
Started Aug 27 03:05:09 PM UTC 24
Finished Aug 27 03:05:19 PM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333293633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.333293633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3788161425
Short name T430
Test name
Test status
Simulation time 24671075462 ps
CPU time 172.46 seconds
Started Aug 27 03:05:14 PM UTC 24
Finished Aug 27 03:08:10 PM UTC 24
Peak memory 257624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788161425 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.3788161425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.4189707221
Short name T16
Test name
Test status
Simulation time 898151095 ps
CPU time 15.68 seconds
Started Aug 27 03:05:14 PM UTC 24
Finished Aug 27 03:05:31 PM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4189707221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.otp_ctrl_stress_all_with_rand_reset.4189707221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.4016405650
Short name T565
Test name
Test status
Simulation time 12030878210 ps
CPU time 60.07 seconds
Started Aug 27 03:05:14 PM UTC 24
Finished Aug 27 03:06:16 PM UTC 24
Peak memory 251632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016405650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.4016405650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.1283479545
Short name T1025
Test name
Test status
Simulation time 149269891 ps
CPU time 5.02 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283479545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1283479545
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.2320780088
Short name T1031
Test name
Test status
Simulation time 1045811196 ps
CPU time 6.32 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:29 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320780088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2320780088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.1041760687
Short name T1022
Test name
Test status
Simulation time 315763141 ps
CPU time 4.14 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:27 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041760687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.1041760687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.170814489
Short name T1049
Test name
Test status
Simulation time 841996937 ps
CPU time 11.33 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170814489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.170814489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.387851197
Short name T1021
Test name
Test status
Simulation time 315972870 ps
CPU time 3.96 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:27 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387851197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.387851197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1772834400
Short name T1033
Test name
Test status
Simulation time 314580437 ps
CPU time 6.58 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:29 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772834400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1772834400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.3072433165
Short name T152
Test name
Test status
Simulation time 246767080 ps
CPU time 6.46 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:29 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072433165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3072433165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.2091100095
Short name T990
Test name
Test status
Simulation time 310079090 ps
CPU time 3.4 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:26 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091100095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2091100095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.673048546
Short name T1079
Test name
Test status
Simulation time 6520159159 ps
CPU time 17.07 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673048546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.673048546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.2425395360
Short name T1034
Test name
Test status
Simulation time 1512508100 ps
CPU time 6.47 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:30 PM UTC 24
Peak memory 250956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425395360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2425395360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.1629392638
Short name T1037
Test name
Test status
Simulation time 3522429738 ps
CPU time 8.64 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:32 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629392638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.1629392638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.3546102225
Short name T1019
Test name
Test status
Simulation time 179125061 ps
CPU time 3.64 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:27 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546102225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3546102225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.115985453
Short name T1066
Test name
Test status
Simulation time 966426338 ps
CPU time 13.91 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115985453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.115985453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.1311856373
Short name T80
Test name
Test status
Simulation time 2221969353 ps
CPU time 4 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:27 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311856373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1311856373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.1461880302
Short name T1024
Test name
Test status
Simulation time 177163358 ps
CPU time 4.34 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461880302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1461880302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.3462337583
Short name T1036
Test name
Test status
Simulation time 197539659 ps
CPU time 8.01 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:31 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462337583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3462337583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.4075426363
Short name T1029
Test name
Test status
Simulation time 249414855 ps
CPU time 4.63 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075426363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4075426363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.1942284100
Short name T1020
Test name
Test status
Simulation time 1164829614 ps
CPU time 3.33 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:27 PM UTC 24
Peak memory 257248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942284100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1942284100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.3458235844
Short name T523
Test name
Test status
Simulation time 660396444 ps
CPU time 3.15 seconds
Started Aug 27 03:05:24 PM UTC 24
Finished Aug 27 03:05:28 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458235844 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3458235844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.1929234674
Short name T125
Test name
Test status
Simulation time 343271219 ps
CPU time 4.16 seconds
Started Aug 27 03:05:19 PM UTC 24
Finished Aug 27 03:05:25 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929234674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1929234674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.3982137118
Short name T258
Test name
Test status
Simulation time 2640909978 ps
CPU time 39.13 seconds
Started Aug 27 03:05:18 PM UTC 24
Finished Aug 27 03:05:59 PM UTC 24
Peak memory 259452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982137118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3982137118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.724367023
Short name T525
Test name
Test status
Simulation time 652233837 ps
CPU time 9.98 seconds
Started Aug 27 03:05:18 PM UTC 24
Finished Aug 27 03:05:29 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724367023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.724367023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.3912472596
Short name T31
Test name
Test status
Simulation time 192358241 ps
CPU time 5.03 seconds
Started Aug 27 03:05:15 PM UTC 24
Finished Aug 27 03:05:21 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912472596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3912472596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.1840181105
Short name T217
Test name
Test status
Simulation time 1465424684 ps
CPU time 14.59 seconds
Started Aug 27 03:05:21 PM UTC 24
Finished Aug 27 03:05:37 PM UTC 24
Peak memory 255448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840181105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1840181105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.3360971534
Short name T539
Test name
Test status
Simulation time 3556545319 ps
CPU time 20.03 seconds
Started Aug 27 03:05:21 PM UTC 24
Finished Aug 27 03:05:42 PM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360971534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3360971534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.1353011887
Short name T286
Test name
Test status
Simulation time 578275717 ps
CPU time 8.47 seconds
Started Aug 27 03:05:16 PM UTC 24
Finished Aug 27 03:05:26 PM UTC 24
Peak memory 251064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353011887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1353011887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.406983280
Short name T527
Test name
Test status
Simulation time 6449755177 ps
CPU time 14.63 seconds
Started Aug 27 03:05:16 PM UTC 24
Finished Aug 27 03:05:32 PM UTC 24
Peak memory 257292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406983280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.406983280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.566761575
Short name T522
Test name
Test status
Simulation time 208391761 ps
CPU time 5.86 seconds
Started Aug 27 03:05:21 PM UTC 24
Finished Aug 27 03:05:28 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566761575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.566761575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.2894846117
Short name T521
Test name
Test status
Simulation time 535727232 ps
CPU time 11.01 seconds
Started Aug 27 03:05:15 PM UTC 24
Finished Aug 27 03:05:27 PM UTC 24
Peak memory 257436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894846117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2894846117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.547466990
Short name T478
Test name
Test status
Simulation time 9061274099 ps
CPU time 64.2 seconds
Started Aug 27 03:05:24 PM UTC 24
Finished Aug 27 03:06:30 PM UTC 24
Peak memory 255512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547466990 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.547466990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1195470164
Short name T293
Test name
Test status
Simulation time 29968186199 ps
CPU time 164.79 seconds
Started Aug 27 03:05:24 PM UTC 24
Finished Aug 27 03:08:12 PM UTC 24
Peak memory 267952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1195470164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.otp_ctrl_stress_all_with_rand_reset.1195470164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.2260517786
Short name T529
Test name
Test status
Simulation time 1504715766 ps
CPU time 9.95 seconds
Started Aug 27 03:05:22 PM UTC 24
Finished Aug 27 03:05:33 PM UTC 24
Peak memory 251568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260517786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2260517786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.1920654721
Short name T1026
Test name
Test status
Simulation time 148670931 ps
CPU time 4.2 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920654721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1920654721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3556285327
Short name T1044
Test name
Test status
Simulation time 807229458 ps
CPU time 9.99 seconds
Started Aug 27 03:11:22 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556285327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3556285327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.534211431
Short name T1048
Test name
Test status
Simulation time 248196947 ps
CPU time 3.99 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534211431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.534211431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.1685394513
Short name T1065
Test name
Test status
Simulation time 295899890 ps
CPU time 6.94 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685394513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1685394513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.370778812
Short name T1046
Test name
Test status
Simulation time 227672454 ps
CPU time 3.72 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370778812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.370778812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.4157494492
Short name T1080
Test name
Test status
Simulation time 360972185 ps
CPU time 10.2 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157494492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.4157494492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.2371395078
Short name T1047
Test name
Test status
Simulation time 367198387 ps
CPU time 3.8 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371395078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2371395078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.2166211370
Short name T1054
Test name
Test status
Simulation time 189759325 ps
CPU time 4.51 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 257312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166211370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2166211370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1088722672
Short name T1041
Test name
Test status
Simulation time 174232792 ps
CPU time 3.24 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:33 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088722672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1088722672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.1933207801
Short name T1069
Test name
Test status
Simulation time 575447223 ps
CPU time 7.4 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:38 PM UTC 24
Peak memory 251132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933207801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1933207801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.3491567781
Short name T1060
Test name
Test status
Simulation time 2277888323 ps
CPU time 4.98 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491567781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3491567781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.1251320949
Short name T1045
Test name
Test status
Simulation time 131765739 ps
CPU time 3.33 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251320949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1251320949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.3425004578
Short name T1055
Test name
Test status
Simulation time 377567072 ps
CPU time 4.38 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425004578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3425004578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1697517261
Short name T1092
Test name
Test status
Simulation time 6052203066 ps
CPU time 10.91 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697517261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1697517261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.578106733
Short name T1053
Test name
Test status
Simulation time 2028132455 ps
CPU time 4.21 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578106733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.578106733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3162038831
Short name T1057
Test name
Test status
Simulation time 225776827 ps
CPU time 4.55 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162038831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3162038831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.3631369607
Short name T1051
Test name
Test status
Simulation time 509907497 ps
CPU time 3.93 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631369607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3631369607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.2112513459
Short name T1098
Test name
Test status
Simulation time 489135336 ps
CPU time 11.98 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:42 PM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112513459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2112513459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.1073304837
Short name T1059
Test name
Test status
Simulation time 2288666917 ps
CPU time 4.6 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073304837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1073304837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2790449023
Short name T165
Test name
Test status
Simulation time 335763715 ps
CPU time 6.52 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790449023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2790449023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.635417706
Short name T532
Test name
Test status
Simulation time 215285970 ps
CPU time 2.96 seconds
Started Aug 27 03:05:32 PM UTC 24
Finished Aug 27 03:05:36 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635417706 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.635417706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.944419546
Short name T448
Test name
Test status
Simulation time 644436261 ps
CPU time 12.12 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:41 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944419546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.944419546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.1506134797
Short name T549
Test name
Test status
Simulation time 1912736217 ps
CPU time 27.3 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:56 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506134797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1506134797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.1236739178
Short name T530
Test name
Test status
Simulation time 196830060 ps
CPU time 5.67 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:34 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236739178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1236739178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.708934650
Short name T55
Test name
Test status
Simulation time 1948588869 ps
CPU time 3.82 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:32 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708934650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.708934650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.322166871
Short name T540
Test name
Test status
Simulation time 2693073863 ps
CPU time 14.36 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:43 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322166871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.322166871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.3752908070
Short name T552
Test name
Test status
Simulation time 789486152 ps
CPU time 27.29 seconds
Started Aug 27 03:05:30 PM UTC 24
Finished Aug 27 03:05:58 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752908070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3752908070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.4009235441
Short name T287
Test name
Test status
Simulation time 1066055925 ps
CPU time 17.79 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:46 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009235441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.4009235441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.2504457780
Short name T551
Test name
Test status
Simulation time 8471824256 ps
CPU time 29.49 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:58 PM UTC 24
Peak memory 253656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504457780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2504457780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.3014977167
Short name T537
Test name
Test status
Simulation time 671734624 ps
CPU time 9.61 seconds
Started Aug 27 03:05:30 PM UTC 24
Finished Aug 27 03:05:40 PM UTC 24
Peak memory 251120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014977167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3014977167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.1912248812
Short name T528
Test name
Test status
Simulation time 487633227 ps
CPU time 4.85 seconds
Started Aug 27 03:05:27 PM UTC 24
Finished Aug 27 03:05:33 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912248812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1912248812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.83542241
Short name T482
Test name
Test status
Simulation time 1921689907 ps
CPU time 45.11 seconds
Started Aug 27 03:05:30 PM UTC 24
Finished Aug 27 03:06:16 PM UTC 24
Peak memory 259544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83542241 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.83542241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.3445735202
Short name T468
Test name
Test status
Simulation time 21645471796 ps
CPU time 42.94 seconds
Started Aug 27 03:05:30 PM UTC 24
Finished Aug 27 03:06:14 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445735202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3445735202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.1288239913
Short name T1058
Test name
Test status
Simulation time 499178088 ps
CPU time 4.46 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288239913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1288239913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3285741098
Short name T1056
Test name
Test status
Simulation time 307263030 ps
CPU time 4.21 seconds
Started Aug 27 03:11:29 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285741098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3285741098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.3261935374
Short name T1043
Test name
Test status
Simulation time 160518084 ps
CPU time 2.76 seconds
Started Aug 27 03:11:30 PM UTC 24
Finished Aug 27 03:11:33 PM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261935374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.3261935374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.2037549955
Short name T1050
Test name
Test status
Simulation time 392923474 ps
CPU time 3.62 seconds
Started Aug 27 03:11:30 PM UTC 24
Finished Aug 27 03:11:34 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037549955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2037549955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.2198885539
Short name T1072
Test name
Test status
Simulation time 1558252763 ps
CPU time 4.58 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:38 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198885539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2198885539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.2557156163
Short name T68
Test name
Test status
Simulation time 382544312 ps
CPU time 4.16 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557156163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2557156163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3493856217
Short name T1083
Test name
Test status
Simulation time 256015610 ps
CPU time 7.15 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493856217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3493856217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.1047696414
Short name T1077
Test name
Test status
Simulation time 2572629297 ps
CPU time 6.17 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047696414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1047696414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.617501640
Short name T1078
Test name
Test status
Simulation time 357326839 ps
CPU time 6.5 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617501640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.617501640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2841852536
Short name T1067
Test name
Test status
Simulation time 145468330 ps
CPU time 3.67 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841852536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2841852536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1435707433
Short name T1074
Test name
Test status
Simulation time 249825998 ps
CPU time 5.61 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:39 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435707433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1435707433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.1624663142
Short name T1070
Test name
Test status
Simulation time 200416890 ps
CPU time 4.22 seconds
Started Aug 27 03:11:32 PM UTC 24
Finished Aug 27 03:11:38 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624663142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1624663142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.297754656
Short name T1063
Test name
Test status
Simulation time 112851678 ps
CPU time 2.94 seconds
Started Aug 27 03:11:33 PM UTC 24
Finished Aug 27 03:11:36 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297754656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.297754656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.1101856909
Short name T180
Test name
Test status
Simulation time 548877495 ps
CPU time 3.56 seconds
Started Aug 27 03:11:33 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101856909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1101856909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.3455428285
Short name T1076
Test name
Test status
Simulation time 587959966 ps
CPU time 5.86 seconds
Started Aug 27 03:11:33 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455428285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3455428285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1006923566
Short name T1081
Test name
Test status
Simulation time 287917792 ps
CPU time 3.42 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006923566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1006923566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2027852284
Short name T1103
Test name
Test status
Simulation time 513817627 ps
CPU time 11.91 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:49 PM UTC 24
Peak memory 251132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027852284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2027852284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.4066042750
Short name T1088
Test name
Test status
Simulation time 443904977 ps
CPU time 4.12 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066042750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.4066042750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.4062251354
Short name T1100
Test name
Test status
Simulation time 1503668849 ps
CPU time 8.24 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:45 PM UTC 24
Peak memory 251112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062251354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.4062251354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2613588100
Short name T225
Test name
Test status
Simulation time 80067447 ps
CPU time 1.79 seconds
Started Aug 27 03:03:47 PM UTC 24
Finished Aug 27 03:03:50 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613588100 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2613588100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.2037091762
Short name T133
Test name
Test status
Simulation time 467308864 ps
CPU time 5.21 seconds
Started Aug 27 03:03:39 PM UTC 24
Finished Aug 27 03:03:46 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037091762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2037091762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.2852946069
Short name T10
Test name
Test status
Simulation time 1353281753 ps
CPU time 21.16 seconds
Started Aug 27 03:03:43 PM UTC 24
Finished Aug 27 03:04:05 PM UTC 24
Peak memory 251132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852946069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2852946069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.3470874493
Short name T224
Test name
Test status
Simulation time 1076212403 ps
CPU time 5.25 seconds
Started Aug 27 03:03:42 PM UTC 24
Finished Aug 27 03:03:48 PM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470874493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3470874493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.1237855078
Short name T96
Test name
Test status
Simulation time 186724041 ps
CPU time 3.64 seconds
Started Aug 27 03:03:38 PM UTC 24
Finished Aug 27 03:03:43 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237855078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1237855078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.788423419
Short name T197
Test name
Test status
Simulation time 122918180 ps
CPU time 3.19 seconds
Started Aug 27 03:03:45 PM UTC 24
Finished Aug 27 03:03:49 PM UTC 24
Peak memory 257436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788423419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.788423419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.2113755280
Short name T118
Test name
Test status
Simulation time 1514596699 ps
CPU time 17.67 seconds
Started Aug 27 03:03:40 PM UTC 24
Finished Aug 27 03:03:59 PM UTC 24
Peak memory 257624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113755280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2113755280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.756514936
Short name T239
Test name
Test status
Simulation time 415980317 ps
CPU time 4.19 seconds
Started Aug 27 03:03:47 PM UTC 24
Finished Aug 27 03:03:52 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756514936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.756514936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.2059124001
Short name T223
Test name
Test status
Simulation time 257735865 ps
CPU time 5.92 seconds
Started Aug 27 03:03:37 PM UTC 24
Finished Aug 27 03:03:44 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059124001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2059124001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.107555606
Short name T393
Test name
Test status
Simulation time 3151161122 ps
CPU time 13.42 seconds
Started Aug 27 03:03:47 PM UTC 24
Finished Aug 27 03:04:02 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107555606 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.107555606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.3837470813
Short name T20
Test name
Test status
Simulation time 811827898 ps
CPU time 11.57 seconds
Started Aug 27 03:03:47 PM UTC 24
Finished Aug 27 03:04:00 PM UTC 24
Peak memory 250368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837470813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3837470813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.1749709782
Short name T536
Test name
Test status
Simulation time 651206784 ps
CPU time 1.88 seconds
Started Aug 27 03:05:37 PM UTC 24
Finished Aug 27 03:05:40 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749709782 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1749709782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.3287268792
Short name T61
Test name
Test status
Simulation time 1116106967 ps
CPU time 14.22 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:50 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287268792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3287268792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.220434223
Short name T257
Test name
Test status
Simulation time 954656360 ps
CPU time 13.82 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:50 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220434223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.220434223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.1400585488
Short name T546
Test name
Test status
Simulation time 1712155033 ps
CPU time 15.33 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:51 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400585488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1400585488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.3863177186
Short name T218
Test name
Test status
Simulation time 2042814389 ps
CPU time 9.18 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:45 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863177186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3863177186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.2500502278
Short name T173
Test name
Test status
Simulation time 4165247149 ps
CPU time 35.97 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:06:12 PM UTC 24
Peak memory 255452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500502278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2500502278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.1364336104
Short name T538
Test name
Test status
Simulation time 1708067451 ps
CPU time 5.7 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:42 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364336104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1364336104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.3888446448
Short name T284
Test name
Test status
Simulation time 1560001506 ps
CPU time 4.87 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:41 PM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888446448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.3888446448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.1039590020
Short name T276
Test name
Test status
Simulation time 152693026 ps
CPU time 6.67 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:43 PM UTC 24
Peak memory 251140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039590020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1039590020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.3195390709
Short name T541
Test name
Test status
Simulation time 2484776700 ps
CPU time 7.87 seconds
Started Aug 27 03:05:35 PM UTC 24
Finished Aug 27 03:05:44 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195390709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3195390709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.1803195316
Short name T534
Test name
Test status
Simulation time 1812752388 ps
CPU time 6.45 seconds
Started Aug 27 03:05:32 PM UTC 24
Finished Aug 27 03:05:39 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803195316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1803195316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.1397756186
Short name T542
Test name
Test status
Simulation time 3685902513 ps
CPU time 7.76 seconds
Started Aug 27 03:05:37 PM UTC 24
Finished Aug 27 03:05:46 PM UTC 24
Peak memory 257520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397756186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1397756186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.56847010
Short name T1071
Test name
Test status
Simulation time 195995776 ps
CPU time 3.52 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56847010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.56847010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.4016900885
Short name T78
Test name
Test status
Simulation time 812938285 ps
CPU time 5.14 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:42 PM UTC 24
Peak memory 251040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016900885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.4016900885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3097469428
Short name T1096
Test name
Test status
Simulation time 1787252872 ps
CPU time 4.55 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:42 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097469428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3097469428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.1348653713
Short name T1068
Test name
Test status
Simulation time 146421898 ps
CPU time 3.22 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348653713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1348653713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.3031890432
Short name T1082
Test name
Test status
Simulation time 132895728 ps
CPU time 3.19 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:40 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031890432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3031890432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.2760269502
Short name T1090
Test name
Test status
Simulation time 128942295 ps
CPU time 3.98 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 250492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760269502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2760269502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.2188161363
Short name T1085
Test name
Test status
Simulation time 456740994 ps
CPU time 3.51 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188161363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2188161363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.2630507209
Short name T1089
Test name
Test status
Simulation time 430028138 ps
CPU time 3.67 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 253060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630507209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2630507209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2121730437
Short name T1084
Test name
Test status
Simulation time 129926249 ps
CPU time 3.35 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 253268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121730437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2121730437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.1422749764
Short name T545
Test name
Test status
Simulation time 72714162 ps
CPU time 2.48 seconds
Started Aug 27 03:05:47 PM UTC 24
Finished Aug 27 03:05:51 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422749764 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1422749764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.3534591175
Short name T72
Test name
Test status
Simulation time 2382768831 ps
CPU time 23.06 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:06:06 PM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534591175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3534591175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.1983197758
Short name T559
Test name
Test status
Simulation time 784155298 ps
CPU time 24.58 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:06:08 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983197758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1983197758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.1866788675
Short name T555
Test name
Test status
Simulation time 2624835564 ps
CPU time 22.07 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:06:05 PM UTC 24
Peak memory 251644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866788675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1866788675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3551699844
Short name T33
Test name
Test status
Simulation time 210356556 ps
CPU time 5.92 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:05:49 PM UTC 24
Peak memory 253508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551699844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3551699844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.3023093405
Short name T544
Test name
Test status
Simulation time 203318741 ps
CPU time 3.77 seconds
Started Aug 27 03:05:44 PM UTC 24
Finished Aug 27 03:05:49 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023093405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3023093405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.709589779
Short name T484
Test name
Test status
Simulation time 187348383 ps
CPU time 5.32 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:05:48 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709589779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.709589779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.2548404682
Short name T480
Test name
Test status
Simulation time 8768238620 ps
CPU time 24.55 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:06:08 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548404682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2548404682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.617816081
Short name T543
Test name
Test status
Simulation time 202867765 ps
CPU time 4.89 seconds
Started Aug 27 03:05:42 PM UTC 24
Finished Aug 27 03:05:48 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617816081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.617816081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.515514419
Short name T274
Test name
Test status
Simulation time 56037435834 ps
CPU time 51.42 seconds
Started Aug 27 03:05:44 PM UTC 24
Finished Aug 27 03:06:37 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515514419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.515514419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.346626492
Short name T1087
Test name
Test status
Simulation time 145749541 ps
CPU time 3.59 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346626492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.346626492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2160837678
Short name T1094
Test name
Test status
Simulation time 475401554 ps
CPU time 3.99 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160837678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2160837678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.3788602357
Short name T1099
Test name
Test status
Simulation time 2956980093 ps
CPU time 7.69 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:45 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788602357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3788602357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1857092585
Short name T1086
Test name
Test status
Simulation time 258997765 ps
CPU time 3.33 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857092585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1857092585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.2968667108
Short name T1091
Test name
Test status
Simulation time 479665437 ps
CPU time 3.75 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968667108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2968667108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2559535938
Short name T1093
Test name
Test status
Simulation time 225641118 ps
CPU time 3.7 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559535938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2559535938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.1979729732
Short name T1097
Test name
Test status
Simulation time 169030850 ps
CPU time 4.52 seconds
Started Aug 27 03:11:36 PM UTC 24
Finished Aug 27 03:11:42 PM UTC 24
Peak memory 250952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979729732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1979729732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.1036607729
Short name T1095
Test name
Test status
Simulation time 529986679 ps
CPU time 3.85 seconds
Started Aug 27 03:11:37 PM UTC 24
Finished Aug 27 03:11:42 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036607729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1036607729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3474308735
Short name T1038
Test name
Test status
Simulation time 143776729 ps
CPU time 2.79 seconds
Started Aug 27 03:11:37 PM UTC 24
Finished Aug 27 03:11:41 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474308735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3474308735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.3709228600
Short name T1121
Test name
Test status
Simulation time 469793783 ps
CPU time 4.77 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 250720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709228600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.3709228600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.1577051112
Short name T556
Test name
Test status
Simulation time 627746617 ps
CPU time 3.32 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:06 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577051112 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1577051112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.2634445144
Short name T447
Test name
Test status
Simulation time 690406620 ps
CPU time 12.13 seconds
Started Aug 27 03:05:50 PM UTC 24
Finished Aug 27 03:06:03 PM UTC 24
Peak memory 251056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634445144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2634445144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.2541048275
Short name T259
Test name
Test status
Simulation time 534944545 ps
CPU time 8.72 seconds
Started Aug 27 03:05:50 PM UTC 24
Finished Aug 27 03:05:59 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541048275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2541048275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.90284110
Short name T558
Test name
Test status
Simulation time 762535767 ps
CPU time 17.48 seconds
Started Aug 27 03:05:48 PM UTC 24
Finished Aug 27 03:06:07 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90284110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.90284110
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.3922126865
Short name T237
Test name
Test status
Simulation time 3398611516 ps
CPU time 32.11 seconds
Started Aug 27 03:05:50 PM UTC 24
Finished Aug 27 03:06:23 PM UTC 24
Peak memory 255544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922126865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3922126865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.2185505291
Short name T470
Test name
Test status
Simulation time 4700831495 ps
CPU time 27.06 seconds
Started Aug 27 03:05:52 PM UTC 24
Finished Aug 27 03:06:20 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185505291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.2185505291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.1941563748
Short name T399
Test name
Test status
Simulation time 523247491 ps
CPU time 10.19 seconds
Started Aug 27 03:05:47 PM UTC 24
Finished Aug 27 03:05:59 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941563748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1941563748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.3472015935
Short name T548
Test name
Test status
Simulation time 348358374 ps
CPU time 7.38 seconds
Started Aug 27 03:05:47 PM UTC 24
Finished Aug 27 03:05:56 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472015935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3472015935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.1814492282
Short name T553
Test name
Test status
Simulation time 559086758 ps
CPU time 6.13 seconds
Started Aug 27 03:05:52 PM UTC 24
Finished Aug 27 03:05:59 PM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814492282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1814492282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.778024669
Short name T550
Test name
Test status
Simulation time 164340126 ps
CPU time 7.93 seconds
Started Aug 27 03:05:47 PM UTC 24
Finished Aug 27 03:05:56 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778024669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.778024669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2659865055
Short name T365
Test name
Test status
Simulation time 22873336329 ps
CPU time 117.27 seconds
Started Aug 27 03:05:52 PM UTC 24
Finished Aug 27 03:07:51 PM UTC 24
Peak memory 267888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2659865055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.otp_ctrl_stress_all_with_rand_reset.2659865055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.4276913431
Short name T554
Test name
Test status
Simulation time 635770298 ps
CPU time 12.24 seconds
Started Aug 27 03:05:52 PM UTC 24
Finished Aug 27 03:06:05 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276913431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.4276913431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3712188576
Short name T1104
Test name
Test status
Simulation time 556804161 ps
CPU time 3.64 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712188576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3712188576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3253097468
Short name T1129
Test name
Test status
Simulation time 2243431153 ps
CPU time 5.31 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253097468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3253097468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3932239914
Short name T1140
Test name
Test status
Simulation time 1902886241 ps
CPU time 5.96 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932239914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3932239914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.2070887924
Short name T1120
Test name
Test status
Simulation time 540475669 ps
CPU time 4.59 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070887924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2070887924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.1912740921
Short name T145
Test name
Test status
Simulation time 672735696 ps
CPU time 3.81 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912740921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1912740921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.890723627
Short name T1105
Test name
Test status
Simulation time 222674036 ps
CPU time 3.55 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890723627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.890723627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.140030520
Short name T1133
Test name
Test status
Simulation time 513113367 ps
CPU time 5.28 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140030520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.140030520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2869558863
Short name T1109
Test name
Test status
Simulation time 189109634 ps
CPU time 3.91 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869558863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2869558863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.2436407913
Short name T1107
Test name
Test status
Simulation time 156691411 ps
CPU time 3.56 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436407913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2436407913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.1392357651
Short name T557
Test name
Test status
Simulation time 169489614 ps
CPU time 1.79 seconds
Started Aug 27 03:06:04 PM UTC 24
Finished Aug 27 03:06:07 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392357651 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1392357651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.849525971
Short name T463
Test name
Test status
Simulation time 3078819783 ps
CPU time 26.03 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:29 PM UTC 24
Peak memory 257912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849525971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.849525971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.2756502239
Short name T272
Test name
Test status
Simulation time 1140022474 ps
CPU time 32.71 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:35 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756502239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2756502239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.2877227837
Short name T533
Test name
Test status
Simulation time 1035691568 ps
CPU time 24.06 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:27 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877227837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2877227837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.468594252
Short name T183
Test name
Test status
Simulation time 675386046 ps
CPU time 4.14 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:06 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468594252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.468594252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.1676669251
Short name T407
Test name
Test status
Simulation time 2069660317 ps
CPU time 7.85 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:10 PM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676669251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.1676669251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.3995728405
Short name T568
Test name
Test status
Simulation time 6683141659 ps
CPU time 17.56 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:20 PM UTC 24
Peak memory 257536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995728405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3995728405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.3997665850
Short name T400
Test name
Test status
Simulation time 583179683 ps
CPU time 5.15 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:07 PM UTC 24
Peak memory 251016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997665850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.3997665850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.4032478665
Short name T576
Test name
Test status
Simulation time 10637719367 ps
CPU time 27.47 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:30 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032478665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4032478665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.2417183400
Short name T560
Test name
Test status
Simulation time 278289777 ps
CPU time 7.96 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:10 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417183400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2417183400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.2896180583
Short name T563
Test name
Test status
Simulation time 1716582610 ps
CPU time 13.04 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:15 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896180583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2896180583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.3603664188
Short name T391
Test name
Test status
Simulation time 51769580229 ps
CPU time 82.96 seconds
Started Aug 27 03:06:03 PM UTC 24
Finished Aug 27 03:07:28 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603664188 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.3603664188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1864148672
Short name T382
Test name
Test status
Simulation time 5742015095 ps
CPU time 74.34 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:07:17 PM UTC 24
Peak memory 257708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1864148672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.otp_ctrl_stress_all_with_rand_reset.1864148672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.252261328
Short name T561
Test name
Test status
Simulation time 539567520 ps
CPU time 9.57 seconds
Started Aug 27 03:06:01 PM UTC 24
Finished Aug 27 03:06:12 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252261328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.252261328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.4159173588
Short name T1112
Test name
Test status
Simulation time 100854387 ps
CPU time 3.98 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159173588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.4159173588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3965093440
Short name T1118
Test name
Test status
Simulation time 1580835358 ps
CPU time 4.18 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 253584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965093440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3965093440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.1737890376
Short name T1119
Test name
Test status
Simulation time 524006346 ps
CPU time 4.22 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737890376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1737890376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2643850754
Short name T1110
Test name
Test status
Simulation time 148449892 ps
CPU time 3.82 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643850754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2643850754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3559518106
Short name T1126
Test name
Test status
Simulation time 663154371 ps
CPU time 4.63 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559518106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3559518106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.399710511
Short name T1130
Test name
Test status
Simulation time 359749993 ps
CPU time 4.84 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399710511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.399710511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.67329843
Short name T1125
Test name
Test status
Simulation time 193866712 ps
CPU time 4.54 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67329843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.67329843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.3693164692
Short name T1113
Test name
Test status
Simulation time 292717380 ps
CPU time 3.81 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693164692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3693164692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1893154291
Short name T1117
Test name
Test status
Simulation time 230070722 ps
CPU time 3.97 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893154291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1893154291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.849270864
Short name T1142
Test name
Test status
Simulation time 1885239225 ps
CPU time 5.44 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849270864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.849270864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.2032991066
Short name T567
Test name
Test status
Simulation time 60728301 ps
CPU time 2.81 seconds
Started Aug 27 03:06:15 PM UTC 24
Finished Aug 27 03:06:19 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032991066 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2032991066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.8540718
Short name T406
Test name
Test status
Simulation time 5896442562 ps
CPU time 31.83 seconds
Started Aug 27 03:06:09 PM UTC 24
Finished Aug 27 03:06:42 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8540718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S
EQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.8540718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.1091287719
Short name T564
Test name
Test status
Simulation time 1675621686 ps
CPU time 6.04 seconds
Started Aug 27 03:06:09 PM UTC 24
Finished Aug 27 03:06:16 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091287719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1091287719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.2215315398
Short name T236
Test name
Test status
Simulation time 118327070 ps
CPU time 4.93 seconds
Started Aug 27 03:06:07 PM UTC 24
Finished Aug 27 03:06:13 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215315398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2215315398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.4264285144
Short name T595
Test name
Test status
Simulation time 21509070338 ps
CPU time 38.08 seconds
Started Aug 27 03:06:09 PM UTC 24
Finished Aug 27 03:06:49 PM UTC 24
Peak memory 267808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264285144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.4264285144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.897517516
Short name T570
Test name
Test status
Simulation time 412216338 ps
CPU time 13.13 seconds
Started Aug 27 03:06:11 PM UTC 24
Finished Aug 27 03:06:26 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897517516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.897517516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.1144057649
Short name T573
Test name
Test status
Simulation time 629002841 ps
CPU time 19.44 seconds
Started Aug 27 03:06:07 PM UTC 24
Finished Aug 27 03:06:28 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144057649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1144057649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.773959509
Short name T566
Test name
Test status
Simulation time 327302804 ps
CPU time 4.86 seconds
Started Aug 27 03:06:12 PM UTC 24
Finished Aug 27 03:06:17 PM UTC 24
Peak memory 251272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773959509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.773959509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.214638893
Short name T562
Test name
Test status
Simulation time 276964788 ps
CPU time 6.73 seconds
Started Aug 27 03:06:07 PM UTC 24
Finished Aug 27 03:06:15 PM UTC 24
Peak memory 250624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214638893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.214638893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.4210867024
Short name T599
Test name
Test status
Simulation time 6140879789 ps
CPU time 34.66 seconds
Started Aug 27 03:06:15 PM UTC 24
Finished Aug 27 03:06:51 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210867024 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.4210867024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.1655783055
Short name T364
Test name
Test status
Simulation time 3423660516 ps
CPU time 79.21 seconds
Started Aug 27 03:06:12 PM UTC 24
Finished Aug 27 03:07:33 PM UTC 24
Peak memory 257712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1655783055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.otp_ctrl_stress_all_with_rand_reset.1655783055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.2225011838
Short name T572
Test name
Test status
Simulation time 663434181 ps
CPU time 14.64 seconds
Started Aug 27 03:06:12 PM UTC 24
Finished Aug 27 03:06:27 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225011838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2225011838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.575633422
Short name T1114
Test name
Test status
Simulation time 161328030 ps
CPU time 3.84 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575633422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.575633422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1109954502
Short name T1115
Test name
Test status
Simulation time 123796009 ps
CPU time 3.73 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109954502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1109954502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.1459951312
Short name T1132
Test name
Test status
Simulation time 280472424 ps
CPU time 4.66 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459951312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1459951312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.2196907683
Short name T1128
Test name
Test status
Simulation time 175773843 ps
CPU time 4.47 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196907683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2196907683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1830685751
Short name T1108
Test name
Test status
Simulation time 149887807 ps
CPU time 3.15 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830685751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1830685751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2484543023
Short name T1106
Test name
Test status
Simulation time 94456016 ps
CPU time 2.88 seconds
Started Aug 27 03:11:45 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484543023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2484543023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.24255249
Short name T1122
Test name
Test status
Simulation time 255551005 ps
CPU time 4 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24255249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.24255249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.4268397464
Short name T1123
Test name
Test status
Simulation time 304135247 ps
CPU time 4.11 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268397464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.4268397464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.745392008
Short name T1135
Test name
Test status
Simulation time 147357310 ps
CPU time 4.81 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745392008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.745392008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.1671615257
Short name T571
Test name
Test status
Simulation time 80571512 ps
CPU time 2 seconds
Started Aug 27 03:06:24 PM UTC 24
Finished Aug 27 03:06:27 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671615257 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1671615257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.2587636660
Short name T582
Test name
Test status
Simulation time 815376328 ps
CPU time 23.12 seconds
Started Aug 27 03:06:17 PM UTC 24
Finished Aug 27 03:06:41 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587636660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2587636660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.4041064311
Short name T581
Test name
Test status
Simulation time 2056111453 ps
CPU time 22.14 seconds
Started Aug 27 03:06:17 PM UTC 24
Finished Aug 27 03:06:40 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041064311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4041064311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.2015528920
Short name T248
Test name
Test status
Simulation time 1011069056 ps
CPU time 24.23 seconds
Started Aug 27 03:06:19 PM UTC 24
Finished Aug 27 03:06:45 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015528920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2015528920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.3608182564
Short name T577
Test name
Test status
Simulation time 788392582 ps
CPU time 9.69 seconds
Started Aug 27 03:06:19 PM UTC 24
Finished Aug 27 03:06:30 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608182564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3608182564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.1878996270
Short name T485
Test name
Test status
Simulation time 294132760 ps
CPU time 8.08 seconds
Started Aug 27 03:06:17 PM UTC 24
Finished Aug 27 03:06:26 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878996270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1878996270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.3619340218
Short name T575
Test name
Test status
Simulation time 1473166720 ps
CPU time 12.94 seconds
Started Aug 27 03:06:15 PM UTC 24
Finished Aug 27 03:06:29 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619340218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3619340218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2331746377
Short name T574
Test name
Test status
Simulation time 283001265 ps
CPU time 8.13 seconds
Started Aug 27 03:06:19 PM UTC 24
Finished Aug 27 03:06:29 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331746377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2331746377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.3437264768
Short name T569
Test name
Test status
Simulation time 322493284 ps
CPU time 5.19 seconds
Started Aug 27 03:06:15 PM UTC 24
Finished Aug 27 03:06:21 PM UTC 24
Peak memory 251600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437264768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3437264768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.2437093178
Short name T339
Test name
Test status
Simulation time 2822056284 ps
CPU time 41.7 seconds
Started Aug 27 03:06:24 PM UTC 24
Finished Aug 27 03:07:07 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437093178 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.2437093178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.3949044792
Short name T273
Test name
Test status
Simulation time 471002709 ps
CPU time 15.49 seconds
Started Aug 27 03:06:19 PM UTC 24
Finished Aug 27 03:06:36 PM UTC 24
Peak memory 251372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949044792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3949044792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2577943307
Short name T1139
Test name
Test status
Simulation time 462424179 ps
CPU time 4.92 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577943307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2577943307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.3579723651
Short name T1116
Test name
Test status
Simulation time 190580242 ps
CPU time 3.55 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579723651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3579723651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.2790103497
Short name T1136
Test name
Test status
Simulation time 309800184 ps
CPU time 4.75 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790103497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2790103497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.2993534449
Short name T1138
Test name
Test status
Simulation time 214522742 ps
CPU time 4.98 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 253264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993534449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2993534449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.3158640233
Short name T1141
Test name
Test status
Simulation time 204118069 ps
CPU time 4.9 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158640233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3158640233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.903465954
Short name T1144
Test name
Test status
Simulation time 2001502338 ps
CPU time 6.26 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:53 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903465954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.903465954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.866492617
Short name T1111
Test name
Test status
Simulation time 124336304 ps
CPU time 3.15 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:50 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866492617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.866492617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.280322341
Short name T1148
Test name
Test status
Simulation time 2821380312 ps
CPU time 7.6 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:55 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280322341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.280322341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1066333825
Short name T1146
Test name
Test status
Simulation time 2953197589 ps
CPU time 6.32 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:54 PM UTC 24
Peak memory 251580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066333825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1066333825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.1334767146
Short name T1143
Test name
Test status
Simulation time 2472862529 ps
CPU time 5.3 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:53 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334767146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1334767146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.3242846174
Short name T271
Test name
Test status
Simulation time 54655335 ps
CPU time 2.55 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:35 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242846174 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3242846174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.567779833
Short name T126
Test name
Test status
Simulation time 602287761 ps
CPU time 9.22 seconds
Started Aug 27 03:06:27 PM UTC 24
Finished Aug 27 03:06:37 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567779833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.567779833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.1551707578
Short name T617
Test name
Test status
Simulation time 5353309242 ps
CPU time 34.3 seconds
Started Aug 27 03:06:27 PM UTC 24
Finished Aug 27 03:07:03 PM UTC 24
Peak memory 255520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551707578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1551707578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.210299273
Short name T583
Test name
Test status
Simulation time 2460819191 ps
CPU time 15.18 seconds
Started Aug 27 03:06:27 PM UTC 24
Finished Aug 27 03:06:43 PM UTC 24
Peak memory 253500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210299273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.210299273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.38570979
Short name T220
Test name
Test status
Simulation time 328895824 ps
CPU time 4.09 seconds
Started Aug 27 03:06:24 PM UTC 24
Finished Aug 27 03:06:29 PM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38570979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.38570979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.3014255646
Short name T585
Test name
Test status
Simulation time 1433466097 ps
CPU time 15.54 seconds
Started Aug 27 03:06:27 PM UTC 24
Finished Aug 27 03:06:44 PM UTC 24
Peak memory 255416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014255646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3014255646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.710304159
Short name T464
Test name
Test status
Simulation time 199777365 ps
CPU time 7.33 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:39 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710304159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.710304159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.4256817120
Short name T289
Test name
Test status
Simulation time 1042504897 ps
CPU time 11.5 seconds
Started Aug 27 03:06:27 PM UTC 24
Finished Aug 27 03:06:40 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256817120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.4256817120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3914051592
Short name T605
Test name
Test status
Simulation time 3413823732 ps
CPU time 30.27 seconds
Started Aug 27 03:06:24 PM UTC 24
Finished Aug 27 03:06:56 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914051592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3914051592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.4152964225
Short name T579
Test name
Test status
Simulation time 579026901 ps
CPU time 5.64 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:37 PM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152964225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.4152964225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.1180445243
Short name T578
Test name
Test status
Simulation time 553119273 ps
CPU time 6.83 seconds
Started Aug 27 03:06:24 PM UTC 24
Finished Aug 27 03:06:32 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180445243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1180445243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.2884565107
Short name T697
Test name
Test status
Simulation time 17622228297 ps
CPU time 95.4 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:08:08 PM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884565107 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.2884565107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3278819451
Short name T170
Test name
Test status
Simulation time 3931381980 ps
CPU time 28.37 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:07:01 PM UTC 24
Peak memory 274228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3278819451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.otp_ctrl_stress_all_with_rand_reset.3278819451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.2347043906
Short name T580
Test name
Test status
Simulation time 865413839 ps
CPU time 7.54 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:39 PM UTC 24
Peak memory 251308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347043906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2347043906
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.3802515280
Short name T1124
Test name
Test status
Simulation time 2126063557 ps
CPU time 3.84 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802515280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3802515280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.2743740492
Short name T1131
Test name
Test status
Simulation time 597766036 ps
CPU time 4.08 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743740492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2743740492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.2141705844
Short name T1145
Test name
Test status
Simulation time 2212523475 ps
CPU time 6.29 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:54 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141705844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2141705844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3294699852
Short name T1137
Test name
Test status
Simulation time 165340017 ps
CPU time 4.61 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:52 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294699852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3294699852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.2734228566
Short name T1134
Test name
Test status
Simulation time 103647177 ps
CPU time 4.22 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734228566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2734228566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.2471096572
Short name T1127
Test name
Test status
Simulation time 120374986 ps
CPU time 3.82 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:51 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471096572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2471096572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.157156403
Short name T1150
Test name
Test status
Simulation time 2484827184 ps
CPU time 7.95 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:55 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157156403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.157156403
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.649200735
Short name T1147
Test name
Test status
Simulation time 2370653876 ps
CPU time 6.28 seconds
Started Aug 27 03:11:46 PM UTC 24
Finished Aug 27 03:11:54 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649200735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.649200735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.1696525400
Short name T1151
Test name
Test status
Simulation time 350344305 ps
CPU time 3.43 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:58 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696525400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1696525400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.825227305
Short name T1152
Test name
Test status
Simulation time 284561862 ps
CPU time 3.72 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825227305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.825227305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.350311574
Short name T586
Test name
Test status
Simulation time 88614119 ps
CPU time 2.33 seconds
Started Aug 27 03:06:40 PM UTC 24
Finished Aug 27 03:06:44 PM UTC 24
Peak memory 251244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350311574 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.350311574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.1408407164
Short name T584
Test name
Test status
Simulation time 2140820189 ps
CPU time 8.55 seconds
Started Aug 27 03:06:34 PM UTC 24
Finished Aug 27 03:06:43 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408407164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1408407164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.2161591745
Short name T601
Test name
Test status
Simulation time 1698108663 ps
CPU time 17.93 seconds
Started Aug 27 03:06:34 PM UTC 24
Finished Aug 27 03:06:53 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161591745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2161591745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.3357526884
Short name T195
Test name
Test status
Simulation time 341352254 ps
CPU time 5 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:37 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357526884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3357526884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.351614704
Short name T590
Test name
Test status
Simulation time 868184434 ps
CPU time 10.61 seconds
Started Aug 27 03:06:34 PM UTC 24
Finished Aug 27 03:06:46 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351614704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.351614704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.612496963
Short name T588
Test name
Test status
Simulation time 142991216 ps
CPU time 6.9 seconds
Started Aug 27 03:06:37 PM UTC 24
Finished Aug 27 03:06:45 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612496963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.612496963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.3095208516
Short name T589
Test name
Test status
Simulation time 190365136 ps
CPU time 10.64 seconds
Started Aug 27 03:06:34 PM UTC 24
Finished Aug 27 03:06:46 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095208516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3095208516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.3940838388
Short name T467
Test name
Test status
Simulation time 496924254 ps
CPU time 11.56 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:44 PM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940838388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.3940838388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.2432565653
Short name T594
Test name
Test status
Simulation time 1033432947 ps
CPU time 9.75 seconds
Started Aug 27 03:06:37 PM UTC 24
Finished Aug 27 03:06:48 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432565653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2432565653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.2403802509
Short name T275
Test name
Test status
Simulation time 604277703 ps
CPU time 5.27 seconds
Started Aug 27 03:06:31 PM UTC 24
Finished Aug 27 03:06:37 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403802509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2403802509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.1142429820
Short name T381
Test name
Test status
Simulation time 6311248915 ps
CPU time 67.39 seconds
Started Aug 27 03:06:40 PM UTC 24
Finished Aug 27 03:07:49 PM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142429820 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.1142429820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.4148539532
Short name T460
Test name
Test status
Simulation time 6790457515 ps
CPU time 91.96 seconds
Started Aug 27 03:06:40 PM UTC 24
Finished Aug 27 03:08:14 PM UTC 24
Peak memory 271896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4148539532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.otp_ctrl_stress_all_with_rand_reset.4148539532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1732801353
Short name T587
Test name
Test status
Simulation time 802237445 ps
CPU time 6.13 seconds
Started Aug 27 03:06:37 PM UTC 24
Finished Aug 27 03:06:45 PM UTC 24
Peak memory 257452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732801353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1732801353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.3988741563
Short name T1164
Test name
Test status
Simulation time 523132507 ps
CPU time 4.65 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988741563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.3988741563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3805418508
Short name T1170
Test name
Test status
Simulation time 2765631180 ps
CPU time 5.09 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 250640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805418508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3805418508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3327326485
Short name T1175
Test name
Test status
Simulation time 2627369117 ps
CPU time 6.82 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:02 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327326485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3327326485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3448039917
Short name T144
Test name
Test status
Simulation time 197938156 ps
CPU time 3.8 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448039917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3448039917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2583747119
Short name T1149
Test name
Test status
Simulation time 448301371 ps
CPU time 4.18 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583747119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2583747119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.3491274215
Short name T129
Test name
Test status
Simulation time 422714576 ps
CPU time 4.06 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 253520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491274215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3491274215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3979134942
Short name T1161
Test name
Test status
Simulation time 126434211 ps
CPU time 4.45 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979134942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3979134942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.2147679070
Short name T1158
Test name
Test status
Simulation time 1647992930 ps
CPU time 4.02 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147679070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2147679070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.3388303760
Short name T1153
Test name
Test status
Simulation time 325833941 ps
CPU time 3.48 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388303760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3388303760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.1041473648
Short name T1157
Test name
Test status
Simulation time 791737111 ps
CPU time 4.11 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041473648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1041473648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.3741568204
Short name T596
Test name
Test status
Simulation time 96052036 ps
CPU time 2 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:06:49 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741568204 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3741568204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.1215609690
Short name T469
Test name
Test status
Simulation time 865979851 ps
CPU time 13.53 seconds
Started Aug 27 03:06:41 PM UTC 24
Finished Aug 27 03:06:55 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215609690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1215609690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.3486945436
Short name T602
Test name
Test status
Simulation time 2154799052 ps
CPU time 12.58 seconds
Started Aug 27 03:06:41 PM UTC 24
Finished Aug 27 03:06:54 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486945436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3486945436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.1681894564
Short name T593
Test name
Test status
Simulation time 2447827501 ps
CPU time 6.58 seconds
Started Aug 27 03:06:41 PM UTC 24
Finished Aug 27 03:06:48 PM UTC 24
Peak memory 251620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681894564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1681894564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.1787796711
Short name T591
Test name
Test status
Simulation time 113948518 ps
CPU time 4.82 seconds
Started Aug 27 03:06:40 PM UTC 24
Finished Aug 27 03:06:46 PM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787796711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1787796711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.1858624010
Short name T190
Test name
Test status
Simulation time 326447042 ps
CPU time 10.79 seconds
Started Aug 27 03:06:43 PM UTC 24
Finished Aug 27 03:06:55 PM UTC 24
Peak memory 253684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858624010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1858624010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2700092102
Short name T607
Test name
Test status
Simulation time 1141262969 ps
CPU time 12.07 seconds
Started Aug 27 03:06:43 PM UTC 24
Finished Aug 27 03:06:56 PM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700092102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2700092102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.4215965880
Short name T295
Test name
Test status
Simulation time 2603335088 ps
CPU time 16.94 seconds
Started Aug 27 03:06:41 PM UTC 24
Finished Aug 27 03:06:59 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215965880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.4215965880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.3160919749
Short name T597
Test name
Test status
Simulation time 506325516 ps
CPU time 8.23 seconds
Started Aug 27 03:06:40 PM UTC 24
Finished Aug 27 03:06:50 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160919749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3160919749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.191642306
Short name T598
Test name
Test status
Simulation time 1127131767 ps
CPU time 6.72 seconds
Started Aug 27 03:06:43 PM UTC 24
Finished Aug 27 03:06:51 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191642306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.191642306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3121715640
Short name T604
Test name
Test status
Simulation time 8256397601 ps
CPU time 14.05 seconds
Started Aug 27 03:06:40 PM UTC 24
Finished Aug 27 03:06:56 PM UTC 24
Peak memory 257628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121715640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3121715640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.3766854858
Short name T338
Test name
Test status
Simulation time 443192700 ps
CPU time 13.52 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:07:01 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766854858 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.3766854858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.946528227
Short name T457
Test name
Test status
Simulation time 13867416764 ps
CPU time 104.19 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:08:32 PM UTC 24
Peak memory 274228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=946528227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
28.otp_ctrl_stress_all_with_rand_reset.946528227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.1095769193
Short name T613
Test name
Test status
Simulation time 2327243730 ps
CPU time 13.63 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:07:01 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095769193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1095769193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.1876149544
Short name T1172
Test name
Test status
Simulation time 1969785294 ps
CPU time 5.23 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876149544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1876149544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2489153316
Short name T1154
Test name
Test status
Simulation time 193901389 ps
CPU time 3.55 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489153316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2489153316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1114943749
Short name T1155
Test name
Test status
Simulation time 458164010 ps
CPU time 3.67 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114943749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1114943749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3309026294
Short name T1163
Test name
Test status
Simulation time 477547984 ps
CPU time 4.16 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309026294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3309026294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3346785606
Short name T1156
Test name
Test status
Simulation time 139813176 ps
CPU time 3.62 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346785606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3346785606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.4290714954
Short name T1160
Test name
Test status
Simulation time 544956521 ps
CPU time 3.92 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290714954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.4290714954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2053837633
Short name T1177
Test name
Test status
Simulation time 2944495930 ps
CPU time 8.28 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:04 PM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053837633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2053837633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.460318292
Short name T1165
Test name
Test status
Simulation time 540526945 ps
CPU time 4.09 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460318292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.460318292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.3450852505
Short name T1176
Test name
Test status
Simulation time 2369162304 ps
CPU time 6.42 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:02 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450852505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.3450852505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.3981757373
Short name T606
Test name
Test status
Simulation time 126159902 ps
CPU time 2.81 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:06:56 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981757373 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3981757373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.3083813489
Short name T446
Test name
Test status
Simulation time 1172587471 ps
CPU time 22.31 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:15 PM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083813489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3083813489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.2794128154
Short name T387
Test name
Test status
Simulation time 1333190311 ps
CPU time 26.5 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:19 PM UTC 24
Peak memory 255332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794128154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2794128154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.860956096
Short name T624
Test name
Test status
Simulation time 2951037411 ps
CPU time 18.19 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:11 PM UTC 24
Peak memory 253692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860956096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.860956096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.431568032
Short name T600
Test name
Test status
Simulation time 289946223 ps
CPU time 4.74 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:06:52 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431568032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.431568032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.809638082
Short name T592
Test name
Test status
Simulation time 378921834 ps
CPU time 14.81 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:08 PM UTC 24
Peak memory 253096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809638082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.809638082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.2257148082
Short name T616
Test name
Test status
Simulation time 6138580403 ps
CPU time 14.35 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:07 PM UTC 24
Peak memory 253408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257148082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.2257148082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.2937658453
Short name T610
Test name
Test status
Simulation time 528024436 ps
CPU time 12.62 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:07:00 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937658453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2937658453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.2988435425
Short name T603
Test name
Test status
Simulation time 890006407 ps
CPU time 7.85 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:06:55 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988435425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2988435425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.349821439
Short name T609
Test name
Test status
Simulation time 124538942 ps
CPU time 5.81 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:06:59 PM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349821439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.349821439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.1235077164
Short name T608
Test name
Test status
Simulation time 500162539 ps
CPU time 9.15 seconds
Started Aug 27 03:06:46 PM UTC 24
Finished Aug 27 03:06:56 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235077164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1235077164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.986979236
Short name T476
Test name
Test status
Simulation time 2679875225 ps
CPU time 51.92 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:46 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986979236 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.986979236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.1728780315
Short name T612
Test name
Test status
Simulation time 518446057 ps
CPU time 7.4 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:00 PM UTC 24
Peak memory 257456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728780315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1728780315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.2566469954
Short name T1166
Test name
Test status
Simulation time 153079439 ps
CPU time 4.17 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566469954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2566469954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3433249361
Short name T1167
Test name
Test status
Simulation time 125439816 ps
CPU time 4.18 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433249361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3433249361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2242727738
Short name T69
Test name
Test status
Simulation time 127599838 ps
CPU time 4.06 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242727738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2242727738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.1451766958
Short name T1173
Test name
Test status
Simulation time 1467559506 ps
CPU time 5.1 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451766958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1451766958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.4260899835
Short name T1162
Test name
Test status
Simulation time 98865436 ps
CPU time 3.77 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 253264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260899835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.4260899835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.790624450
Short name T1168
Test name
Test status
Simulation time 110763254 ps
CPU time 4.23 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790624450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.790624450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.327952347
Short name T1174
Test name
Test status
Simulation time 372647790 ps
CPU time 5.3 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:12:01 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327952347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.327952347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.2921595447
Short name T1159
Test name
Test status
Simulation time 432662154 ps
CPU time 3.53 seconds
Started Aug 27 03:11:54 PM UTC 24
Finished Aug 27 03:11:59 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921595447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2921595447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3822044890
Short name T1171
Test name
Test status
Simulation time 156986674 ps
CPU time 4.51 seconds
Started Aug 27 03:11:55 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822044890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3822044890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.3734805248
Short name T250
Test name
Test status
Simulation time 102192980 ps
CPU time 1.92 seconds
Started Aug 27 03:03:51 PM UTC 24
Finished Aug 27 03:03:54 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734805248 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.3734805248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.2721229130
Short name T97
Test name
Test status
Simulation time 1847746194 ps
CPU time 19.51 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:09 PM UTC 24
Peak memory 253364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721229130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2721229130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.3265298044
Short name T405
Test name
Test status
Simulation time 5049156196 ps
CPU time 33.23 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:24 PM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265298044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3265298044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.3529368887
Short name T253
Test name
Test status
Simulation time 11127068610 ps
CPU time 22.17 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:12 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529368887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3529368887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.1387205838
Short name T175
Test name
Test status
Simulation time 449457321 ps
CPU time 12.48 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:03 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387205838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1387205838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.48740187
Short name T123
Test name
Test status
Simulation time 1050523079 ps
CPU time 16.74 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:07 PM UTC 24
Peak memory 251052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48740187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.48740187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.4246420609
Short name T238
Test name
Test status
Simulation time 75096204 ps
CPU time 2.23 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:03:52 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246420609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.4246420609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.3892260160
Short name T268
Test name
Test status
Simulation time 12274738128 ps
CPU time 182.08 seconds
Started Aug 27 03:03:51 PM UTC 24
Finished Aug 27 03:06:56 PM UTC 24
Peak memory 297772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892260160 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3892260160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2953530368
Short name T251
Test name
Test status
Simulation time 255848638 ps
CPU time 5.62 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:03:55 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953530368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2953530368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.1658885928
Short name T300
Test name
Test status
Simulation time 15490223363 ps
CPU time 23.92 seconds
Started Aug 27 03:03:49 PM UTC 24
Finished Aug 27 03:04:14 PM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658885928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1658885928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.2268685350
Short name T615
Test name
Test status
Simulation time 249309501 ps
CPU time 3.34 seconds
Started Aug 27 03:06:58 PM UTC 24
Finished Aug 27 03:07:02 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268685350 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2268685350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.2078752166
Short name T50
Test name
Test status
Simulation time 2116897496 ps
CPU time 25.59 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:24 PM UTC 24
Peak memory 253688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078752166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.2078752166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.2096988980
Short name T385
Test name
Test status
Simulation time 800415291 ps
CPU time 20.42 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:19 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096988980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2096988980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2318734930
Short name T645
Test name
Test status
Simulation time 2614901729 ps
CPU time 31.43 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:30 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318734930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2318734930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.1307754451
Short name T196
Test name
Test status
Simulation time 267865832 ps
CPU time 4.18 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:06:57 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307754451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1307754451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.4114841771
Short name T451
Test name
Test status
Simulation time 23574623697 ps
CPU time 43.41 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:42 PM UTC 24
Peak memory 267832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114841771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.4114841771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.2551539589
Short name T625
Test name
Test status
Simulation time 625452999 ps
CPU time 13.68 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:12 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551539589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2551539589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.2056281839
Short name T622
Test name
Test status
Simulation time 208320569 ps
CPU time 11.57 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:10 PM UTC 24
Peak memory 250848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056281839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2056281839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3141533610
Short name T618
Test name
Test status
Simulation time 1999463549 ps
CPU time 5.63 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:04 PM UTC 24
Peak memory 250860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141533610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3141533610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.4241525535
Short name T384
Test name
Test status
Simulation time 5189496563 ps
CPU time 19.5 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:18 PM UTC 24
Peak memory 253388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241525535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.4241525535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.3899183489
Short name T611
Test name
Test status
Simulation time 424322544 ps
CPU time 7.1 seconds
Started Aug 27 03:06:52 PM UTC 24
Finished Aug 27 03:07:00 PM UTC 24
Peak memory 257436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899183489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3899183489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.3651019592
Short name T159
Test name
Test status
Simulation time 11668435983 ps
CPU time 85.22 seconds
Started Aug 27 03:06:58 PM UTC 24
Finished Aug 27 03:08:25 PM UTC 24
Peak memory 255420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651019592 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.3651019592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.937993644
Short name T628
Test name
Test status
Simulation time 2919123079 ps
CPU time 16.03 seconds
Started Aug 27 03:06:57 PM UTC 24
Finished Aug 27 03:07:15 PM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937993644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.937993644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.3594224557
Short name T621
Test name
Test status
Simulation time 101301204 ps
CPU time 2.62 seconds
Started Aug 27 03:07:05 PM UTC 24
Finished Aug 27 03:07:09 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594224557 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3594224557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3857445689
Short name T141
Test name
Test status
Simulation time 1068116156 ps
CPU time 10.14 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:07:14 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857445689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3857445689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.3482732017
Short name T629
Test name
Test status
Simulation time 5776193152 ps
CPU time 13.83 seconds
Started Aug 27 03:07:00 PM UTC 24
Finished Aug 27 03:07:15 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482732017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3482732017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.3234541823
Short name T634
Test name
Test status
Simulation time 12180937718 ps
CPU time 20.21 seconds
Started Aug 27 03:07:00 PM UTC 24
Finished Aug 27 03:07:22 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234541823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3234541823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.2149835598
Short name T39
Test name
Test status
Simulation time 210112561 ps
CPU time 5.83 seconds
Started Aug 27 03:07:00 PM UTC 24
Finished Aug 27 03:07:07 PM UTC 24
Peak memory 253276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149835598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2149835598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.1478257913
Short name T635
Test name
Test status
Simulation time 2372145323 ps
CPU time 18.03 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:07:22 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478257913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1478257913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.532053919
Short name T636
Test name
Test status
Simulation time 1787855795 ps
CPU time 18.61 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:07:23 PM UTC 24
Peak memory 253592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532053919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.532053919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.2228995813
Short name T614
Test name
Test status
Simulation time 294693831 ps
CPU time 3.27 seconds
Started Aug 27 03:07:00 PM UTC 24
Finished Aug 27 03:07:04 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228995813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2228995813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.79623153
Short name T626
Test name
Test status
Simulation time 1593584968 ps
CPU time 12.81 seconds
Started Aug 27 03:07:00 PM UTC 24
Finished Aug 27 03:07:14 PM UTC 24
Peak memory 256956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79623153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.79623153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.2068622312
Short name T620
Test name
Test status
Simulation time 400345151 ps
CPU time 4.88 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:07:09 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068622312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2068622312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.230257581
Short name T619
Test name
Test status
Simulation time 1238159459 ps
CPU time 14.38 seconds
Started Aug 27 03:06:58 PM UTC 24
Finished Aug 27 03:07:13 PM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230257581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.230257581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.340766649
Short name T455
Test name
Test status
Simulation time 1280425638 ps
CPU time 39.64 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:07:44 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340766649 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.340766649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3402816008
Short name T445
Test name
Test status
Simulation time 3246356321 ps
CPU time 58 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:08:02 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3402816008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.otp_ctrl_stress_all_with_rand_reset.3402816008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.3386478459
Short name T453
Test name
Test status
Simulation time 2292061373 ps
CPU time 25.32 seconds
Started Aug 27 03:07:03 PM UTC 24
Finished Aug 27 03:07:30 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386478459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.3386478459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.2179890491
Short name T630
Test name
Test status
Simulation time 239037257 ps
CPU time 3.55 seconds
Started Aug 27 03:07:12 PM UTC 24
Finished Aug 27 03:07:17 PM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179890491 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2179890491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.2190990415
Short name T83
Test name
Test status
Simulation time 1860749594 ps
CPU time 29.87 seconds
Started Aug 27 03:07:09 PM UTC 24
Finished Aug 27 03:07:40 PM UTC 24
Peak memory 253688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190990415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2190990415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.1492021235
Short name T640
Test name
Test status
Simulation time 1004360971 ps
CPU time 15.4 seconds
Started Aug 27 03:07:09 PM UTC 24
Finished Aug 27 03:07:26 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492021235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1492021235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.383079291
Short name T627
Test name
Test status
Simulation time 206655744 ps
CPU time 7.41 seconds
Started Aug 27 03:07:06 PM UTC 24
Finished Aug 27 03:07:14 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383079291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.383079291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.4051591717
Short name T221
Test name
Test status
Simulation time 795906614 ps
CPU time 16.49 seconds
Started Aug 27 03:07:09 PM UTC 24
Finished Aug 27 03:07:27 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051591717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.4051591717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.4242950896
Short name T631
Test name
Test status
Simulation time 172243795 ps
CPU time 6.7 seconds
Started Aug 27 03:07:09 PM UTC 24
Finished Aug 27 03:07:17 PM UTC 24
Peak memory 257692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242950896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.4242950896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.1517528145
Short name T292
Test name
Test status
Simulation time 965365786 ps
CPU time 11.78 seconds
Started Aug 27 03:07:05 PM UTC 24
Finished Aug 27 03:07:18 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517528145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1517528145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.1769915887
Short name T383
Test name
Test status
Simulation time 542657668 ps
CPU time 11.21 seconds
Started Aug 27 03:07:05 PM UTC 24
Finished Aug 27 03:07:18 PM UTC 24
Peak memory 257372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769915887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1769915887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.473281374
Short name T422
Test name
Test status
Simulation time 272070374 ps
CPU time 9.4 seconds
Started Aug 27 03:07:09 PM UTC 24
Finished Aug 27 03:07:20 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473281374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.473281374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.4023720608
Short name T637
Test name
Test status
Simulation time 6951270231 ps
CPU time 16.11 seconds
Started Aug 27 03:07:05 PM UTC 24
Finished Aug 27 03:07:23 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023720608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.4023720608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1438174356
Short name T722
Test name
Test status
Simulation time 8015374437 ps
CPU time 69.43 seconds
Started Aug 27 03:07:11 PM UTC 24
Finished Aug 27 03:08:22 PM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438174356 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1438174356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.1072617271
Short name T633
Test name
Test status
Simulation time 868846118 ps
CPU time 8.87 seconds
Started Aug 27 03:07:11 PM UTC 24
Finished Aug 27 03:07:21 PM UTC 24
Peak memory 257412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072617271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1072617271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.2646620257
Short name T638
Test name
Test status
Simulation time 113174404 ps
CPU time 2.85 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:07:24 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646620257 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2646620257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.534169903
Short name T706
Test name
Test status
Simulation time 4521127474 ps
CPU time 51.68 seconds
Started Aug 27 03:07:19 PM UTC 24
Finished Aug 27 03:08:13 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534169903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.534169903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.1538729126
Short name T649
Test name
Test status
Simulation time 350053817 ps
CPU time 18.25 seconds
Started Aug 27 03:07:16 PM UTC 24
Finished Aug 27 03:07:35 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538729126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1538729126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3461380499
Short name T655
Test name
Test status
Simulation time 956219537 ps
CPU time 22.08 seconds
Started Aug 27 03:07:15 PM UTC 24
Finished Aug 27 03:07:39 PM UTC 24
Peak memory 251580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461380499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3461380499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2495659671
Short name T632
Test name
Test status
Simulation time 514962882 ps
CPU time 5.29 seconds
Started Aug 27 03:07:14 PM UTC 24
Finished Aug 27 03:07:20 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495659671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2495659671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.755318607
Short name T662
Test name
Test status
Simulation time 985154143 ps
CPU time 21.66 seconds
Started Aug 27 03:07:19 PM UTC 24
Finished Aug 27 03:07:42 PM UTC 24
Peak memory 253344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755318607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.755318607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.3864973870
Short name T683
Test name
Test status
Simulation time 11995707374 ps
CPU time 39.52 seconds
Started Aug 27 03:07:19 PM UTC 24
Finished Aug 27 03:08:00 PM UTC 24
Peak memory 253660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864973870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3864973870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.1157603857
Short name T651
Test name
Test status
Simulation time 808767718 ps
CPU time 20.28 seconds
Started Aug 27 03:07:15 PM UTC 24
Finished Aug 27 03:07:37 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157603857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1157603857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.4027408640
Short name T647
Test name
Test status
Simulation time 326780645 ps
CPU time 11.29 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:07:32 PM UTC 24
Peak memory 251052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027408640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.4027408640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.637309407
Short name T386
Test name
Test status
Simulation time 175653847 ps
CPU time 4.62 seconds
Started Aug 27 03:07:14 PM UTC 24
Finished Aug 27 03:07:19 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637309407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.637309407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.3829781378
Short name T1182
Test name
Test status
Simulation time 145426720764 ps
CPU time 453.56 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:15:00 PM UTC 24
Peak memory 292276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829781378 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.3829781378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.959652238
Short name T402
Test name
Test status
Simulation time 13665168840 ps
CPU time 102.92 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:09:05 PM UTC 24
Peak memory 274100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=959652238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
33.otp_ctrl_stress_all_with_rand_reset.959652238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.2650872386
Short name T641
Test name
Test status
Simulation time 246669088 ps
CPU time 5.27 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:07:26 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650872386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2650872386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.520456733
Short name T644
Test name
Test status
Simulation time 765113771 ps
CPU time 2.83 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:29 PM UTC 24
Peak memory 251240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520456733 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.520456733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1663391498
Short name T661
Test name
Test status
Simulation time 1953352196 ps
CPU time 15.27 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:42 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663391498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1663391498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.2987257448
Short name T666
Test name
Test status
Simulation time 1926516146 ps
CPU time 20.37 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:47 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987257448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2987257448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.3518411796
Short name T461
Test name
Test status
Simulation time 18409457942 ps
CPU time 22.9 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:49 PM UTC 24
Peak memory 253692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518411796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3518411796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.214145340
Short name T642
Test name
Test status
Simulation time 387953449 ps
CPU time 6.25 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:07:27 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214145340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.214145340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.1025868828
Short name T652
Test name
Test status
Simulation time 485256448 ps
CPU time 11.02 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:37 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025868828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1025868828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.1458337338
Short name T657
Test name
Test status
Simulation time 305135878 ps
CPU time 13.8 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:40 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458337338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1458337338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.1649682099
Short name T658
Test name
Test status
Simulation time 461043486 ps
CPU time 14.65 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:41 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649682099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1649682099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.1569145087
Short name T639
Test name
Test status
Simulation time 175814536 ps
CPU time 4.38 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:07:25 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569145087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1569145087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.3971156885
Short name T423
Test name
Test status
Simulation time 319473651 ps
CPU time 10.54 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:37 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971156885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.3971156885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1856984264
Short name T643
Test name
Test status
Simulation time 479835805 ps
CPU time 8.01 seconds
Started Aug 27 03:07:20 PM UTC 24
Finished Aug 27 03:07:29 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856984264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1856984264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1786131318
Short name T342
Test name
Test status
Simulation time 9927763083 ps
CPU time 133.48 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:09:41 PM UTC 24
Peak memory 257564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786131318 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.1786131318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.4243330346
Short name T854
Test name
Test status
Simulation time 13824331533 ps
CPU time 138.18 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:09:46 PM UTC 24
Peak memory 274096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4243330346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.otp_ctrl_stress_all_with_rand_reset.4243330346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.326365620
Short name T479
Test name
Test status
Simulation time 12898971573 ps
CPU time 28.87 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:55 PM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326365620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.326365620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.3122634158
Short name T654
Test name
Test status
Simulation time 63376117 ps
CPU time 2.63 seconds
Started Aug 27 03:07:34 PM UTC 24
Finished Aug 27 03:07:38 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122634158 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3122634158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.17743952
Short name T91
Test name
Test status
Simulation time 3342082454 ps
CPU time 19.76 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:07:51 PM UTC 24
Peak memory 251796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17743952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.17743952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.936139791
Short name T684
Test name
Test status
Simulation time 1298998375 ps
CPU time 32.85 seconds
Started Aug 27 03:07:27 PM UTC 24
Finished Aug 27 03:08:01 PM UTC 24
Peak memory 253316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936139791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.936139791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.2756911950
Short name T681
Test name
Test status
Simulation time 2643260321 ps
CPU time 30.18 seconds
Started Aug 27 03:07:27 PM UTC 24
Finished Aug 27 03:07:59 PM UTC 24
Peak memory 253412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756911950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2756911950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.2451035805
Short name T646
Test name
Test status
Simulation time 192664727 ps
CPU time 4.45 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:31 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451035805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2451035805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.4077691992
Short name T249
Test name
Test status
Simulation time 2772487661 ps
CPU time 17.09 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:07:48 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077691992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.4077691992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.875284547
Short name T660
Test name
Test status
Simulation time 1167620969 ps
CPU time 10.45 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:07:41 PM UTC 24
Peak memory 251572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875284547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.875284547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.3953090735
Short name T648
Test name
Test status
Simulation time 368924265 ps
CPU time 4.19 seconds
Started Aug 27 03:07:27 PM UTC 24
Finished Aug 27 03:07:32 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953090735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3953090735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.1885310256
Short name T656
Test name
Test status
Simulation time 850988618 ps
CPU time 11.16 seconds
Started Aug 27 03:07:27 PM UTC 24
Finished Aug 27 03:07:39 PM UTC 24
Peak memory 257316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885310256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1885310256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.979045238
Short name T653
Test name
Test status
Simulation time 353458032 ps
CPU time 6.94 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:07:38 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979045238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.979045238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.1010214941
Short name T650
Test name
Test status
Simulation time 3857079752 ps
CPU time 8.59 seconds
Started Aug 27 03:07:25 PM UTC 24
Finished Aug 27 03:07:35 PM UTC 24
Peak memory 251612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010214941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1010214941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.581067222
Short name T847
Test name
Test status
Simulation time 3805700665 ps
CPU time 128.46 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:09:41 PM UTC 24
Peak memory 269756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581067222 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.581067222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3648619233
Short name T150
Test name
Test status
Simulation time 1240387119 ps
CPU time 44.48 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:08:16 PM UTC 24
Peak memory 257648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3648619233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.otp_ctrl_stress_all_with_rand_reset.3648619233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.1042954286
Short name T664
Test name
Test status
Simulation time 9907692206 ps
CPU time 12.98 seconds
Started Aug 27 03:07:30 PM UTC 24
Finished Aug 27 03:07:44 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042954286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1042954286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.1540054480
Short name T667
Test name
Test status
Simulation time 53063872 ps
CPU time 2.18 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:07:48 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540054480 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1540054480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.185326452
Short name T743
Test name
Test status
Simulation time 4941384438 ps
CPU time 53.9 seconds
Started Aug 27 03:07:37 PM UTC 24
Finished Aug 27 03:08:32 PM UTC 24
Peak memory 253104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185326452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.185326452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.3819274519
Short name T676
Test name
Test status
Simulation time 1161256417 ps
CPU time 19.52 seconds
Started Aug 27 03:07:35 PM UTC 24
Finished Aug 27 03:07:56 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819274519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3819274519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.1707811082
Short name T663
Test name
Test status
Simulation time 358301194 ps
CPU time 8.15 seconds
Started Aug 27 03:07:34 PM UTC 24
Finished Aug 27 03:07:44 PM UTC 24
Peak memory 251644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707811082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1707811082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3105489910
Short name T623
Test name
Test status
Simulation time 2479873188 ps
CPU time 11.51 seconds
Started Aug 27 03:07:34 PM UTC 24
Finished Aug 27 03:07:47 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105489910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3105489910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.1440661781
Short name T693
Test name
Test status
Simulation time 4516208408 ps
CPU time 29.15 seconds
Started Aug 27 03:07:37 PM UTC 24
Finished Aug 27 03:08:07 PM UTC 24
Peak memory 257164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440661781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1440661781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.1780014004
Short name T686
Test name
Test status
Simulation time 2273315071 ps
CPU time 22.96 seconds
Started Aug 27 03:07:39 PM UTC 24
Finished Aug 27 03:08:04 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780014004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1780014004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.1145893711
Short name T659
Test name
Test status
Simulation time 253638078 ps
CPU time 5.15 seconds
Started Aug 27 03:07:34 PM UTC 24
Finished Aug 27 03:07:41 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145893711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1145893711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.1288565455
Short name T670
Test name
Test status
Simulation time 7670385401 ps
CPU time 17.2 seconds
Started Aug 27 03:07:34 PM UTC 24
Finished Aug 27 03:07:53 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288565455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1288565455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.3695463282
Short name T668
Test name
Test status
Simulation time 299867739 ps
CPU time 9 seconds
Started Aug 27 03:07:39 PM UTC 24
Finished Aug 27 03:07:50 PM UTC 24
Peak memory 251244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695463282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3695463282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.3613964827
Short name T672
Test name
Test status
Simulation time 6368224641 ps
CPU time 17.83 seconds
Started Aug 27 03:07:34 PM UTC 24
Finished Aug 27 03:07:54 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613964827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3613964827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3184831732
Short name T677
Test name
Test status
Simulation time 2360573684 ps
CPU time 14.96 seconds
Started Aug 27 03:07:39 PM UTC 24
Finished Aug 27 03:07:56 PM UTC 24
Peak memory 253508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184831732 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3184831732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1216152201
Short name T210
Test name
Test status
Simulation time 42955587498 ps
CPU time 87.95 seconds
Started Aug 27 03:07:39 PM UTC 24
Finished Aug 27 03:09:10 PM UTC 24
Peak memory 268180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1216152201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.otp_ctrl_stress_all_with_rand_reset.1216152201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.2570242851
Short name T680
Test name
Test status
Simulation time 936379386 ps
CPU time 17.26 seconds
Started Aug 27 03:07:39 PM UTC 24
Finished Aug 27 03:07:58 PM UTC 24
Peak memory 251568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570242851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2570242851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.2701407579
Short name T669
Test name
Test status
Simulation time 137768679 ps
CPU time 1.79 seconds
Started Aug 27 03:07:49 PM UTC 24
Finished Aug 27 03:07:51 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701407579 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2701407579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.3489559297
Short name T104
Test name
Test status
Simulation time 807775953 ps
CPU time 17.44 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:08:04 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489559297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3489559297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.155976456
Short name T699
Test name
Test status
Simulation time 793638794 ps
CPU time 23.5 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:08:10 PM UTC 24
Peak memory 253660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155976456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.155976456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.203239130
Short name T742
Test name
Test status
Simulation time 13027049436 ps
CPU time 45.67 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:08:32 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203239130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.203239130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2361462628
Short name T665
Test name
Test status
Simulation time 328868018 ps
CPU time 3.83 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:07:50 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361462628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2361462628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2176589312
Short name T691
Test name
Test status
Simulation time 1619570383 ps
CPU time 19.19 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:08:06 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176589312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2176589312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.2266884783
Short name T692
Test name
Test status
Simulation time 1575642499 ps
CPU time 19.19 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:08:06 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266884783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2266884783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.4154003916
Short name T675
Test name
Test status
Simulation time 526866593 ps
CPU time 8.74 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:07:55 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154003916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4154003916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.1386365029
Short name T689
Test name
Test status
Simulation time 2459103334 ps
CPU time 18.9 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:08:05 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386365029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.1386365029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.4169246574
Short name T674
Test name
Test status
Simulation time 308403720 ps
CPU time 7.42 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:07:54 PM UTC 24
Peak memory 257424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169246574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.4169246574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.254684588
Short name T671
Test name
Test status
Simulation time 385606338 ps
CPU time 7.58 seconds
Started Aug 27 03:07:45 PM UTC 24
Finished Aug 27 03:07:54 PM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254684588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.254684588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.398043746
Short name T744
Test name
Test status
Simulation time 2390033823 ps
CPU time 42.63 seconds
Started Aug 27 03:07:48 PM UTC 24
Finished Aug 27 03:08:33 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398043746 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.398043746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.4053580193
Short name T704
Test name
Test status
Simulation time 10897746905 ps
CPU time 21.67 seconds
Started Aug 27 03:07:48 PM UTC 24
Finished Aug 27 03:08:11 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053580193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.4053580193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.3708863616
Short name T688
Test name
Test status
Simulation time 104185244 ps
CPU time 2.26 seconds
Started Aug 27 03:08:01 PM UTC 24
Finished Aug 27 03:08:05 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708863616 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3708863616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.1367597622
Short name T687
Test name
Test status
Simulation time 412290487 ps
CPU time 11.06 seconds
Started Aug 27 03:07:51 PM UTC 24
Finished Aug 27 03:08:04 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367597622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1367597622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.439522171
Short name T702
Test name
Test status
Simulation time 879969833 ps
CPU time 18.3 seconds
Started Aug 27 03:07:51 PM UTC 24
Finished Aug 27 03:08:11 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439522171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.439522171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.186523020
Short name T679
Test name
Test status
Simulation time 192010717 ps
CPU time 4.35 seconds
Started Aug 27 03:07:51 PM UTC 24
Finished Aug 27 03:07:57 PM UTC 24
Peak memory 257656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186523020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.186523020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.733467225
Short name T673
Test name
Test status
Simulation time 487207762 ps
CPU time 3.93 seconds
Started Aug 27 03:07:49 PM UTC 24
Finished Aug 27 03:07:54 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733467225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.733467225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.2688549744
Short name T700
Test name
Test status
Simulation time 4004289147 ps
CPU time 17.32 seconds
Started Aug 27 03:07:51 PM UTC 24
Finished Aug 27 03:08:10 PM UTC 24
Peak memory 255480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688549744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.2688549744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.3037838737
Short name T719
Test name
Test status
Simulation time 1847805740 ps
CPU time 24.94 seconds
Started Aug 27 03:07:53 PM UTC 24
Finished Aug 27 03:08:20 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037838737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3037838737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.3609866209
Short name T711
Test name
Test status
Simulation time 4920353928 ps
CPU time 22.38 seconds
Started Aug 27 03:07:51 PM UTC 24
Finished Aug 27 03:08:15 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609866209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3609866209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.2075428799
Short name T477
Test name
Test status
Simulation time 950110595 ps
CPU time 11.33 seconds
Started Aug 27 03:07:49 PM UTC 24
Finished Aug 27 03:08:01 PM UTC 24
Peak memory 257372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075428799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2075428799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.1688981874
Short name T682
Test name
Test status
Simulation time 272624164 ps
CPU time 4.33 seconds
Started Aug 27 03:07:53 PM UTC 24
Finished Aug 27 03:07:59 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688981874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1688981874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3737343036
Short name T678
Test name
Test status
Simulation time 1188280031 ps
CPU time 7.01 seconds
Started Aug 27 03:07:49 PM UTC 24
Finished Aug 27 03:07:57 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737343036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3737343036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.2308341365
Short name T243
Test name
Test status
Simulation time 44128689420 ps
CPU time 189.06 seconds
Started Aug 27 03:08:01 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 258760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308341365 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.2308341365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.328194131
Short name T685
Test name
Test status
Simulation time 516747857 ps
CPU time 7.35 seconds
Started Aug 27 03:07:53 PM UTC 24
Finished Aug 27 03:08:02 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328194131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.328194131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.2008320050
Short name T690
Test name
Test status
Simulation time 566294140 ps
CPU time 2.26 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:05 PM UTC 24
Peak memory 251036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008320050 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2008320050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.2821623856
Short name T768
Test name
Test status
Simulation time 3354184860 ps
CPU time 37.27 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:41 PM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821623856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2821623856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1403698828
Short name T740
Test name
Test status
Simulation time 1784736484 ps
CPU time 28.08 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:31 PM UTC 24
Peak memory 253604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403698828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1403698828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.2631906165
Short name T696
Test name
Test status
Simulation time 238953501 ps
CPU time 5.11 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:08 PM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631906165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2631906165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.1301020124
Short name T695
Test name
Test status
Simulation time 384735322 ps
CPU time 5.15 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:08 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301020124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1301020124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.3115883069
Short name T707
Test name
Test status
Simulation time 1080054778 ps
CPU time 10.13 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:13 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115883069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3115883069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.3108634070
Short name T716
Test name
Test status
Simulation time 333053090 ps
CPU time 14.44 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:18 PM UTC 24
Peak memory 253596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108634070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3108634070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.3148246209
Short name T710
Test name
Test status
Simulation time 234311986 ps
CPU time 11.87 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:15 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148246209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3148246209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.1833123361
Short name T717
Test name
Test status
Simulation time 955065774 ps
CPU time 16.54 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:19 PM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833123361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1833123361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.136903091
Short name T705
Test name
Test status
Simulation time 483595068 ps
CPU time 9.49 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:13 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136903091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.136903091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.1877353397
Short name T694
Test name
Test status
Simulation time 576101768 ps
CPU time 5 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:08 PM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877353397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1877353397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3728009826
Short name T730
Test name
Test status
Simulation time 6538148254 ps
CPU time 23.53 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:27 PM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728009826 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3728009826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.827625570
Short name T367
Test name
Test status
Simulation time 45359611311 ps
CPU time 87.95 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:09:32 PM UTC 24
Peak memory 274008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=827625570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
39.otp_ctrl_stress_all_with_rand_reset.827625570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.1575767715
Short name T340
Test name
Test status
Simulation time 1896108896 ps
CPU time 22.88 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:26 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575767715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1575767715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.2325326390
Short name T252
Test name
Test status
Simulation time 143545709 ps
CPU time 2.69 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:03:58 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325326390 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2325326390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1311029824
Short name T120
Test name
Test status
Simulation time 586133739 ps
CPU time 10.62 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:04:04 PM UTC 24
Peak memory 251616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311029824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1311029824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1022456466
Short name T187
Test name
Test status
Simulation time 322277339 ps
CPU time 3.88 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:03:57 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022456466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1022456466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.3951955317
Short name T109
Test name
Test status
Simulation time 3204726505 ps
CPU time 38.78 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:04:33 PM UTC 24
Peak memory 261164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951955317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3951955317
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.2729857038
Short name T254
Test name
Test status
Simulation time 3531747423 ps
CPU time 23.76 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:04:17 PM UTC 24
Peak memory 251644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729857038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2729857038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1788514829
Short name T128
Test name
Test status
Simulation time 124335571 ps
CPU time 3.14 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:03:56 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788514829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1788514829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.3303053499
Short name T176
Test name
Test status
Simulation time 1378853371 ps
CPU time 10.77 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:04:04 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303053499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3303053499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.1073239580
Short name T256
Test name
Test status
Simulation time 2417343405 ps
CPU time 25.76 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:04:21 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073239580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1073239580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.1109697323
Short name T155
Test name
Test status
Simulation time 340292944 ps
CPU time 4.79 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:03:58 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109697323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1109697323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.1515237716
Short name T138
Test name
Test status
Simulation time 5420757833 ps
CPU time 11.75 seconds
Started Aug 27 03:03:52 PM UTC 24
Finished Aug 27 03:04:05 PM UTC 24
Peak memory 251532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515237716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1515237716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.1624900607
Short name T421
Test name
Test status
Simulation time 286787349 ps
CPU time 3.49 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:03:58 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624900607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1624900607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1749623660
Short name T269
Test name
Test status
Simulation time 32017597693 ps
CPU time 184.86 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:07:02 PM UTC 24
Peak memory 288120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749623660 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1749623660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1665484229
Short name T392
Test name
Test status
Simulation time 322848776 ps
CPU time 9.49 seconds
Started Aug 27 03:03:51 PM UTC 24
Finished Aug 27 03:04:01 PM UTC 24
Peak memory 251612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665484229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1665484229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.1210624504
Short name T260
Test name
Test status
Simulation time 41057025233 ps
CPU time 169.65 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:06:46 PM UTC 24
Peak memory 286224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210624504 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.1210624504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.927962566
Short name T226
Test name
Test status
Simulation time 2862399397 ps
CPU time 9.28 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:04:04 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927962566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.927962566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3990413132
Short name T703
Test name
Test status
Simulation time 103618447 ps
CPU time 2.44 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:11 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990413132 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3990413132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.2225846458
Short name T748
Test name
Test status
Simulation time 765562604 ps
CPU time 24.97 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:34 PM UTC 24
Peak memory 253344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225846458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2225846458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.2842981386
Short name T757
Test name
Test status
Simulation time 5018746354 ps
CPU time 28.31 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:37 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842981386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2842981386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.4001625254
Short name T709
Test name
Test status
Simulation time 859591034 ps
CPU time 16.72 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:25 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001625254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.4001625254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.2097955000
Short name T698
Test name
Test status
Simulation time 2592991439 ps
CPU time 5.06 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:08 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097955000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2097955000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.2069335476
Short name T762
Test name
Test status
Simulation time 1549380097 ps
CPU time 30.43 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:39 PM UTC 24
Peak memory 269792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069335476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2069335476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.1629568163
Short name T720
Test name
Test status
Simulation time 1578707447 ps
CPU time 11.3 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:20 PM UTC 24
Peak memory 257784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629568163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1629568163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.3503918810
Short name T712
Test name
Test status
Simulation time 392796863 ps
CPU time 7.61 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:16 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503918810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3503918810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.2774221411
Short name T723
Test name
Test status
Simulation time 8506847872 ps
CPU time 13.98 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:22 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774221411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2774221411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.1556576531
Short name T714
Test name
Test status
Simulation time 305281064 ps
CPU time 8.59 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:17 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556576531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1556576531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.2295710203
Short name T701
Test name
Test status
Simulation time 3077433144 ps
CPU time 7.18 seconds
Started Aug 27 03:08:02 PM UTC 24
Finished Aug 27 03:08:10 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295710203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2295710203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.2865295050
Short name T946
Test name
Test status
Simulation time 7021428148 ps
CPU time 166.87 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:10:57 PM UTC 24
Peak memory 267688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865295050 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.2865295050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.4052421805
Short name T906
Test name
Test status
Simulation time 3999971215 ps
CPU time 148.04 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:10:38 PM UTC 24
Peak memory 257968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4052421805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.otp_ctrl_stress_all_with_rand_reset.4052421805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2676410855
Short name T713
Test name
Test status
Simulation time 894717666 ps
CPU time 7.53 seconds
Started Aug 27 03:08:07 PM UTC 24
Finished Aug 27 03:08:16 PM UTC 24
Peak memory 251108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676410855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2676410855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.525126856
Short name T718
Test name
Test status
Simulation time 96567208 ps
CPU time 2.11 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:20 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525126856 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.525126856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.2971111569
Short name T724
Test name
Test status
Simulation time 408772668 ps
CPU time 5.26 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:22 PM UTC 24
Peak memory 257332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971111569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2971111569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1020541800
Short name T738
Test name
Test status
Simulation time 1585515785 ps
CPU time 12.43 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:30 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020541800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1020541800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.4044031497
Short name T731
Test name
Test status
Simulation time 1677332292 ps
CPU time 10.2 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:27 PM UTC 24
Peak memory 251580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044031497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.4044031497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.3165895393
Short name T789
Test name
Test status
Simulation time 3760979574 ps
CPU time 38.22 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:56 PM UTC 24
Peak memory 257592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165895393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3165895393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.2588325744
Short name T763
Test name
Test status
Simulation time 3877543317 ps
CPU time 21.98 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:39 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588325744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2588325744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.792998269
Short name T770
Test name
Test status
Simulation time 1874556262 ps
CPU time 24.73 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:42 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792998269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.792998269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.1995136837
Short name T734
Test name
Test status
Simulation time 551528014 ps
CPU time 10.55 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:28 PM UTC 24
Peak memory 253592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995136837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1995136837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.3948366327
Short name T721
Test name
Test status
Simulation time 239376123 ps
CPU time 4.39 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:22 PM UTC 24
Peak memory 257424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948366327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3948366327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.3799173057
Short name T715
Test name
Test status
Simulation time 4174795320 ps
CPU time 8.55 seconds
Started Aug 27 03:08:08 PM UTC 24
Finished Aug 27 03:08:17 PM UTC 24
Peak memory 251740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799173057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3799173057
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.4178195469
Short name T919
Test name
Test status
Simulation time 12298523367 ps
CPU time 145.88 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:10:45 PM UTC 24
Peak memory 257880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178195469 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.4178195469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1576575269
Short name T366
Test name
Test status
Simulation time 18543496021 ps
CPU time 50.23 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:09:08 PM UTC 24
Peak memory 257760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1576575269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.otp_ctrl_stress_all_with_rand_reset.1576575269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.564679063
Short name T766
Test name
Test status
Simulation time 2538917986 ps
CPU time 22.81 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:40 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564679063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.564679063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.794263330
Short name T729
Test name
Test status
Simulation time 93710226 ps
CPU time 2.83 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:26 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794263330 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.794263330
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.3370485195
Short name T726
Test name
Test status
Simulation time 1108439905 ps
CPU time 5.95 seconds
Started Aug 27 03:08:17 PM UTC 24
Finished Aug 27 03:08:24 PM UTC 24
Peak memory 251048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370485195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3370485195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.4025151038
Short name T206
Test name
Test status
Simulation time 1653024341 ps
CPU time 41.37 seconds
Started Aug 27 03:08:17 PM UTC 24
Finished Aug 27 03:08:59 PM UTC 24
Peak memory 261880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025151038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.4025151038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.198655905
Short name T481
Test name
Test status
Simulation time 8125419063 ps
CPU time 11.65 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:29 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198655905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.198655905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.14180851
Short name T751
Test name
Test status
Simulation time 1561307469 ps
CPU time 16.57 seconds
Started Aug 27 03:08:17 PM UTC 24
Finished Aug 27 03:08:35 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14180851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.14180851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.1971197503
Short name T725
Test name
Test status
Simulation time 421138888 ps
CPU time 5 seconds
Started Aug 27 03:08:17 PM UTC 24
Finished Aug 27 03:08:23 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971197503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.1971197503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.1764894224
Short name T746
Test name
Test status
Simulation time 264228535 ps
CPU time 15.4 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:33 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764894224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1764894224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.2701246250
Short name T728
Test name
Test status
Simulation time 305345870 ps
CPU time 7.65 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:25 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701246250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.2701246250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.1642282970
Short name T733
Test name
Test status
Simulation time 539209514 ps
CPU time 5.09 seconds
Started Aug 27 03:08:21 PM UTC 24
Finished Aug 27 03:08:28 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642282970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1642282970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.2537328802
Short name T727
Test name
Test status
Simulation time 599956439 ps
CPU time 7.17 seconds
Started Aug 27 03:08:16 PM UTC 24
Finished Aug 27 03:08:25 PM UTC 24
Peak memory 257564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537328802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2537328802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.1135958274
Short name T1015
Test name
Test status
Simulation time 14713215328 ps
CPU time 177.15 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:11:22 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135958274 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.1135958274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.309098940
Short name T458
Test name
Test status
Simulation time 20058953621 ps
CPU time 42.16 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:09:05 PM UTC 24
Peak memory 267888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=309098940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
42.otp_ctrl_stress_all_with_rand_reset.309098940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.2645700489
Short name T771
Test name
Test status
Simulation time 3067054501 ps
CPU time 23.91 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:47 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645700489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2645700489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.8715582
Short name T737
Test name
Test status
Simulation time 777246357 ps
CPU time 2.63 seconds
Started Aug 27 03:08:25 PM UTC 24
Finished Aug 27 03:08:29 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8715582 -assert nopostproc +UVM_TESTNAME=otp_
ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.8715582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.2769258108
Short name T735
Test name
Test status
Simulation time 418997711 ps
CPU time 4.69 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:28 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769258108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.2769258108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.1923575381
Short name T747
Test name
Test status
Simulation time 286873212 ps
CPU time 10.33 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:33 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923575381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1923575381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.4069450882
Short name T800
Test name
Test status
Simulation time 5865094671 ps
CPU time 38.56 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:09:02 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069450882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.4069450882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.3418515953
Short name T732
Test name
Test status
Simulation time 154502563 ps
CPU time 4.43 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:27 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418515953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3418515953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.3943393310
Short name T752
Test name
Test status
Simulation time 2162469915 ps
CPU time 11.74 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:35 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943393310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3943393310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.4210663454
Short name T764
Test name
Test status
Simulation time 906236470 ps
CPU time 16.76 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:40 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210663454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.4210663454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.2825930979
Short name T749
Test name
Test status
Simulation time 1626259267 ps
CPU time 11.08 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:34 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825930979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2825930979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.3581560891
Short name T741
Test name
Test status
Simulation time 291980738 ps
CPU time 8.31 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:31 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581560891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3581560891
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.90677872
Short name T750
Test name
Test status
Simulation time 3600813316 ps
CPU time 8.66 seconds
Started Aug 27 03:08:25 PM UTC 24
Finished Aug 27 03:08:34 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90677872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ot
p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.90677872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.1269416986
Short name T736
Test name
Test status
Simulation time 1851504144 ps
CPU time 5.08 seconds
Started Aug 27 03:08:22 PM UTC 24
Finished Aug 27 03:08:28 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269416986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1269416986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.1894069015
Short name T149
Test name
Test status
Simulation time 38588302323 ps
CPU time 74.98 seconds
Started Aug 27 03:08:25 PM UTC 24
Finished Aug 27 03:09:42 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894069015 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.1894069015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3185943518
Short name T1006
Test name
Test status
Simulation time 4812115466 ps
CPU time 172.61 seconds
Started Aug 27 03:08:25 PM UTC 24
Finished Aug 27 03:11:20 PM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3185943518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.otp_ctrl_stress_all_with_rand_reset.3185943518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.2598337740
Short name T201
Test name
Test status
Simulation time 828654426 ps
CPU time 17.02 seconds
Started Aug 27 03:08:25 PM UTC 24
Finished Aug 27 03:08:43 PM UTC 24
Peak memory 257776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598337740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2598337740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.3029215413
Short name T753
Test name
Test status
Simulation time 59323915 ps
CPU time 2.49 seconds
Started Aug 27 03:08:32 PM UTC 24
Finished Aug 27 03:08:35 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029215413 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3029215413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.2981073798
Short name T760
Test name
Test status
Simulation time 496563728 ps
CPU time 5.65 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:38 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981073798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2981073798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.3452113664
Short name T208
Test name
Test status
Simulation time 982161868 ps
CPU time 13.51 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:46 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452113664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3452113664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2893312890
Short name T782
Test name
Test status
Simulation time 1631310865 ps
CPU time 19.65 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:52 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893312890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2893312890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.1558319692
Short name T755
Test name
Test status
Simulation time 158661154 ps
CPU time 3.64 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:36 PM UTC 24
Peak memory 251136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558319692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1558319692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.2672860159
Short name T775
Test name
Test status
Simulation time 456510694 ps
CPU time 15.43 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:48 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672860159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2672860159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.670625782
Short name T754
Test name
Test status
Simulation time 234842017 ps
CPU time 3 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:35 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670625782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.670625782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.1330201079
Short name T205
Test name
Test status
Simulation time 1372594109 ps
CPU time 13.15 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:45 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330201079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1330201079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.1345764744
Short name T761
Test name
Test status
Simulation time 383174470 ps
CPU time 6.3 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:39 PM UTC 24
Peak memory 250856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345764744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1345764744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.3286498890
Short name T758
Test name
Test status
Simulation time 271564880 ps
CPU time 4.68 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:37 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286498890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3286498890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.573073112
Short name T756
Test name
Test status
Simulation time 3505350182 ps
CPU time 10.57 seconds
Started Aug 27 03:08:25 PM UTC 24
Finished Aug 27 03:08:37 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573073112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.573073112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.1116636543
Short name T474
Test name
Test status
Simulation time 2065281035 ps
CPU time 32.01 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:09:05 PM UTC 24
Peak memory 255356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116636543 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.1116636543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.760977673
Short name T776
Test name
Test status
Simulation time 10624948770 ps
CPU time 15.95 seconds
Started Aug 27 03:08:31 PM UTC 24
Finished Aug 27 03:08:49 PM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760977673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.760977673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.1800901145
Short name T767
Test name
Test status
Simulation time 138206390 ps
CPU time 2.55 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:40 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800901145 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1800901145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.1092566479
Short name T73
Test name
Test status
Simulation time 1256519956 ps
CPU time 18.6 seconds
Started Aug 27 03:08:36 PM UTC 24
Finished Aug 27 03:08:56 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092566479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1092566479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.957443301
Short name T780
Test name
Test status
Simulation time 494214717 ps
CPU time 13.54 seconds
Started Aug 27 03:08:36 PM UTC 24
Finished Aug 27 03:08:51 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957443301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.957443301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.450671068
Short name T203
Test name
Test status
Simulation time 3872683095 ps
CPU time 6.91 seconds
Started Aug 27 03:08:36 PM UTC 24
Finished Aug 27 03:08:44 PM UTC 24
Peak memory 253500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450671068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.450671068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.4285473711
Short name T759
Test name
Test status
Simulation time 389630017 ps
CPU time 4.43 seconds
Started Aug 27 03:08:32 PM UTC 24
Finished Aug 27 03:08:37 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285473711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.4285473711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.3402796301
Short name T745
Test name
Test status
Simulation time 11869693745 ps
CPU time 21.3 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:59 PM UTC 24
Peak memory 257628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402796301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3402796301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.3638539132
Short name T787
Test name
Test status
Simulation time 444478323 ps
CPU time 17.54 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:55 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638539132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3638539132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3507293899
Short name T774
Test name
Test status
Simulation time 6657264274 ps
CPU time 14.64 seconds
Started Aug 27 03:08:32 PM UTC 24
Finished Aug 27 03:08:48 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507293899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3507293899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.3888134102
Short name T786
Test name
Test status
Simulation time 8285880095 ps
CPU time 20.91 seconds
Started Aug 27 03:08:32 PM UTC 24
Finished Aug 27 03:08:54 PM UTC 24
Peak memory 257588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888134102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3888134102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.1215256349
Short name T772
Test name
Test status
Simulation time 558872852 ps
CPU time 9.07 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:47 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215256349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1215256349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.1690270557
Short name T765
Test name
Test status
Simulation time 378755510 ps
CPU time 7.4 seconds
Started Aug 27 03:08:32 PM UTC 24
Finished Aug 27 03:08:40 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690270557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.1690270557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.2960716969
Short name T888
Test name
Test status
Simulation time 8218284344 ps
CPU time 101.73 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:10:21 PM UTC 24
Peak memory 271920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960716969 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.2960716969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.427425548
Short name T24
Test name
Test status
Simulation time 14070950953 ps
CPU time 125.82 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:10:45 PM UTC 24
Peak memory 267864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=427425548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
45.otp_ctrl_stress_all_with_rand_reset.427425548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.4278962224
Short name T783
Test name
Test status
Simulation time 816366369 ps
CPU time 14.45 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:52 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278962224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4278962224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.2945498807
Short name T204
Test name
Test status
Simulation time 173543342 ps
CPU time 2.63 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:08:45 PM UTC 24
Peak memory 250964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945498807 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2945498807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.1487233251
Short name T811
Test name
Test status
Simulation time 11619709032 ps
CPU time 30.74 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:09:09 PM UTC 24
Peak memory 253688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487233251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1487233251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.4275526133
Short name T777
Test name
Test status
Simulation time 871712714 ps
CPU time 10.72 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:49 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275526133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.4275526133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.764630365
Short name T804
Test name
Test status
Simulation time 2074071788 ps
CPU time 28.34 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:09:07 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764630365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.764630365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.3548065901
Short name T102
Test name
Test status
Simulation time 144164523 ps
CPU time 4.02 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:42 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548065901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3548065901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.2981352947
Short name T817
Test name
Test status
Simulation time 1910878013 ps
CPU time 37.03 seconds
Started Aug 27 03:08:39 PM UTC 24
Finished Aug 27 03:09:17 PM UTC 24
Peak memory 257532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981352947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2981352947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1936340279
Short name T802
Test name
Test status
Simulation time 10909272873 ps
CPU time 25.41 seconds
Started Aug 27 03:08:39 PM UTC 24
Finished Aug 27 03:09:05 PM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936340279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1936340279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.1198211428
Short name T769
Test name
Test status
Simulation time 94870732 ps
CPU time 2.65 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:41 PM UTC 24
Peak memory 251096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198211428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1198211428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.254167289
Short name T207
Test name
Test status
Simulation time 429675009 ps
CPU time 7.65 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:46 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254167289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.254167289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.1046607495
Short name T424
Test name
Test status
Simulation time 794091359 ps
CPU time 7.36 seconds
Started Aug 27 03:08:39 PM UTC 24
Finished Aug 27 03:08:47 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046607495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1046607495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.3137675950
Short name T202
Test name
Test status
Simulation time 227795657 ps
CPU time 5.66 seconds
Started Aug 27 03:08:37 PM UTC 24
Finished Aug 27 03:08:44 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137675950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3137675950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.4077557630
Short name T1102
Test name
Test status
Simulation time 14415500084 ps
CPU time 182.37 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:11:47 PM UTC 24
Peak memory 274136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077557630 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.4077557630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3461564642
Short name T879
Test name
Test status
Simulation time 3429450659 ps
CPU time 93.59 seconds
Started Aug 27 03:08:39 PM UTC 24
Finished Aug 27 03:10:14 PM UTC 24
Peak memory 272088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3461564642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.otp_ctrl_stress_all_with_rand_reset.3461564642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.4228658502
Short name T795
Test name
Test status
Simulation time 7862869496 ps
CPU time 19.69 seconds
Started Aug 27 03:08:39 PM UTC 24
Finished Aug 27 03:09:00 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228658502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.4228658502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.3269582648
Short name T779
Test name
Test status
Simulation time 108937842 ps
CPU time 2.69 seconds
Started Aug 27 03:08:47 PM UTC 24
Finished Aug 27 03:08:51 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269582648 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3269582648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.2722773013
Short name T797
Test name
Test status
Simulation time 723357686 ps
CPU time 15.28 seconds
Started Aug 27 03:08:44 PM UTC 24
Finished Aug 27 03:09:00 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722773013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.2722773013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.1538831030
Short name T785
Test name
Test status
Simulation time 752359283 ps
CPU time 10.59 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:08:53 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538831030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1538831030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.3459412582
Short name T812
Test name
Test status
Simulation time 11556997360 ps
CPU time 33.49 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:09:16 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459412582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3459412582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.3331614688
Short name T209
Test name
Test status
Simulation time 95614909 ps
CPU time 4.07 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:08:46 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331614688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3331614688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.2653547145
Short name T798
Test name
Test status
Simulation time 813343623 ps
CPU time 15.61 seconds
Started Aug 27 03:08:44 PM UTC 24
Finished Aug 27 03:09:00 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653547145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2653547145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.2635598803
Short name T790
Test name
Test status
Simulation time 326106393 ps
CPU time 11.25 seconds
Started Aug 27 03:08:44 PM UTC 24
Finished Aug 27 03:08:56 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635598803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2635598803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.1776726643
Short name T792
Test name
Test status
Simulation time 276712423 ps
CPU time 15.9 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:08:58 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776726643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1776726643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.2503029941
Short name T466
Test name
Test status
Simulation time 639539765 ps
CPU time 18.91 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:09:01 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503029941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2503029941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.2043777106
Short name T778
Test name
Test status
Simulation time 387444522 ps
CPU time 4.53 seconds
Started Aug 27 03:08:44 PM UTC 24
Finished Aug 27 03:08:49 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043777106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2043777106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.3038683589
Short name T773
Test name
Test status
Simulation time 185525126 ps
CPU time 5.19 seconds
Started Aug 27 03:08:41 PM UTC 24
Finished Aug 27 03:08:47 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038683589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3038683589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.767851543
Short name T343
Test name
Test status
Simulation time 10983961544 ps
CPU time 130.03 seconds
Started Aug 27 03:08:45 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 257880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767851543 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.767851543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.1491225669
Short name T781
Test name
Test status
Simulation time 191172254 ps
CPU time 5.05 seconds
Started Aug 27 03:08:45 PM UTC 24
Finished Aug 27 03:08:51 PM UTC 24
Peak memory 257456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491225669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1491225669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.1661329157
Short name T791
Test name
Test status
Simulation time 75660254 ps
CPU time 2.89 seconds
Started Aug 27 03:08:53 PM UTC 24
Finished Aug 27 03:08:57 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661329157 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1661329157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.1393526914
Short name T801
Test name
Test status
Simulation time 1706601542 ps
CPU time 10.74 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:03 PM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393526914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1393526914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.3177168953
Short name T211
Test name
Test status
Simulation time 1361440468 ps
CPU time 22.21 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:14 PM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177168953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3177168953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.3562291625
Short name T803
Test name
Test status
Simulation time 479012095 ps
CPU time 14.61 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:06 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562291625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.3562291625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.3788223202
Short name T784
Test name
Test status
Simulation time 170671156 ps
CPU time 4.38 seconds
Started Aug 27 03:08:47 PM UTC 24
Finished Aug 27 03:08:53 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788223202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3788223202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.401340110
Short name T796
Test name
Test status
Simulation time 344724047 ps
CPU time 7.8 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:00 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401340110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.401340110
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.1980646123
Short name T805
Test name
Test status
Simulation time 1942153655 ps
CPU time 14.73 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:07 PM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980646123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1980646123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.901207199
Short name T794
Test name
Test status
Simulation time 2428169550 ps
CPU time 7.61 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:08:59 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901207199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.901207199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.3549052263
Short name T475
Test name
Test status
Simulation time 680714398 ps
CPU time 10.82 seconds
Started Aug 27 03:08:47 PM UTC 24
Finished Aug 27 03:08:59 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549052263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3549052263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.1888786192
Short name T799
Test name
Test status
Simulation time 308148305 ps
CPU time 9.79 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:02 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888786192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1888786192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.181060857
Short name T788
Test name
Test status
Simulation time 281012867 ps
CPU time 6.88 seconds
Started Aug 27 03:08:47 PM UTC 24
Finished Aug 27 03:08:55 PM UTC 24
Peak memory 257696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181060857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.181060857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.2280347821
Short name T885
Test name
Test status
Simulation time 10701263851 ps
CPU time 95.12 seconds
Started Aug 27 03:08:53 PM UTC 24
Finished Aug 27 03:10:30 PM UTC 24
Peak memory 255420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280347821 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.2280347821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.1930270862
Short name T341
Test name
Test status
Simulation time 207668480 ps
CPU time 7.86 seconds
Started Aug 27 03:08:51 PM UTC 24
Finished Aug 27 03:09:00 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930270862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1930270862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.4054728497
Short name T806
Test name
Test status
Simulation time 98479828 ps
CPU time 2.42 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:09:07 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054728497 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.4054728497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.1502974607
Short name T830
Test name
Test status
Simulation time 1553365738 ps
CPU time 23.51 seconds
Started Aug 27 03:08:59 PM UTC 24
Finished Aug 27 03:09:24 PM UTC 24
Peak memory 253624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502974607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1502974607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.3997835741
Short name T214
Test name
Test status
Simulation time 9237088146 ps
CPU time 18.76 seconds
Started Aug 27 03:08:56 PM UTC 24
Finished Aug 27 03:09:15 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997835741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3997835741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.1751033221
Short name T814
Test name
Test status
Simulation time 1302872513 ps
CPU time 19.83 seconds
Started Aug 27 03:08:56 PM UTC 24
Finished Aug 27 03:09:17 PM UTC 24
Peak memory 257532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751033221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1751033221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.3788789350
Short name T40
Test name
Test status
Simulation time 223416395 ps
CPU time 5.55 seconds
Started Aug 27 03:08:55 PM UTC 24
Finished Aug 27 03:09:02 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788789350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3788789350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.31038016
Short name T831
Test name
Test status
Simulation time 7517176051 ps
CPU time 23.48 seconds
Started Aug 27 03:08:59 PM UTC 24
Finished Aug 27 03:09:24 PM UTC 24
Peak memory 255572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31038016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.31038016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.1536006408
Short name T456
Test name
Test status
Simulation time 787119239 ps
CPU time 25.2 seconds
Started Aug 27 03:08:59 PM UTC 24
Finished Aug 27 03:09:26 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536006408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1536006408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.3445101035
Short name T810
Test name
Test status
Simulation time 236089880 ps
CPU time 12 seconds
Started Aug 27 03:08:55 PM UTC 24
Finished Aug 27 03:09:09 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445101035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3445101035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.956133248
Short name T824
Test name
Test status
Simulation time 894511983 ps
CPU time 23.32 seconds
Started Aug 27 03:08:55 PM UTC 24
Finished Aug 27 03:09:20 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956133248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.956133248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.930792642
Short name T425
Test name
Test status
Simulation time 622718968 ps
CPU time 9.13 seconds
Started Aug 27 03:08:59 PM UTC 24
Finished Aug 27 03:09:09 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930792642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.930792642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.340906273
Short name T739
Test name
Test status
Simulation time 203395719 ps
CPU time 5.19 seconds
Started Aug 27 03:08:53 PM UTC 24
Finished Aug 27 03:08:59 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340906273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.340906273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.2394181393
Short name T1061
Test name
Test status
Simulation time 18377572639 ps
CPU time 148.96 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:11:35 PM UTC 24
Peak memory 255420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394181393 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.2394181393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.2982081576
Short name T827
Test name
Test status
Simulation time 2055433555 ps
CPU time 21.36 seconds
Started Aug 27 03:08:59 PM UTC 24
Finished Aug 27 03:09:22 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982081576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.2982081576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.3351085569
Short name T143
Test name
Test status
Simulation time 2044275063 ps
CPU time 25.24 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:04:21 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351085569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3351085569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.592996312
Short name T111
Test name
Test status
Simulation time 1673707368 ps
CPU time 35.66 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:34 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592996312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.592996312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.2309821299
Short name T228
Test name
Test status
Simulation time 1983306467 ps
CPU time 24.89 seconds
Started Aug 27 03:03:56 PM UTC 24
Finished Aug 27 03:04:22 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309821299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2309821299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.3431017699
Short name T172
Test name
Test status
Simulation time 14610360319 ps
CPU time 132.58 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:06:12 PM UTC 24
Peak memory 267868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431017699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3431017699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.3495060294
Short name T174
Test name
Test status
Simulation time 648771125 ps
CPU time 8.8 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:07 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495060294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3495060294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.431805638
Short name T291
Test name
Test status
Simulation time 1031134404 ps
CPU time 28.81 seconds
Started Aug 27 03:03:54 PM UTC 24
Finished Aug 27 03:04:24 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431805638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.431805638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.1978279346
Short name T395
Test name
Test status
Simulation time 388578475 ps
CPU time 4.8 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:03 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978279346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1978279346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.1532750954
Short name T319
Test name
Test status
Simulation time 1236936319 ps
CPU time 13.71 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:12 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532750954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1532750954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.1262686074
Short name T103
Test name
Test status
Simulation time 103626538 ps
CPU time 4.77 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:09:10 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262686074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1262686074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.3863353490
Short name T161
Test name
Test status
Simulation time 211239441 ps
CPU time 5.38 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:09:10 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863353490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3863353490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3121407107
Short name T375
Test name
Test status
Simulation time 42553864330 ps
CPU time 87.67 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:10:34 PM UTC 24
Peak memory 268088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3121407107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 50.otp_ctrl_stress_all_with_rand_reset.3121407107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.3899529100
Short name T808
Test name
Test status
Simulation time 197789764 ps
CPU time 3.18 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:09:08 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899529100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3899529100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.1776908525
Short name T809
Test name
Test status
Simulation time 224822106 ps
CPU time 3.52 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:09:09 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776908525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1776908525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1970049188
Short name T882
Test name
Test status
Simulation time 4855386617 ps
CPU time 71.36 seconds
Started Aug 27 03:09:03 PM UTC 24
Finished Aug 27 03:10:17 PM UTC 24
Peak memory 267836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1970049188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 51.otp_ctrl_stress_all_with_rand_reset.1970049188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.1541030101
Short name T45
Test name
Test status
Simulation time 116162206 ps
CPU time 4.16 seconds
Started Aug 27 03:09:04 PM UTC 24
Finished Aug 27 03:09:09 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541030101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1541030101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.1424161869
Short name T836
Test name
Test status
Simulation time 3817606172 ps
CPU time 22.64 seconds
Started Aug 27 03:09:04 PM UTC 24
Finished Aug 27 03:09:28 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424161869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1424161869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.1624866429
Short name T41
Test name
Test status
Simulation time 2389759592 ps
CPU time 5.8 seconds
Started Aug 27 03:09:04 PM UTC 24
Finished Aug 27 03:09:11 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624866429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1624866429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.467488423
Short name T807
Test name
Test status
Simulation time 213666660 ps
CPU time 2.79 seconds
Started Aug 27 03:09:04 PM UTC 24
Finished Aug 27 03:09:08 PM UTC 24
Peak memory 251120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467488423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.467488423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.726136120
Short name T162
Test name
Test status
Simulation time 4659825298 ps
CPU time 86.24 seconds
Started Aug 27 03:09:05 PM UTC 24
Finished Aug 27 03:10:34 PM UTC 24
Peak memory 268212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=726136120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
53.otp_ctrl_stress_all_with_rand_reset.726136120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.4105470140
Short name T56
Test name
Test status
Simulation time 132523227 ps
CPU time 4.09 seconds
Started Aug 27 03:09:06 PM UTC 24
Finished Aug 27 03:09:11 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105470140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.4105470140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.1414495807
Short name T212
Test name
Test status
Simulation time 1331643825 ps
CPU time 7.55 seconds
Started Aug 27 03:09:06 PM UTC 24
Finished Aug 27 03:09:15 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414495807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1414495807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.76450854
Short name T953
Test name
Test status
Simulation time 8866870304 ps
CPU time 105.67 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:10:59 PM UTC 24
Peak memory 274108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=76450854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
54.otp_ctrl_stress_all_with_rand_reset.76450854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.1490592023
Short name T813
Test name
Test status
Simulation time 260714673 ps
CPU time 4.32 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:16 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490592023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1490592023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.1207912236
Short name T815
Test name
Test status
Simulation time 288745004 ps
CPU time 4.76 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:17 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207912236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1207912236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.1999764832
Short name T819
Test name
Test status
Simulation time 343685667 ps
CPU time 5.81 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:18 PM UTC 24
Peak memory 251144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999764832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1999764832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.2062303650
Short name T825
Test name
Test status
Simulation time 2212448101 ps
CPU time 8.69 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:21 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062303650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2062303650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.48182908
Short name T816
Test name
Test status
Simulation time 391973669 ps
CPU time 4.55 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:17 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48182908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.48182908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.3162349268
Short name T290
Test name
Test status
Simulation time 1894659505 ps
CPU time 13.44 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:26 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162349268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3162349268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.916925985
Short name T900
Test name
Test status
Simulation time 21102346364 ps
CPU time 81.57 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:10:35 PM UTC 24
Peak memory 267952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=916925985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
57.otp_ctrl_stress_all_with_rand_reset.916925985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.1548311569
Short name T818
Test name
Test status
Simulation time 143375446 ps
CPU time 5.44 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:18 PM UTC 24
Peak memory 251436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548311569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1548311569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.4066035501
Short name T853
Test name
Test status
Simulation time 16186302391 ps
CPU time 32.53 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:45 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066035501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.4066035501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3201175920
Short name T1179
Test name
Test status
Simulation time 19915499242 ps
CPU time 199.24 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:12:34 PM UTC 24
Peak memory 268052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3201175920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 58.otp_ctrl_stress_all_with_rand_reset.3201175920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.3659785477
Short name T215
Test name
Test status
Simulation time 210622225 ps
CPU time 3.31 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:16 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659785477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3659785477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.989027407
Short name T821
Test name
Test status
Simulation time 130549322 ps
CPU time 6.05 seconds
Started Aug 27 03:09:11 PM UTC 24
Finished Aug 27 03:09:19 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989027407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.989027407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.672134692
Short name T873
Test name
Test status
Simulation time 3000138704 ps
CPU time 57.56 seconds
Started Aug 27 03:09:13 PM UTC 24
Finished Aug 27 03:10:12 PM UTC 24
Peak memory 257968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=672134692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
59.otp_ctrl_stress_all_with_rand_reset.672134692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.1092748593
Short name T486
Test name
Test status
Simulation time 704536968 ps
CPU time 3.35 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:10 PM UTC 24
Peak memory 251076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092748593 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1092748593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.2019918091
Short name T136
Test name
Test status
Simulation time 223758604 ps
CPU time 6.23 seconds
Started Aug 27 03:03:58 PM UTC 24
Finished Aug 27 03:04:05 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019918091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2019918091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.3020023966
Short name T57
Test name
Test status
Simulation time 703508123 ps
CPU time 9.46 seconds
Started Aug 27 03:03:59 PM UTC 24
Finished Aug 27 03:04:10 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020023966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3020023966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.3365070381
Short name T233
Test name
Test status
Simulation time 5184523942 ps
CPU time 23.2 seconds
Started Aug 27 03:03:59 PM UTC 24
Finished Aug 27 03:04:23 PM UTC 24
Peak memory 251084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365070381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3365070381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.2211306297
Short name T454
Test name
Test status
Simulation time 1779324330 ps
CPU time 24.77 seconds
Started Aug 27 03:03:59 PM UTC 24
Finished Aug 27 03:04:25 PM UTC 24
Peak memory 253336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211306297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2211306297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1250351096
Short name T184
Test name
Test status
Simulation time 113711512 ps
CPU time 4.89 seconds
Started Aug 27 03:03:58 PM UTC 24
Finished Aug 27 03:04:04 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250351096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1250351096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.1663666276
Short name T283
Test name
Test status
Simulation time 19533021033 ps
CPU time 38.15 seconds
Started Aug 27 03:04:02 PM UTC 24
Finished Aug 27 03:04:42 PM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663666276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1663666276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.911940806
Short name T156
Test name
Test status
Simulation time 214001326 ps
CPU time 4.66 seconds
Started Aug 27 03:03:59 PM UTC 24
Finished Aug 27 03:04:05 PM UTC 24
Peak memory 251028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911940806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.911940806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.348486314
Short name T394
Test name
Test status
Simulation time 124237247 ps
CPU time 4.22 seconds
Started Aug 27 03:03:57 PM UTC 24
Finished Aug 27 03:04:03 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348486314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.348486314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1450912467
Short name T452
Test name
Test status
Simulation time 20412900720 ps
CPU time 239.74 seconds
Started Aug 27 03:04:03 PM UTC 24
Finished Aug 27 03:08:06 PM UTC 24
Peak memory 271048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450912467 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1450912467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.2567480551
Short name T113
Test name
Test status
Simulation time 4780760919 ps
CPU time 30.78 seconds
Started Aug 27 03:04:03 PM UTC 24
Finished Aug 27 03:04:35 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567480551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2567480551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.1830511854
Short name T822
Test name
Test status
Simulation time 269706967 ps
CPU time 4.67 seconds
Started Aug 27 03:09:13 PM UTC 24
Finished Aug 27 03:09:19 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830511854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1830511854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.954530763
Short name T823
Test name
Test status
Simulation time 248510279 ps
CPU time 5.57 seconds
Started Aug 27 03:09:13 PM UTC 24
Finished Aug 27 03:09:20 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954530763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.954530763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.463323964
Short name T820
Test name
Test status
Simulation time 141237727 ps
CPU time 4.04 seconds
Started Aug 27 03:09:13 PM UTC 24
Finished Aug 27 03:09:18 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463323964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.463323964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.1804188994
Short name T835
Test name
Test status
Simulation time 429061515 ps
CPU time 13.03 seconds
Started Aug 27 03:09:13 PM UTC 24
Finished Aug 27 03:09:27 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804188994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1804188994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3409075269
Short name T970
Test name
Test status
Simulation time 16414499670 ps
CPU time 106.85 seconds
Started Aug 27 03:09:16 PM UTC 24
Finished Aug 27 03:11:05 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3409075269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 61.otp_ctrl_stress_all_with_rand_reset.3409075269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.174539486
Short name T828
Test name
Test status
Simulation time 170089801 ps
CPU time 4.53 seconds
Started Aug 27 03:09:16 PM UTC 24
Finished Aug 27 03:09:22 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174539486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.174539486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.2103156460
Short name T829
Test name
Test status
Simulation time 123631364 ps
CPU time 4.47 seconds
Started Aug 27 03:09:17 PM UTC 24
Finished Aug 27 03:09:22 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103156460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2103156460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.148768059
Short name T1169
Test name
Test status
Simulation time 61806344617 ps
CPU time 160.73 seconds
Started Aug 27 03:09:17 PM UTC 24
Finished Aug 27 03:12:00 PM UTC 24
Peak memory 274204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=148768059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
62.otp_ctrl_stress_all_with_rand_reset.148768059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.3160772998
Short name T826
Test name
Test status
Simulation time 126538357 ps
CPU time 3.79 seconds
Started Aug 27 03:09:17 PM UTC 24
Finished Aug 27 03:09:21 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160772998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3160772998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.2003943679
Short name T834
Test name
Test status
Simulation time 170160650 ps
CPU time 7.25 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:09:27 PM UTC 24
Peak memory 250748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003943679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2003943679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.3280644324
Short name T956
Test name
Test status
Simulation time 7306290645 ps
CPU time 98.6 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:11:00 PM UTC 24
Peak memory 267664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3280644324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 63.otp_ctrl_stress_all_with_rand_reset.3280644324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.1070931634
Short name T74
Test name
Test status
Simulation time 385619634 ps
CPU time 6.92 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:09:27 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070931634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1070931634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.603959179
Short name T837
Test name
Test status
Simulation time 807300855 ps
CPU time 11.85 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:09:32 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603959179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.603959179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3473458325
Short name T994
Test name
Test status
Simulation time 43697551559 ps
CPU time 114.57 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:11:16 PM UTC 24
Peak memory 267860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3473458325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 64.otp_ctrl_stress_all_with_rand_reset.3473458325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.965298092
Short name T832
Test name
Test status
Simulation time 165845791 ps
CPU time 4.28 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:09:24 PM UTC 24
Peak memory 251396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965298092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.965298092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.3292203265
Short name T833
Test name
Test status
Simulation time 232463385 ps
CPU time 5.03 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:09:25 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292203265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3292203265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2748974437
Short name T23
Test name
Test status
Simulation time 2336700622 ps
CPU time 61.21 seconds
Started Aug 27 03:09:19 PM UTC 24
Finished Aug 27 03:10:22 PM UTC 24
Peak memory 257684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2748974437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 65.otp_ctrl_stress_all_with_rand_reset.2748974437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3398050676
Short name T42
Test name
Test status
Simulation time 201984124 ps
CPU time 5.55 seconds
Started Aug 27 03:09:20 PM UTC 24
Finished Aug 27 03:09:27 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398050676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3398050676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.932563735
Short name T871
Test name
Test status
Simulation time 6610356125 ps
CPU time 46.92 seconds
Started Aug 27 03:09:20 PM UTC 24
Finished Aug 27 03:10:09 PM UTC 24
Peak memory 268212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=932563735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
66.otp_ctrl_stress_all_with_rand_reset.932563735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.1569210508
Short name T838
Test name
Test status
Simulation time 224497678 ps
CPU time 5.93 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:36 PM UTC 24
Peak memory 250836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569210508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.1569210508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.2066829537
Short name T843
Test name
Test status
Simulation time 259724757 ps
CPU time 6.45 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:37 PM UTC 24
Peak memory 250752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066829537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2066829537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2935775459
Short name T379
Test name
Test status
Simulation time 10499451613 ps
CPU time 91.21 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:11:02 PM UTC 24
Peak memory 257684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2935775459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 67.otp_ctrl_stress_all_with_rand_reset.2935775459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.3150157372
Short name T793
Test name
Test status
Simulation time 1820757143 ps
CPU time 5.84 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:36 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150157372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3150157372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.3039375220
Short name T846
Test name
Test status
Simulation time 2277650705 ps
CPU time 8.84 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:39 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039375220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3039375220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.1616812807
Short name T46
Test name
Test status
Simulation time 526377178 ps
CPU time 3.77 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:34 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616812807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1616812807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.1176442078
Short name T839
Test name
Test status
Simulation time 261029893 ps
CPU time 4.66 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:35 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176442078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1176442078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.148730847
Short name T1032
Test name
Test status
Simulation time 45108130002 ps
CPU time 117.76 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:11:29 PM UTC 24
Peak memory 267820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=148730847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
69.otp_ctrl_stress_all_with_rand_reset.148730847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.1367970109
Short name T488
Test name
Test status
Simulation time 81728183 ps
CPU time 2.36 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:14 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367970109 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1367970109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.3828037674
Short name T137
Test name
Test status
Simulation time 4087521191 ps
CPU time 23.14 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:30 PM UTC 24
Peak memory 253684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828037674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3828037674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.3082167734
Short name T60
Test name
Test status
Simulation time 4131475375 ps
CPU time 23.8 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:31 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082167734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3082167734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.2151523667
Short name T327
Test name
Test status
Simulation time 2759565222 ps
CPU time 42.43 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:50 PM UTC 24
Peak memory 261824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151523667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2151523667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.2093224174
Short name T489
Test name
Test status
Simulation time 3011254174 ps
CPU time 9.83 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:17 PM UTC 24
Peak memory 251396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093224174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2093224174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.397840630
Short name T51
Test name
Test status
Simulation time 111074827 ps
CPU time 5.94 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:13 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397840630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.397840630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.2833355420
Short name T178
Test name
Test status
Simulation time 631109382 ps
CPU time 13.6 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:21 PM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833355420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2833355420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.1179593162
Short name T432
Test name
Test status
Simulation time 2211434529 ps
CPU time 14.89 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:22 PM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179593162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1179593162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.2730310157
Short name T397
Test name
Test status
Simulation time 657800542 ps
CPU time 16.75 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:24 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730310157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2730310157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.737914889
Short name T487
Test name
Test status
Simulation time 211061101 ps
CPU time 5.24 seconds
Started Aug 27 03:04:06 PM UTC 24
Finished Aug 27 03:04:12 PM UTC 24
Peak memory 250976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737914889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.737914889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.3070504404
Short name T308
Test name
Test status
Simulation time 1044357450 ps
CPU time 4.07 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:16 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070504404 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.3070504404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3636031081
Short name T21
Test name
Test status
Simulation time 18177714491 ps
CPU time 92.7 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:05:45 PM UTC 24
Peak memory 268176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3636031081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.otp_ctrl_stress_all_with_rand_reset.3636031081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.958485304
Short name T317
Test name
Test status
Simulation time 1541239497 ps
CPU time 24.97 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:37 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958485304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.958485304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.1387581672
Short name T842
Test name
Test status
Simulation time 430030313 ps
CPU time 4.84 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:35 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387581672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1387581672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.1858897732
Short name T301
Test name
Test status
Simulation time 285264754 ps
CPU time 16.37 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:47 PM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858897732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1858897732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.3565782179
Short name T841
Test name
Test status
Simulation time 100844114 ps
CPU time 4.62 seconds
Started Aug 27 03:09:29 PM UTC 24
Finished Aug 27 03:09:35 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565782179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3565782179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.2236513861
Short name T844
Test name
Test status
Simulation time 149982175 ps
CPU time 6.24 seconds
Started Aug 27 03:09:30 PM UTC 24
Finished Aug 27 03:09:37 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236513861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2236513861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.3192355216
Short name T845
Test name
Test status
Simulation time 2124360253 ps
CPU time 6.78 seconds
Started Aug 27 03:09:30 PM UTC 24
Finished Aug 27 03:09:38 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192355216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3192355216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.3942072815
Short name T876
Test name
Test status
Simulation time 15653348852 ps
CPU time 42.91 seconds
Started Aug 27 03:09:30 PM UTC 24
Finished Aug 27 03:10:14 PM UTC 24
Peak memory 253300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942072815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3942072815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1034532861
Short name T979
Test name
Test status
Simulation time 13162872981 ps
CPU time 99.64 seconds
Started Aug 27 03:09:30 PM UTC 24
Finished Aug 27 03:11:12 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1034532861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 72.otp_ctrl_stress_all_with_rand_reset.1034532861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.600475025
Short name T213
Test name
Test status
Simulation time 99280058 ps
CPU time 3.26 seconds
Started Aug 27 03:09:31 PM UTC 24
Finished Aug 27 03:09:36 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600475025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.600475025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.1809111919
Short name T840
Test name
Test status
Simulation time 76867450 ps
CPU time 2.84 seconds
Started Aug 27 03:09:31 PM UTC 24
Finished Aug 27 03:09:35 PM UTC 24
Peak memory 251124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809111919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1809111919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1063937540
Short name T848
Test name
Test status
Simulation time 595893195 ps
CPU time 6.86 seconds
Started Aug 27 03:09:33 PM UTC 24
Finished Aug 27 03:09:41 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063937540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1063937540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.2408186726
Short name T849
Test name
Test status
Simulation time 335431665 ps
CPU time 4.62 seconds
Started Aug 27 03:09:36 PM UTC 24
Finished Aug 27 03:09:41 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408186726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2408186726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3403585425
Short name T160
Test name
Test status
Simulation time 154702737 ps
CPU time 4.48 seconds
Started Aug 27 03:09:36 PM UTC 24
Finished Aug 27 03:09:41 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403585425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3403585425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.729719212
Short name T377
Test name
Test status
Simulation time 2182330357 ps
CPU time 63.45 seconds
Started Aug 27 03:09:36 PM UTC 24
Finished Aug 27 03:10:41 PM UTC 24
Peak memory 259744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=729719212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
75.otp_ctrl_stress_all_with_rand_reset.729719212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.3127191679
Short name T852
Test name
Test status
Simulation time 619218590 ps
CPU time 7.43 seconds
Started Aug 27 03:09:36 PM UTC 24
Finished Aug 27 03:09:44 PM UTC 24
Peak memory 251400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127191679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3127191679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.3335368283
Short name T851
Test name
Test status
Simulation time 267929478 ps
CPU time 5.67 seconds
Started Aug 27 03:09:37 PM UTC 24
Finished Aug 27 03:09:44 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335368283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3335368283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.526113401
Short name T850
Test name
Test status
Simulation time 231825291 ps
CPU time 4.69 seconds
Started Aug 27 03:09:37 PM UTC 24
Finished Aug 27 03:09:43 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526113401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.526113401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.2333647562
Short name T855
Test name
Test status
Simulation time 2042120858 ps
CPU time 8.41 seconds
Started Aug 27 03:09:37 PM UTC 24
Finished Aug 27 03:09:47 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333647562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2333647562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.1542120861
Short name T856
Test name
Test status
Simulation time 1419186571 ps
CPU time 7.11 seconds
Started Aug 27 03:09:39 PM UTC 24
Finished Aug 27 03:09:47 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542120861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1542120861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.997388086
Short name T925
Test name
Test status
Simulation time 2897585798 ps
CPU time 66.21 seconds
Started Aug 27 03:09:40 PM UTC 24
Finished Aug 27 03:10:48 PM UTC 24
Peak memory 274240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=997388086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
78.otp_ctrl_stress_all_with_rand_reset.997388086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.1301032022
Short name T862
Test name
Test status
Simulation time 263246644 ps
CPU time 5.42 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:09:57 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301032022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1301032022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.1286084732
Short name T142
Test name
Test status
Simulation time 554612816 ps
CPU time 12.5 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:10:04 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286084732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1286084732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.376853357
Short name T491
Test name
Test status
Simulation time 219492156 ps
CPU time 1.9 seconds
Started Aug 27 03:04:17 PM UTC 24
Finished Aug 27 03:04:20 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376853357 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.376853357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.2823249604
Short name T433
Test name
Test status
Simulation time 9458245689 ps
CPU time 14.01 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:26 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823249604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.2823249604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.921616664
Short name T38
Test name
Test status
Simulation time 7941667066 ps
CPU time 23.1 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:38 PM UTC 24
Peak memory 251700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921616664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.921616664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.3450972744
Short name T408
Test name
Test status
Simulation time 6387743339 ps
CPU time 40.58 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:56 PM UTC 24
Peak memory 263684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450972744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3450972744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.4088991133
Short name T431
Test name
Test status
Simulation time 647463422 ps
CPU time 12.85 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:28 PM UTC 24
Peak memory 251612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088991133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.4088991133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.2731384572
Short name T62
Test name
Test status
Simulation time 542389211 ps
CPU time 5.43 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:17 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731384572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2731384572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.1548129088
Short name T177
Test name
Test status
Simulation time 353680937 ps
CPU time 5.25 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:20 PM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548129088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1548129088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.3894777463
Short name T281
Test name
Test status
Simulation time 2779345606 ps
CPU time 24.12 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:40 PM UTC 24
Peak memory 253140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894777463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3894777463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2802222091
Short name T285
Test name
Test status
Simulation time 3187185566 ps
CPU time 14.3 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:29 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802222091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2802222091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.4049601415
Short name T296
Test name
Test status
Simulation time 670013290 ps
CPU time 10.46 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:22 PM UTC 24
Peak memory 253268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049601415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.4049601415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.1760440596
Short name T490
Test name
Test status
Simulation time 156945183 ps
CPU time 6.8 seconds
Started Aug 27 03:04:10 PM UTC 24
Finished Aug 27 03:04:18 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760440596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1760440596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.2137270414
Short name T93
Test name
Test status
Simulation time 21169398084 ps
CPU time 199.27 seconds
Started Aug 27 03:04:17 PM UTC 24
Finished Aug 27 03:07:39 PM UTC 24
Peak memory 270248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2137270414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.otp_ctrl_stress_all_with_rand_reset.2137270414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.4044124934
Short name T320
Test name
Test status
Simulation time 1165342291 ps
CPU time 13.63 seconds
Started Aug 27 03:04:14 PM UTC 24
Finished Aug 27 03:04:29 PM UTC 24
Peak memory 250932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044124934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.4044124934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.1218129087
Short name T861
Test name
Test status
Simulation time 155556049 ps
CPU time 5.2 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:09:56 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218129087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1218129087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3909323613
Short name T867
Test name
Test status
Simulation time 259256135 ps
CPU time 15.93 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:10:07 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909323613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3909323613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.353940625
Short name T917
Test name
Test status
Simulation time 1788666325 ps
CPU time 51.9 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:10:44 PM UTC 24
Peak memory 267824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=353940625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
80.otp_ctrl_stress_all_with_rand_reset.353940625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.2940835845
Short name T858
Test name
Test status
Simulation time 227663906 ps
CPU time 4.47 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:09:56 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940835845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2940835845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.3050112058
Short name T863
Test name
Test status
Simulation time 773690093 ps
CPU time 11.24 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:10:03 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050112058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3050112058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3185178944
Short name T931
Test name
Test status
Simulation time 3632459283 ps
CPU time 56.79 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:10:49 PM UTC 24
Peak memory 257592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3185178944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 81.otp_ctrl_stress_all_with_rand_reset.3185178944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.1315112801
Short name T857
Test name
Test status
Simulation time 478212058 ps
CPU time 3.97 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:09:56 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315112801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1315112801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.3007801607
Short name T302
Test name
Test status
Simulation time 176184631 ps
CPU time 9.97 seconds
Started Aug 27 03:09:50 PM UTC 24
Finished Aug 27 03:10:02 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007801607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3007801607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.1370805129
Short name T859
Test name
Test status
Simulation time 154850843 ps
CPU time 4.36 seconds
Started Aug 27 03:09:51 PM UTC 24
Finished Aug 27 03:09:56 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370805129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1370805129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.3147744228
Short name T860
Test name
Test status
Simulation time 233682316 ps
CPU time 4.57 seconds
Started Aug 27 03:09:51 PM UTC 24
Finished Aug 27 03:09:56 PM UTC 24
Peak memory 251040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147744228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3147744228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1671205180
Short name T376
Test name
Test status
Simulation time 3432856721 ps
CPU time 34.82 seconds
Started Aug 27 03:09:51 PM UTC 24
Finished Aug 27 03:10:27 PM UTC 24
Peak memory 257592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1671205180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 83.otp_ctrl_stress_all_with_rand_reset.1671205180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2301684149
Short name T34
Test name
Test status
Simulation time 148092749 ps
CPU time 5.9 seconds
Started Aug 27 03:09:51 PM UTC 24
Finished Aug 27 03:09:58 PM UTC 24
Peak memory 253276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301684149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2301684149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2692762448
Short name T866
Test name
Test status
Simulation time 407796248 ps
CPU time 11.82 seconds
Started Aug 27 03:09:53 PM UTC 24
Finished Aug 27 03:10:06 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692762448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2692762448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.1879402485
Short name T75
Test name
Test status
Simulation time 2937959683 ps
CPU time 9.32 seconds
Started Aug 27 03:09:57 PM UTC 24
Finished Aug 27 03:10:07 PM UTC 24
Peak memory 251492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879402485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.1879402485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.2020965968
Short name T870
Test name
Test status
Simulation time 617899421 ps
CPU time 10.69 seconds
Started Aug 27 03:09:57 PM UTC 24
Finished Aug 27 03:10:09 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020965968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2020965968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1225353169
Short name T1180
Test name
Test status
Simulation time 17426672587 ps
CPU time 178.18 seconds
Started Aug 27 03:09:57 PM UTC 24
Finished Aug 27 03:12:58 PM UTC 24
Peak memory 268052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1225353169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 85.otp_ctrl_stress_all_with_rand_reset.1225353169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.1200619984
Short name T864
Test name
Test status
Simulation time 615323993 ps
CPU time 5.59 seconds
Started Aug 27 03:09:57 PM UTC 24
Finished Aug 27 03:10:04 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200619984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1200619984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.1023002609
Short name T869
Test name
Test status
Simulation time 257069868 ps
CPU time 9.32 seconds
Started Aug 27 03:09:58 PM UTC 24
Finished Aug 27 03:10:09 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023002609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1023002609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.4139492202
Short name T279
Test name
Test status
Simulation time 2432159046 ps
CPU time 97.24 seconds
Started Aug 27 03:09:58 PM UTC 24
Finished Aug 27 03:11:37 PM UTC 24
Peak memory 261808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4139492202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 86.otp_ctrl_stress_all_with_rand_reset.4139492202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.4007967908
Short name T865
Test name
Test status
Simulation time 208934109 ps
CPU time 4.83 seconds
Started Aug 27 03:09:59 PM UTC 24
Finished Aug 27 03:10:05 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007967908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.4007967908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.2374866621
Short name T878
Test name
Test status
Simulation time 234208515 ps
CPU time 12.1 seconds
Started Aug 27 03:10:01 PM UTC 24
Finished Aug 27 03:10:14 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374866621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2374866621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.2161147359
Short name T877
Test name
Test status
Simulation time 2588327981 ps
CPU time 9.35 seconds
Started Aug 27 03:10:04 PM UTC 24
Finished Aug 27 03:10:14 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161147359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2161147359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1939608632
Short name T875
Test name
Test status
Simulation time 2062281442 ps
CPU time 7.89 seconds
Started Aug 27 03:10:05 PM UTC 24
Finished Aug 27 03:10:14 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939608632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1939608632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.641457691
Short name T872
Test name
Test status
Simulation time 406557701 ps
CPU time 4.22 seconds
Started Aug 27 03:10:06 PM UTC 24
Finished Aug 27 03:10:12 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641457691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.641457691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.286210057
Short name T886
Test name
Test status
Simulation time 204108467 ps
CPU time 11.36 seconds
Started Aug 27 03:10:08 PM UTC 24
Finished Aug 27 03:10:20 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286210057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.286210057
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.17957105
Short name T318
Test name
Test status
Simulation time 107437882 ps
CPU time 2.8 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17957105 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.17957105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.2376152727
Short name T264
Test name
Test status
Simulation time 801203476 ps
CPU time 20.06 seconds
Started Aug 27 03:04:20 PM UTC 24
Finished Aug 27 03:04:42 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376152727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2376152727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.1267965137
Short name T234
Test name
Test status
Simulation time 1447311223 ps
CPU time 21.76 seconds
Started Aug 27 03:04:21 PM UTC 24
Finished Aug 27 03:04:43 PM UTC 24
Peak memory 251396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267965137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1267965137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.1934799114
Short name T106
Test name
Test status
Simulation time 364050438 ps
CPU time 9.64 seconds
Started Aug 27 03:04:20 PM UTC 24
Finished Aug 27 03:04:31 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934799114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1934799114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.3725362837
Short name T185
Test name
Test status
Simulation time 1469492050 ps
CPU time 4.3 seconds
Started Aug 27 03:04:20 PM UTC 24
Finished Aug 27 03:04:25 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725362837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.3725362837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.2120996649
Short name T462
Test name
Test status
Simulation time 1247109890 ps
CPU time 9.2 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:36 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120996649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2120996649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.4126426928
Short name T230
Test name
Test status
Simulation time 3116817487 ps
CPU time 22.72 seconds
Started Aug 27 03:04:20 PM UTC 24
Finished Aug 27 03:04:44 PM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126426928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.4126426928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.1017587437
Short name T435
Test name
Test status
Simulation time 1344123600 ps
CPU time 13.46 seconds
Started Aug 27 03:04:20 PM UTC 24
Finished Aug 27 03:04:35 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017587437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1017587437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3890122658
Short name T262
Test name
Test status
Simulation time 276385521 ps
CPU time 8.78 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:36 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890122658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3890122658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.60801449
Short name T492
Test name
Test status
Simulation time 1805113292 ps
CPU time 9.81 seconds
Started Aug 27 03:04:17 PM UTC 24
Finished Aug 27 03:04:28 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60801449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.60801449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3820651473
Short name T465
Test name
Test status
Simulation time 71870407329 ps
CPU time 204.81 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:07:54 PM UTC 24
Peak memory 271988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3820651473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.otp_ctrl_stress_all_with_rand_reset.3820651473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.2179598745
Short name T107
Test name
Test status
Simulation time 266854732 ps
CPU time 4.6 seconds
Started Aug 27 03:04:26 PM UTC 24
Finished Aug 27 03:04:31 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179598745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2179598745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.356203035
Short name T85
Test name
Test status
Simulation time 509990178 ps
CPU time 7.03 seconds
Started Aug 27 03:10:08 PM UTC 24
Finished Aug 27 03:10:16 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356203035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.356203035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.2631314018
Short name T874
Test name
Test status
Simulation time 310513179 ps
CPU time 2.36 seconds
Started Aug 27 03:10:10 PM UTC 24
Finished Aug 27 03:10:13 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631314018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2631314018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2765570084
Short name T378
Test name
Test status
Simulation time 21934182877 ps
CPU time 46.13 seconds
Started Aug 27 03:10:10 PM UTC 24
Finished Aug 27 03:10:58 PM UTC 24
Peak memory 267800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2765570084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 90.otp_ctrl_stress_all_with_rand_reset.2765570084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2027397148
Short name T881
Test name
Test status
Simulation time 154099977 ps
CPU time 5.76 seconds
Started Aug 27 03:10:10 PM UTC 24
Finished Aug 27 03:10:17 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027397148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2027397148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.1011094642
Short name T132
Test name
Test status
Simulation time 772312291 ps
CPU time 14.86 seconds
Started Aug 27 03:10:10 PM UTC 24
Finished Aug 27 03:10:26 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011094642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1011094642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.3830909355
Short name T1073
Test name
Test status
Simulation time 4624157918 ps
CPU time 86.56 seconds
Started Aug 27 03:10:10 PM UTC 24
Finished Aug 27 03:11:39 PM UTC 24
Peak memory 267824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3830909355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 91.otp_ctrl_stress_all_with_rand_reset.3830909355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.2774231428
Short name T880
Test name
Test status
Simulation time 92014679 ps
CPU time 4.04 seconds
Started Aug 27 03:10:10 PM UTC 24
Finished Aug 27 03:10:15 PM UTC 24
Peak memory 251272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774231428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2774231428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.519313331
Short name T883
Test name
Test status
Simulation time 3373405197 ps
CPU time 5.7 seconds
Started Aug 27 03:10:11 PM UTC 24
Finished Aug 27 03:10:18 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519313331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.519313331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.335623523
Short name T894
Test name
Test status
Simulation time 2300738796 ps
CPU time 9.27 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:10:26 PM UTC 24
Peak memory 250344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335623523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.335623523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.858608283
Short name T897
Test name
Test status
Simulation time 1578991829 ps
CPU time 12.4 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:10:30 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858608283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.858608283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.2544354688
Short name T991
Test name
Test status
Simulation time 4363274537 ps
CPU time 56.68 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:11:14 PM UTC 24
Peak memory 267860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2544354688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 93.otp_ctrl_stress_all_with_rand_reset.2544354688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.527194629
Short name T887
Test name
Test status
Simulation time 156654537 ps
CPU time 3.31 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:10:21 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527194629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.527194629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.754274023
Short name T891
Test name
Test status
Simulation time 273251994 ps
CPU time 8.06 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:10:25 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754274023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.754274023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.3028500151
Short name T388
Test name
Test status
Simulation time 25023115749 ps
CPU time 121.78 seconds
Started Aug 27 03:10:16 PM UTC 24
Finished Aug 27 03:12:20 PM UTC 24
Peak memory 268120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3028500151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 94.otp_ctrl_stress_all_with_rand_reset.3028500151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.488109719
Short name T167
Test name
Test status
Simulation time 1475308223 ps
CPU time 6.54 seconds
Started Aug 27 03:10:19 PM UTC 24
Finished Aug 27 03:10:27 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488109719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.488109719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.35933765
Short name T892
Test name
Test status
Simulation time 309496910 ps
CPU time 5.12 seconds
Started Aug 27 03:10:19 PM UTC 24
Finished Aug 27 03:10:26 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35933765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.35933765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.1557495132
Short name T890
Test name
Test status
Simulation time 169586471 ps
CPU time 2.99 seconds
Started Aug 27 03:10:19 PM UTC 24
Finished Aug 27 03:10:23 PM UTC 24
Peak memory 253208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557495132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1557495132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.1424213087
Short name T884
Test name
Test status
Simulation time 237004485 ps
CPU time 5.01 seconds
Started Aug 27 03:10:23 PM UTC 24
Finished Aug 27 03:10:30 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424213087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1424213087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.2988340634
Short name T139
Test name
Test status
Simulation time 1089569849 ps
CPU time 16.45 seconds
Started Aug 27 03:10:23 PM UTC 24
Finished Aug 27 03:10:41 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988340634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2988340634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.191649817
Short name T1181
Test name
Test status
Simulation time 10103825089 ps
CPU time 233.71 seconds
Started Aug 27 03:10:23 PM UTC 24
Finished Aug 27 03:14:21 PM UTC 24
Peak memory 278028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=191649817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
97.otp_ctrl_stress_all_with_rand_reset.191649817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.1666765907
Short name T896
Test name
Test status
Simulation time 1497515032 ps
CPU time 4.5 seconds
Started Aug 27 03:10:24 PM UTC 24
Finished Aug 27 03:10:29 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666765907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1666765907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.581055772
Short name T895
Test name
Test status
Simulation time 276088930 ps
CPU time 4.25 seconds
Started Aug 27 03:10:24 PM UTC 24
Finished Aug 27 03:10:29 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581055772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.581055772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1570340523
Short name T380
Test name
Test status
Simulation time 2299551163 ps
CPU time 62.38 seconds
Started Aug 27 03:10:24 PM UTC 24
Finished Aug 27 03:11:28 PM UTC 24
Peak memory 257648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1570340523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 98.otp_ctrl_stress_all_with_rand_reset.1570340523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.754280162
Short name T893
Test name
Test status
Simulation time 104418036 ps
CPU time 4.88 seconds
Started Aug 27 03:10:28 PM UTC 24
Finished Aug 27 03:10:34 PM UTC 24
Peak memory 253276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754280162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.754280162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.210543335
Short name T898
Test name
Test status
Simulation time 1487850220 ps
CPU time 4.97 seconds
Started Aug 27 03:10:28 PM UTC 24
Finished Aug 27 03:10:35 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210543335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.210543335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.689428140
Short name T1178
Test name
Test status
Simulation time 8104561362 ps
CPU time 103.54 seconds
Started Aug 27 03:10:29 PM UTC 24
Finished Aug 27 03:12:14 PM UTC 24
Peak memory 267836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=689428140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
99.otp_ctrl_stress_all_with_rand_reset.689428140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest
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