Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_prog_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_lc_esc	2	0	2	100.00	100	1	1	0
lc_prog_req_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22710

1

T2

4

T4

2

T5

31

auto[1]

686

1

T5

1

T105

4

T106

5

---

Summary for Variable lc_prog_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22459

1

T2

4

T4

2

T5

32

auto[1]

937

1

T105

1

T106

3

T107

2

---

Summary for Variable lc_prog_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lc_prog_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

23370

1

T2

4

T4

2

T5

32

lc_esc_on

26

1

T194

1

T133

1

T336

1

---

Summary for Variable lc_prog_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21808

1

T2

4

T4

2

T5

32

auto[1]

1588

1

T104

1

T105

6

T93

1

---

Summary for Variable lc_prog_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12646

1

T2

2

T4

1

T5

21

auto[1]

10750

1

T2

2

T4

1

T5

11

---

Summary for Variable lc_prog_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21654

1

T2

4

T4

2

T5

31

auto[1]

1742

1

T5

1

T105

5

T106

15

---

Summary for Variable lc_prog_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21669

1

T2

4

T4

2

T5

32

auto[1]

1727

1

T105

7

T106

7

T107

3