Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48541	1			T12	136		T13	58		T90	2
access_err	55721	1			T4	54		T5	4		T11	16
write_blank_err	396	1			T7	2		T137	1		T9	5
ecc_uncorr_err	53535	1			T7	542		T103	2		T111	32
ecc_corr_err	1302	1			T13	4		T7	3		T111	2
no_err	72779	1			T2	30		T4	64		T5	15

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	639	1			T7	3		T9	4		T16	5
secret2	19827	1			T2	5		T4	7		T5	4
secret1	26360	1			T2	11		T4	15		T5	1
secret0	29323	1			T2	2		T4	8		T5	2
hw_cfg1	32031	1			T2	2		T4	7		T5	3
hw_cfg0	22741	1			T2	3		T4	11		T11	5
rot_creator_auth_state	16897	1			T4	9		T11	8		T12	5
rot_creator_auth_codesign	18679	1			T2	2		T4	9		T5	3
owner_sw_cfg	16712	1			T4	18		T11	9		T12	3
creator_sw_cfg	18339	1			T2	5		T4	18		T11	11
vendor_test	30726	1			T4	16		T5	6		T11	13

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3761	1			T21	10		T148	45		T333	620
fsm_err	secret1	5720	1			T110	610		T96	127		T146	597
fsm_err	secret0	3166	1			T94	43		T156	22		T248	212
fsm_err	hw_cfg1	3317	1			T152	15		T241	26		T149	242
fsm_err	hw_cfg0	5169	1			T109	273		T151	110		T247	84
fsm_err	rot_creator_auth_state	1988	1			T183	41		T334	188		T335	321
fsm_err	rot_creator_auth_codesign	3689	1			T12	136		T161	77		T181	27
fsm_err	owner_sw_cfg	2072	1			T172	11		T157	22		T336	1
fsm_err	creator_sw_cfg	3937	1			T185	294		T171	62		T213	63
fsm_err	vendor_test	15722	1			T13	58		T90	2		T61	92
access_err	life_cycle	639	1			T7	3		T9	4		T16	5
access_err	secret2	9283	1			T4	2		T5	3		T11	2
access_err	secret1	6335	1			T4	11		T5	1		T11	3
access_err	secret0	5154	1			T4	5		T11	1		T12	2
access_err	hw_cfg1	1150	1			T4	1		T11	3		T13	3
access_err	hw_cfg0	2434	1			T13	2		T18	2		T105	16
access_err	rot_creator_auth_state	4855	1			T4	4		T11	2		T13	1
access_err	rot_creator_auth_codesign	6859	1			T4	7		T11	2		T12	3
access_err	owner_sw_cfg	6150	1			T4	6		T11	3		T12	1
access_err	creator_sw_cfg	6610	1			T4	10		T13	2		T7	1
access_err	vendor_test	6252	1			T4	8		T18	15		T105	23
write_blank_err	secret2	7	1			T137	1		T135	1		T94	1
write_blank_err	secret1	22	1			T135	1		T337	1		T338	1
write_blank_err	secret0	37	1			T7	1		T9	1		T198	1
write_blank_err	hw_cfg1	61	1			T7	1		T16	1		T163	1
write_blank_err	hw_cfg0	17	1			T113	1		T208	1		T94	2
write_blank_err	rot_creator_auth_state	129	1			T9	1		T198	2		T135	2
write_blank_err	rot_creator_auth_codesign	41	1			T9	3		T113	4		T135	3
write_blank_err	owner_sw_cfg	33	1			T135	2		T339	1		T340	1
write_blank_err	creator_sw_cfg	18	1			T337	2		T341	6		T342	3
write_blank_err	vendor_test	31	1			T343	1		T314	2		T341	1
ecc_uncorr_err	secret2	2390	1			T137	486		T135	315		T94	514
ecc_uncorr_err	secret1	7860	1			T135	717		T337	301		T338	255
ecc_uncorr_err	secret0	14546	1			T7	542		T111	14		T9	625
ecc_uncorr_err	hw_cfg1	18465	1			T162	71		T16	386		T163	211
ecc_uncorr_err	hw_cfg0	4887	1			T103	2		T111	18		T161	67
ecc_uncorr_err	rot_creator_auth_state	2723	1			T161	70		T171	50		T156	19
ecc_uncorr_err	rot_creator_auth_codesign	968	1			T162	40		T207	26		T209	57
ecc_uncorr_err	owner_sw_cfg	696	1			T171	57		T207	22		T156	25
ecc_uncorr_err	creator_sw_cfg	1000	1			T162	40		T169	35		T171	64
ecc_corr_err	secret2	49	1			T111	1		T61	1		T32	1
ecc_corr_err	secret1	135	1			T61	1		T162	5		T32	4
ecc_corr_err	secret0	144	1			T13	2		T32	3		T170	1
ecc_corr_err	hw_cfg1	259	1			T7	3		T61	2		T32	8
ecc_corr_err	hw_cfg0	221	1			T13	1		T61	3		T32	12
ecc_corr_err	rot_creator_auth_state	113	1			T32	1		T120	1		T156	1
ecc_corr_err	rot_creator_auth_codesign	122	1			T32	9		T170	2		T120	1
ecc_corr_err	owner_sw_cfg	125	1			T13	1		T171	1		T120	1
ecc_corr_err	creator_sw_cfg	134	1			T111	1		T162	1		T169	1
no_err	secret2	4337	1			T2	5		T4	5		T5	1
no_err	secret1	6288	1			T2	11		T4	4		T11	1
no_err	secret0	6276	1			T2	2		T4	3		T5	2
no_err	hw_cfg1	8779	1			T2	2		T4	6		T5	3
no_err	hw_cfg0	10013	1			T2	3		T4	11		T11	5
no_err	rot_creator_auth_state	7089	1			T4	5		T11	6		T12	5
no_err	rot_creator_auth_codesign	7000	1			T2	2		T4	2		T5	3
no_err	owner_sw_cfg	7636	1			T4	12		T11	6		T12	2
no_err	creator_sw_cfg	6640	1			T2	5		T4	8		T11	11
no_err	vendor_test	8721	1			T4	8		T5	6		T11	13

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded