Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	44102	1			T4	44		T102	350		T126	12
access_err	46569	1			T6	7		T12	9		T36	29
write_blank_err	316	1			T12	1		T7	1		T8	1
ecc_uncorr_err	52952	1			T12	384		T126	23		T7	140
ecc_corr_err	1375	1			T126	6		T93	17		T100	27
no_err	67106	1			T3	24		T4	14		T5	92

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	519	1			T7	4		T8	3		T9	25
secret2	20452	1			T4	5		T5	14		T6	3
secret1	20455	1			T3	2		T5	6		T6	2
secret0	28388	1			T5	7		T6	12		T12	390
hw_cfg1	25928	1			T3	6		T4	3		T5	5
hw_cfg0	18975	1			T3	3		T5	13		T12	8
rot_creator_auth_state	18707	1			T4	44		T5	10		T6	2
rot_creator_auth_codesign	15852	1			T3	5		T4	1		T5	19
owner_sw_cfg	16277	1			T4	4		T5	6		T6	6
creator_sw_cfg	17734	1			T3	6		T5	4		T6	9
vendor_test	29133	1			T3	2		T4	1		T5	8

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4158	1			T116	34		T296	154		T111	12
fsm_err	secret1	2960	1			T126	12		T346	583		T155	15
fsm_err	secret0	2710	1			T166	257		T197	1		T167	63
fsm_err	hw_cfg1	3407	1			T147	61		T155	57		T342	2
fsm_err	hw_cfg0	2865	1			T102	350		T215	214		T347	29
fsm_err	rot_creator_auth_state	2796	1			T4	44		T172	59		T224	61
fsm_err	rot_creator_auth_codesign	2036	1			T264	50		T167	38		T188	49
fsm_err	owner_sw_cfg	3032	1			T185	29		T237	28		T186	59
fsm_err	creator_sw_cfg	3964	1			T348	60		T349	499		T265	344
fsm_err	vendor_test	16174	1			T100	216		T104	89		T147	48
access_err	life_cycle	519	1			T7	4		T8	3		T9	25
access_err	secret2	7876	1			T6	3		T12	2		T36	2
access_err	secret1	5107	1			T36	3		T93	3		T99	11
access_err	secret0	4314	1			T36	3		T92	5		T99	9
access_err	hw_cfg1	1060	1			T94	1		T93	3		T99	2
access_err	hw_cfg0	1905	1			T36	3		T92	8		T93	1
access_err	rot_creator_auth_state	4011	1			T12	2		T36	2		T94	1
access_err	rot_creator_auth_codesign	5692	1			T12	1		T36	2		T92	8
access_err	owner_sw_cfg	4968	1			T12	2		T36	7		T92	3
access_err	creator_sw_cfg	5810	1			T6	4		T36	5		T92	3
access_err	vendor_test	5307	1			T12	2		T36	2		T92	1
write_blank_err	secret2	11	1			T171	1		T111	1		T293	1
write_blank_err	secret1	17	1			T223	1		T350	1		T351	1
write_blank_err	secret0	40	1			T12	1		T7	1		T352	1
write_blank_err	hw_cfg1	48	1			T8	1		T9	4		T166	3
write_blank_err	hw_cfg0	12	1			T143	1		T353	1		T354	1
write_blank_err	rot_creator_auth_state	112	1			T9	15		T241	1		T166	1
write_blank_err	rot_creator_auth_codesign	36	1			T353	1		T90	1		T355	2
write_blank_err	owner_sw_cfg	15	1			T356	3		T357	3		T358	2
write_blank_err	creator_sw_cfg	8	1			T9	1		T245	3		T157	1
write_blank_err	vendor_test	17	1			T352	1		T244	2		T357	5
ecc_uncorr_err	secret2	4027	1			T147	60		T171	261		T224	59
ecc_uncorr_err	secret1	5897	1			T147	113		T223	348		T224	59
ecc_uncorr_err	secret0	15452	1			T12	384		T7	140		T172	108
ecc_uncorr_err	hw_cfg1	13390	1			T126	3		T8	523		T9	65
ecc_uncorr_err	hw_cfg0	4923	1			T126	10		T147	106		T224	60
ecc_uncorr_err	rot_creator_auth_state	5202	1			T126	10		T147	62		T172	64
ecc_uncorr_err	rot_creator_auth_codesign	1238	1			T172	56		T224	176		T359	8
ecc_uncorr_err	owner_sw_cfg	1114	1			T147	55		T169	43		T237	24
ecc_uncorr_err	creator_sw_cfg	1709	1			T147	58		T224	61		T237	27
ecc_corr_err	secret2	91	1			T100	5		T104	1		T147	5
ecc_corr_err	secret1	140	1			T93	3		T147	2		T128	2
ecc_corr_err	secret0	128	1			T169	1		T172	1		T106	1
ecc_corr_err	hw_cfg1	258	1			T93	3		T100	5		T104	2
ecc_corr_err	hw_cfg0	234	1			T93	2		T100	1		T104	4
ecc_corr_err	rot_creator_auth_state	149	1			T93	3		T100	6		T128	2
ecc_corr_err	rot_creator_auth_codesign	135	1			T93	1		T100	7		T104	4
ecc_corr_err	owner_sw_cfg	110	1			T126	6		T93	3		T100	1
ecc_corr_err	creator_sw_cfg	130	1			T93	2		T100	2		T104	1
no_err	secret2	4289	1			T4	5		T5	14		T13	2
no_err	secret1	6334	1			T3	2		T5	6		T6	2
no_err	secret0	5744	1			T5	7		T6	12		T12	5
no_err	hw_cfg1	7765	1			T3	6		T4	3		T5	5
no_err	hw_cfg0	9036	1			T3	3		T5	13		T12	8
no_err	rot_creator_auth_state	6437	1			T5	10		T6	2		T12	2
no_err	rot_creator_auth_codesign	6715	1			T3	5		T4	1		T5	19
no_err	owner_sw_cfg	7038	1			T4	4		T5	6		T6	6
no_err	creator_sw_cfg	6113	1			T3	6		T5	4		T6	5
no_err	vendor_test	7635	1			T3	2		T4	1		T5	8

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded