Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47123	1			T4	9		T34	87		T95	95
access_err	49033	1			T34	1		T91	67		T135	2
write_blank_err	404	1			T134	1		T7	1		T8	2
ecc_uncorr_err	56253	1			T134	336		T128	174		T154	263
ecc_corr_err	1247	1			T95	17		T128	6		T129	7
no_err	70864	1			T3	54		T5	45		T10	2

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	647	1			T7	4		T8	10		T16	2
secret2	23978	1			T3	10		T4	9		T5	5
secret1	23890	1			T3	9		T5	1		T6	2
secret0	29594	1			T3	2		T5	1		T6	1
hw_cfg1	30056	1			T3	4		T5	5		T24	3
hw_cfg0	21609	1			T3	5		T5	5		T91	17
rot_creator_auth_state	19352	1			T3	11		T5	6		T6	2
rot_creator_auth_codesign	16326	1			T3	5		T5	9		T24	2
owner_sw_cfg	17148	1			T3	3		T5	2		T6	1
creator_sw_cfg	16501	1			T3	4		T5	8		T10	1
vendor_test	25823	1			T3	1		T5	3		T10	1

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4744	1			T4	9		T169	84		T175	570
fsm_err	secret1	5494	1			T15	141		T145	339		T314	69
fsm_err	secret0	3494	1			T204	662		T279	239		T282	318
fsm_err	hw_cfg1	3685	1			T34	87		T178	41		T394	246
fsm_err	hw_cfg0	5929	1			T177	49		T166	339		T167	46
fsm_err	rot_creator_auth_state	3088	1			T129	26		T307	445		T178	41
fsm_err	rot_creator_auth_codesign	1949	1			T199	63		T178	41		T200	55
fsm_err	owner_sw_cfg	3693	1			T184	3		T193	5		T395	117
fsm_err	creator_sw_cfg	3008	1			T184	7		T396	340		T145	211
fsm_err	vendor_test	12039	1			T95	95		T78	83		T104	34
access_err	life_cycle	647	1			T7	4		T8	10		T16	2
access_err	secret2	8204	1			T91	11		T95	3		T17	14
access_err	secret1	5664	1			T91	11		T17	9		T92	4
access_err	secret0	4529	1			T91	3		T135	2		T17	2
access_err	hw_cfg1	1241	1			T34	1		T91	2		T17	2
access_err	hw_cfg0	2290	1			T91	10		T17	3		T18	7
access_err	rot_creator_auth_state	4161	1			T91	6		T17	6		T129	2
access_err	rot_creator_auth_codesign	6030	1			T91	3		T17	7		T92	1
access_err	owner_sw_cfg	4877	1			T91	2		T92	3		T18	3
access_err	creator_sw_cfg	5966	1			T91	11		T17	8		T18	8
access_err	vendor_test	5424	1			T91	8		T17	2		T129	4
write_blank_err	secret2	17	1			T236	1		T242	1		T384	1
write_blank_err	secret1	20	1			T7	1		T16	1		T390	1
write_blank_err	secret0	43	1			T134	1		T8	1		T183	1
write_blank_err	hw_cfg1	58	1			T390	1		T397	1		T398	1
write_blank_err	hw_cfg0	15	1			T399	1		T398	2		T400	1
write_blank_err	rot_creator_auth_state	117	1			T8	1		T390	7		T398	2
write_blank_err	rot_creator_auth_codesign	56	1			T93	4		T167	2		T145	2
write_blank_err	owner_sw_cfg	31	1			T271	7		T401	4		T378	6
write_blank_err	creator_sw_cfg	19	1			T167	5		T402	2		T261	1
write_blank_err	vendor_test	28	1			T16	1		T390	1		T399	2
ecc_uncorr_err	secret2	6215	1			T181	45		T236	648		T242	490
ecc_uncorr_err	secret1	6488	1			T154	36		T7	306		T182	39
ecc_uncorr_err	secret0	15220	1			T134	336		T154	36		T8	116
ecc_uncorr_err	hw_cfg1	16833	1			T128	118		T154	34		T193	11
ecc_uncorr_err	hw_cfg0	3634	1			T182	67		T399	218		T403	14
ecc_uncorr_err	rot_creator_auth_state	4799	1			T182	29		T177	50		T259	482
ecc_uncorr_err	rot_creator_auth_codesign	1151	1			T128	56		T181	51		T184	7
ecc_uncorr_err	owner_sw_cfg	905	1			T154	117		T181	43		T184	2
ecc_uncorr_err	creator_sw_cfg	1008	1			T154	40		T184	2		T321	24
ecc_corr_err	secret2	82	1			T129	2		T148	1		T60	1
ecc_corr_err	secret1	137	1			T95	3		T104	5		T182	4
ecc_corr_err	secret0	131	1			T95	4		T128	3		T129	1
ecc_corr_err	hw_cfg1	225	1			T128	1		T129	2		T154	2
ecc_corr_err	hw_cfg0	204	1			T95	1		T128	1		T129	2
ecc_corr_err	rot_creator_auth_state	126	1			T154	1		T8	1		T181	1
ecc_corr_err	rot_creator_auth_codesign	115	1			T104	4		T182	1		T61	5
ecc_corr_err	owner_sw_cfg	124	1			T95	7		T104	2		T184	2
ecc_corr_err	creator_sw_cfg	103	1			T95	2		T128	1		T104	1
no_err	secret2	4716	1			T3	10		T5	5		T6	3
no_err	secret1	6087	1			T3	9		T5	1		T6	2
no_err	secret0	6177	1			T3	2		T5	1		T6	1
no_err	hw_cfg1	8014	1			T3	4		T5	5		T24	3
no_err	hw_cfg0	9537	1			T3	5		T5	5		T91	7
no_err	rot_creator_auth_state	7061	1			T3	11		T5	6		T6	2
no_err	rot_creator_auth_codesign	7025	1			T3	5		T5	9		T24	2
no_err	owner_sw_cfg	7518	1			T3	3		T5	2		T6	1
no_err	creator_sw_cfg	6397	1			T3	4		T5	8		T10	1
no_err	vendor_test	8332	1			T3	1		T5	3		T10	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded