Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
secret1_lock	2	0	2	100.00	100	1	1	2
sram_index	4	0	4	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sram_req_lock_cross	8	0	8	100.00	100	1	1	0

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T135

4

T128

5

T285

3

auto[1]

1316

1

T127

11

T106

5

T243

15

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Summary for Variable sram_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for sram_index

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	69	1			T436	1		T143	5		T489	2
sram_key[0x1]	719	1			T128	2		T285	1		T7	1
sram_key[0x2]	782	1			T135	2		T128	1		T285	1
sram_key[0x3]	774	1			T135	2		T128	2		T285	1

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Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for sram_req_lock_cross

Bins

sram_index	secret1_lock	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	auto[0]	22	1			T143	2		T489	1		T490	2
sram_key[0x0]	auto[1]	47	1			T436	1		T143	3		T489	1
sram_key[0x1]	auto[0]	322	1			T128	2		T285	1		T7	1
sram_key[0x1]	auto[1]	397	1			T127	1		T243	2		T442	3
sram_key[0x2]	auto[0]	350	1			T135	2		T128	1		T285	1
sram_key[0x2]	auto[1]	432	1			T127	5		T106	1		T243	7
sram_key[0x3]	auto[0]	334	1			T135	2		T128	2		T285	1
sram_key[0x3]	auto[1]	440	1			T127	5		T106	4		T243	6