Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47463	1			T14	15		T34	47		T36	38
access_err	47819	1			T6	1		T95	41		T135	3
write_blank_err	325	1			T7	1		T8	2		T9	4
ecc_uncorr_err	52506	1			T7	180		T8	529		T9	256
ecc_corr_err	1416	1			T36	24		T89	24		T117	1
no_err	69219	1			T2	6		T6	4		T4	6

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	580	1			T7	3		T8	2		T9	3
secret2	21084	1			T2	4		T6	1		T13	2
secret1	23729	1			T6	1		T14	15		T5	2
secret0	28261	1			T13	2		T5	2		T95	11
hw_cfg1	30538	1			T13	5		T5	4		T95	12
hw_cfg0	19390	1			T13	1		T5	3		T95	14
rot_creator_auth_state	16967	1			T2	2		T5	3		T95	14
rot_creator_auth_codesign	18597	1			T4	2		T13	5		T95	18
owner_sw_cfg	17336	1			T6	2		T13	4		T5	2
creator_sw_cfg	16372	1			T4	3		T5	2		T95	15
vendor_test	25894	1			T6	1		T4	1		T14	1

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	6042	1			T274	468		T25	409		T280	494
fsm_err	secret1	3707	1			T14	15		T278	59		T167	137
fsm_err	secret0	3197	1			T115	134		T231	342		T179	296
fsm_err	hw_cfg1	4970	1			T169	261		T25	19		T321	49
fsm_err	hw_cfg0	3255	1			T175	159		T398	55		T164	132
fsm_err	rot_creator_auth_state	3011	1			T180	57		T181	58		T185	24
fsm_err	rot_creator_auth_codesign	4048	1			T180	73		T182	28		T190	25
fsm_err	owner_sw_cfg	3424	1			T399	37		T237	70		T400	96
fsm_err	creator_sw_cfg	3395	1			T182	30		T190	25		T191	23
fsm_err	vendor_test	12414	1			T34	47		T36	38		T89	31
access_err	life_cycle	580	1			T7	3		T8	2		T9	3
access_err	secret2	8073	1			T6	1		T95	6		T135	3
access_err	secret1	5442	1			T95	6		T92	4		T129	17
access_err	secret0	4267	1			T95	7		T92	2		T129	1
access_err	hw_cfg1	1067	1			T129	1		T20	2		T128	2
access_err	hw_cfg0	1910	1			T95	2		T92	2		T129	7
access_err	rot_creator_auth_state	3982	1			T95	3		T7	2		T129	2
access_err	rot_creator_auth_codesign	5920	1			T95	6		T129	3		T20	18
access_err	owner_sw_cfg	5373	1			T95	1		T129	6		T20	3
access_err	creator_sw_cfg	5639	1			T95	8		T129	7		T20	7
access_err	vendor_test	5566	1			T95	2		T129	11		T20	12
write_blank_err	secret2	5	1			T257	1		T401	1		T402	1
write_blank_err	secret1	21	1			T7	1		T9	1		T403	1
write_blank_err	secret0	42	1			T404	1		T323	1		T255	1
write_blank_err	hw_cfg1	49	1			T8	1		T186	1		T236	1
write_blank_err	hw_cfg0	12	1			T325	1		T258	1		T259	1
write_blank_err	rot_creator_auth_state	94	1			T232	5		T405	1		T403	1
write_blank_err	rot_creator_auth_codesign	40	1			T183	1		T232	1		T406	1
write_blank_err	owner_sw_cfg	22	1			T9	3		T232	1		T255	1
write_blank_err	creator_sw_cfg	17	1			T325	2		T257	1		T259	1
write_blank_err	vendor_test	23	1			T8	1		T232	1		T325	5
ecc_uncorr_err	secret2	2398	1			T184	64		T181	123		T397	42
ecc_uncorr_err	secret1	8330	1			T7	180		T9	256		T184	60
ecc_uncorr_err	secret0	14608	1			T180	121		T404	440		T237	64
ecc_uncorr_err	hw_cfg1	16200	1			T8	529		T186	463		T236	541
ecc_uncorr_err	hw_cfg0	4363	1			T184	59		T181	65		T397	90
ecc_uncorr_err	rot_creator_auth_state	2924	1			T117	32		T181	125		T185	42
ecc_uncorr_err	rot_creator_auth_codesign	1682	1			T183	581		T397	48		T182	31
ecc_uncorr_err	owner_sw_cfg	1078	1			T184	57		T181	59		T397	99
ecc_uncorr_err	creator_sw_cfg	923	1			T185	38		T397	44		T182	58
ecc_corr_err	secret2	85	1			T36	1		T89	3		T180	1
ecc_corr_err	secret1	139	1			T181	2		T397	2		T182	1
ecc_corr_err	secret0	143	1			T36	5		T99	1		T90	3
ecc_corr_err	hw_cfg1	275	1			T36	8		T89	7		T99	5
ecc_corr_err	hw_cfg0	234	1			T36	5		T89	2		T99	1
ecc_corr_err	rot_creator_auth_state	117	1			T89	2		T117	1		T180	2
ecc_corr_err	rot_creator_auth_codesign	138	1			T89	9		T99	5		T90	6
ecc_corr_err	owner_sw_cfg	151	1			T36	3		T99	1		T181	1
ecc_corr_err	creator_sw_cfg	134	1			T36	2		T89	1		T87	3
no_err	secret2	4481	1			T2	4		T13	2		T95	2
no_err	secret1	6090	1			T6	1		T5	2		T95	8
no_err	secret0	6004	1			T13	2		T5	2		T95	4
no_err	hw_cfg1	7977	1			T13	5		T5	4		T95	12
no_err	hw_cfg0	9616	1			T13	1		T5	3		T95	12
no_err	rot_creator_auth_state	6839	1			T2	2		T5	3		T95	11
no_err	rot_creator_auth_codesign	6769	1			T4	2		T13	5		T95	12
no_err	owner_sw_cfg	7288	1			T6	2		T13	4		T5	2
no_err	creator_sw_cfg	6264	1			T4	3		T5	2		T95	7
no_err	vendor_test	7891	1			T6	1		T4	1		T14	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded