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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.03 93.71 97.25 96.08 91.08 97.66 96.34 93.07


Total test records in report: 1297
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T1066 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.4269709188 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 310696667 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.117247917 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 273388242 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.3298259259 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 122385310 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1313975235 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 150870604 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.2775332657 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 211830570 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.2431472778 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 189269925 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.718318038 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:15 PM UTC 24 1056182465 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.4006882587 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:21 PM UTC 24 538755904 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.468906195 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:16 PM UTC 24 1048999312 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.3784125625 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:16 PM UTC 24 186190813 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2067573822 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:16 PM UTC 24 190488690 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2084066502 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:16 PM UTC 24 651132692 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2407834094 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:17 PM UTC 24 137856184 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.148598894 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:17 PM UTC 24 2762840551 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.1841191366 Sep 09 07:12:57 PM UTC 24 Sep 09 07:13:17 PM UTC 24 1370727032 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1723079840 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:17 PM UTC 24 2266021545 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.517988766 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:18 PM UTC 24 2178494605 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1095017829 Sep 09 07:13:09 PM UTC 24 Sep 09 07:13:18 PM UTC 24 332377704 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.2028359905 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:18 PM UTC 24 1777417744 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2697440002 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:18 PM UTC 24 182761723 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.352038309 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:20 PM UTC 24 3499749805 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2909874106 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:21 PM UTC 24 112522274 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1299764462 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:21 PM UTC 24 105049720 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.1383922508 Sep 09 07:13:02 PM UTC 24 Sep 09 07:13:21 PM UTC 24 8728699193 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.3746331113 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 628913112 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1730730975 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 276354956 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.3598343080 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 1788677670 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2116772469 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 103754443 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4104240641 Sep 09 07:13:16 PM UTC 24 Sep 09 07:13:22 PM UTC 24 180319800 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.250233885 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 309928374 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.4011801378 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 1991342590 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.1320361760 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 388207230 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.4079635746 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 405248621 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.1946205316 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 231991966 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.4246233837 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 239627298 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1767814247 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:22 PM UTC 24 2330426914 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.156562541 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:23 PM UTC 24 169677658 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2981496505 Sep 09 07:10:42 PM UTC 24 Sep 09 07:13:23 PM UTC 24 8602551421 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.2131761358 Sep 09 07:13:09 PM UTC 24 Sep 09 07:13:23 PM UTC 24 463103174 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1414422366 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:23 PM UTC 24 124827999 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3483371531 Sep 09 07:13:17 PM UTC 24 Sep 09 07:13:23 PM UTC 24 275395532 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3152508830 Sep 09 07:10:11 PM UTC 24 Sep 09 07:13:25 PM UTC 24 54370483268 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.888006903 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:25 PM UTC 24 5890392739 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1274009781 Sep 09 07:12:57 PM UTC 24 Sep 09 07:13:26 PM UTC 24 14142699833 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2834982677 Sep 09 07:13:10 PM UTC 24 Sep 09 07:13:28 PM UTC 24 2771106483 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3279580799 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:31 PM UTC 24 132665507 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.256618572 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:31 PM UTC 24 203096024 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.525135129 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 318731941 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.909989810 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 147653179 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2683058285 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 105243507 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1161341253 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:32 PM UTC 24 119207280 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3083096043 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 529918062 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.4175674414 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 541605311 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.71932482 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 388295549 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.451282360 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:32 PM UTC 24 165660853 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.2924548842 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 411343598 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3379164789 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:32 PM UTC 24 347157209 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3316969463 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:32 PM UTC 24 528042457 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2715215153 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:32 PM UTC 24 591546774 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.536240764 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 426611935 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1153938390 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 316942527 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.730583999 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 155624323 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3776860457 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 120726240 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.2778473151 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 257068993 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.2736337787 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 335707748 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.11451141 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 316779106 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.203839390 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 603502381 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.3740597605 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 327813046 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.4143941235 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 121491823 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.3520535973 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 2044950108 ps
T1130 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.4105973581 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 265720069 ps
T1131 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.3795451287 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 2095580707 ps
T1132 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3630744140 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 384396305 ps
T1133 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.845603887 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 389440253 ps
T1134 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.1697381775 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:33 PM UTC 24 352360483 ps
T1135 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.853303041 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:33 PM UTC 24 120450016 ps
T1136 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.2160603599 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 289748944 ps
T1137 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.1117132029 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 164499150 ps
T1138 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.349985352 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 236594011 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.4084849916 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 285911029 ps
T1139 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.664088182 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 161042694 ps
T1140 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.4271394329 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 154801169 ps
T1141 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.3986156486 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 149054009 ps
T1142 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.4177751500 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 157025436 ps
T1143 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1766080870 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:34 PM UTC 24 1521064187 ps
T1144 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2335032214 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:35 PM UTC 24 1965420976 ps
T1145 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3605857147 Sep 09 07:13:27 PM UTC 24 Sep 09 07:13:35 PM UTC 24 2050388893 ps
T1146 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.4274291782 Sep 09 07:11:36 PM UTC 24 Sep 09 07:13:35 PM UTC 24 71709386695 ps
T1147 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.693760265 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:35 PM UTC 24 2321678360 ps
T1148 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.2369183734 Sep 09 07:13:28 PM UTC 24 Sep 09 07:13:35 PM UTC 24 240668468 ps
T1149 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3561929622 Sep 09 07:12:57 PM UTC 24 Sep 09 07:13:36 PM UTC 24 14743609821 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1001934594 Sep 09 07:10:21 PM UTC 24 Sep 09 07:13:38 PM UTC 24 100527046240 ps
T1150 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3785318671 Sep 09 07:11:01 PM UTC 24 Sep 09 07:13:42 PM UTC 24 20191019736 ps
T1151 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.489960919 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:45 PM UTC 24 107632947 ps
T1152 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3736666329 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:46 PM UTC 24 95031816 ps
T1153 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3092955647 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 157154570 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1802575809 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 259161528 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.2680674088 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 1881278476 ps
T1154 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3527071524 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:46 PM UTC 24 205081387 ps
T1155 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.233973113 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 211351418 ps
T1156 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.4216251515 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 178282654 ps
T1157 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.1993769510 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 137401791 ps
T1158 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2779048060 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 167682749 ps
T1159 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.749688174 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:46 PM UTC 24 259086481 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.1559524338 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:46 PM UTC 24 2001955945 ps
T1160 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.3955717548 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 263498714 ps
T1161 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.2990857770 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:47 PM UTC 24 211071140 ps
T1162 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.2532826173 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 313992173 ps
T1163 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.2448442161 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:47 PM UTC 24 215090169 ps
T1164 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2632460959 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 141082504 ps
T1165 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1323866167 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 2106365799 ps
T1166 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3135620379 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 290632400 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.1553041547 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 294081740 ps
T1167 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.2592308410 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 394959800 ps
T1168 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2551193516 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:47 PM UTC 24 1476965341 ps
T1169 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.305647842 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 159756433 ps
T1170 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.840006627 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 403564991 ps
T1171 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2594078583 Sep 09 07:13:41 PM UTC 24 Sep 09 07:13:47 PM UTC 24 189095917 ps
T1172 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3171751898 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:47 PM UTC 24 348323700 ps
T1173 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.3750569710 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:48 PM UTC 24 295232768 ps
T1174 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3708271676 Sep 09 07:13:42 PM UTC 24 Sep 09 07:13:48 PM UTC 24 1731631324 ps
T1175 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.4048928510 Sep 09 07:11:08 PM UTC 24 Sep 09 07:13:55 PM UTC 24 8201015191 ps
T1176 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.861388689 Sep 09 07:11:34 PM UTC 24 Sep 09 07:15:03 PM UTC 24 62474079661 ps
T1177 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2522891539 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:30 AM UTC 24 37284902 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4017168326 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:30 AM UTC 24 41004882 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3513810232 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:31 AM UTC 24 269105659 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.160429271 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:31 AM UTC 24 49515686 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3940324140 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:32 AM UTC 24 213365477 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3466256095 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:33 AM UTC 24 204027667 ps
T1178 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1902708665 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:33 AM UTC 24 396431222 ps
T1179 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3013785624 Sep 09 11:45:26 AM UTC 24 Sep 09 11:45:35 AM UTC 24 41218872 ps
T1180 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.131732081 Sep 09 11:45:26 AM UTC 24 Sep 09 11:45:35 AM UTC 24 131542980 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2292324188 Sep 09 11:45:27 AM UTC 24 Sep 09 11:45:35 AM UTC 24 3717374034 ps
T1181 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.432683820 Sep 09 11:45:32 AM UTC 24 Sep 09 11:45:36 AM UTC 24 54996718 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3120869579 Sep 09 11:45:31 AM UTC 24 Sep 09 11:45:36 AM UTC 24 111703367 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2046420236 Sep 09 11:45:31 AM UTC 24 Sep 09 11:45:36 AM UTC 24 110581008 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2387610598 Sep 09 11:45:31 AM UTC 24 Sep 09 11:45:36 AM UTC 24 1628664754 ps
T1182 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4042354186 Sep 09 11:45:26 AM UTC 24 Sep 09 11:45:38 AM UTC 24 292275965 ps
T1183 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2249653503 Sep 09 11:45:37 AM UTC 24 Sep 09 11:45:40 AM UTC 24 40395325 ps
T1184 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1076149535 Sep 09 11:45:37 AM UTC 24 Sep 09 11:45:40 AM UTC 24 554498734 ps
T1185 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3032636766 Sep 09 11:45:30 AM UTC 24 Sep 09 11:45:40 AM UTC 24 620259172 ps
T1186 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.1006464581 Sep 09 11:45:37 AM UTC 24 Sep 09 11:45:40 AM UTC 24 39704260 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1465291718 Sep 09 11:45:30 AM UTC 24 Sep 09 11:45:41 AM UTC 24 572560728 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2118747939 Sep 09 11:45:30 AM UTC 24 Sep 09 11:45:41 AM UTC 24 136461126 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2314074243 Sep 09 11:45:35 AM UTC 24 Sep 09 11:45:41 AM UTC 24 99073356 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3073082547 Sep 09 11:45:38 AM UTC 24 Sep 09 11:45:42 AM UTC 24 101690673 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.176283320 Sep 09 11:45:36 AM UTC 24 Sep 09 11:45:42 AM UTC 24 68364268 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3425046024 Sep 09 11:45:31 AM UTC 24 Sep 09 11:45:42 AM UTC 24 473316084 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3643128242 Sep 09 11:45:36 AM UTC 24 Sep 09 11:45:43 AM UTC 24 228744707 ps
T1187 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3926222958 Sep 09 11:45:30 AM UTC 24 Sep 09 11:45:43 AM UTC 24 65730200 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4226240183 Sep 09 11:45:40 AM UTC 24 Sep 09 11:45:43 AM UTC 24 174224177 ps
T1188 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3651005463 Sep 09 11:45:47 AM UTC 24 Sep 09 11:45:52 AM UTC 24 295654864 ps
T1189 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1113424392 Sep 09 11:45:34 AM UTC 24 Sep 09 11:45:43 AM UTC 24 136834284 ps
T1190 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.452546382 Sep 09 11:45:36 AM UTC 24 Sep 09 11:45:44 AM UTC 24 172116624 ps
T1191 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2741094841 Sep 09 11:45:34 AM UTC 24 Sep 09 11:45:44 AM UTC 24 42631633 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3128975893 Sep 09 11:45:26 AM UTC 24 Sep 09 11:45:44 AM UTC 24 2573919535 ps
T1192 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.2288455460 Sep 09 11:45:34 AM UTC 24 Sep 09 11:45:44 AM UTC 24 569846304 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.732161809 Sep 09 11:45:36 AM UTC 24 Sep 09 11:45:44 AM UTC 24 557880774 ps
T1193 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2755324058 Sep 09 11:45:30 AM UTC 24 Sep 09 11:45:44 AM UTC 24 508052222 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2692086729 Sep 09 11:45:41 AM UTC 24 Sep 09 11:45:44 AM UTC 24 167319212 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3902221026 Sep 09 11:45:36 AM UTC 24 Sep 09 11:45:45 AM UTC 24 302803932 ps
T1194 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1368549967 Sep 09 11:45:43 AM UTC 24 Sep 09 11:45:45 AM UTC 24 138458779 ps
T1195 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2271999861 Sep 09 11:45:43 AM UTC 24 Sep 09 11:45:45 AM UTC 24 42787629 ps
T1196 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3271819394 Sep 09 11:45:43 AM UTC 24 Sep 09 11:45:45 AM UTC 24 66788346 ps
T1197 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1841654782 Sep 09 11:45:36 AM UTC 24 Sep 09 11:45:45 AM UTC 24 271450360 ps
T1198 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1318986140 Sep 09 11:45:41 AM UTC 24 Sep 09 11:45:46 AM UTC 24 177064442 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3191420971 Sep 09 11:45:43 AM UTC 24 Sep 09 11:45:46 AM UTC 24 195366163 ps
T1199 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.2442279034 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:47 AM UTC 24 577913203 ps
T1200 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3252932272 Sep 09 11:45:41 AM UTC 24 Sep 09 11:45:47 AM UTC 24 207200780 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.4089586479 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:47 AM UTC 24 75760054 ps
T1201 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3248050504 Sep 09 11:45:41 AM UTC 24 Sep 09 11:45:47 AM UTC 24 154087312 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2272450907 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:47 AM UTC 24 100038948 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3492693025 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:48 AM UTC 24 99138559 ps
T1202 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1554666286 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:48 AM UTC 24 235873176 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3153789138 Sep 09 11:45:41 AM UTC 24 Sep 09 11:45:49 AM UTC 24 894202357 ps
T1203 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2293152023 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:50 AM UTC 24 1583318712 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.688571600 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:50 AM UTC 24 273172368 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3064104185 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:50 AM UTC 24 109033140 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1188182604 Sep 09 11:45:32 AM UTC 24 Sep 09 11:45:50 AM UTC 24 2428305341 ps
T1204 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.3309110663 Sep 09 11:45:47 AM UTC 24 Sep 09 11:45:51 AM UTC 24 38647593 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1430063407 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:51 AM UTC 24 166154268 ps
T1205 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.2305243520 Sep 09 11:45:48 AM UTC 24 Sep 09 11:45:51 AM UTC 24 537715553 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2790756653 Sep 09 11:45:47 AM UTC 24 Sep 09 11:45:51 AM UTC 24 164252255 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1701141107 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:51 AM UTC 24 490512720 ps
T1206 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2360432203 Sep 09 11:45:47 AM UTC 24 Sep 09 11:45:51 AM UTC 24 86373423 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.712731271 Sep 09 11:45:48 AM UTC 24 Sep 09 11:45:52 AM UTC 24 135875156 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3538696354 Sep 09 11:45:45 AM UTC 24 Sep 09 11:45:52 AM UTC 24 45007178 ps
T1207 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1132153886 Sep 09 11:45:47 AM UTC 24 Sep 09 11:45:52 AM UTC 24 119559963 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.128718979 Sep 09 11:45:37 AM UTC 24 Sep 09 11:45:52 AM UTC 24 10329540623 ps
T1208 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2181530172 Sep 09 11:45:48 AM UTC 24 Sep 09 11:45:52 AM UTC 24 144872398 ps
T1209 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1071121661 Sep 09 11:45:45 AM UTC 24 Sep 09 11:45:52 AM UTC 24 111665735 ps
T1210 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1793729434 Sep 09 11:45:48 AM UTC 24 Sep 09 11:45:53 AM UTC 24 330997939 ps
T1211 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3445636006 Sep 09 11:45:44 AM UTC 24 Sep 09 11:45:53 AM UTC 24 1679562712 ps
T1212 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1852011979 Sep 09 11:45:45 AM UTC 24 Sep 09 11:45:54 AM UTC 24 50211609 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.106797069 Sep 09 11:45:49 AM UTC 24 Sep 09 11:45:55 AM UTC 24 82018183 ps
T1213 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3690864931 Sep 09 11:45:53 AM UTC 24 Sep 09 11:45:55 AM UTC 24 38686873 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1388472663 Sep 09 11:45:53 AM UTC 24 Sep 09 11:45:55 AM UTC 24 70880123 ps
T1214 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2870383431 Sep 09 11:45:45 AM UTC 24 Sep 09 11:45:55 AM UTC 24 399537833 ps
T1215 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.1244303411 Sep 09 11:45:51 AM UTC 24 Sep 09 11:45:55 AM UTC 24 604736510 ps
T1216 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.184841024 Sep 09 11:45:49 AM UTC 24 Sep 09 11:45:55 AM UTC 24 76526292 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3930427214 Sep 09 11:45:51 AM UTC 24 Sep 09 11:45:56 AM UTC 24 679832678 ps
T1217 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.636606579 Sep 09 11:45:49 AM UTC 24 Sep 09 11:45:56 AM UTC 24 138370743 ps
T1218 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3074768278 Sep 09 11:45:51 AM UTC 24 Sep 09 11:45:56 AM UTC 24 75240243 ps
T1219 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1095575542 Sep 09 11:45:53 AM UTC 24 Sep 09 11:45:56 AM UTC 24 85659768 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1966087390 Sep 09 11:45:28 AM UTC 24 Sep 09 11:45:56 AM UTC 24 20202953319 ps
T1220 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2097349079 Sep 09 11:45:51 AM UTC 24 Sep 09 11:45:56 AM UTC 24 118559703 ps
T1221 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2126293962 Sep 09 11:45:53 AM UTC 24 Sep 09 11:45:57 AM UTC 24 206323759 ps
T1222 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2494641539 Sep 09 11:45:51 AM UTC 24 Sep 09 11:45:57 AM UTC 24 372721185 ps
T1223 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1783541930 Sep 09 11:45:51 AM UTC 24 Sep 09 11:45:57 AM UTC 24 116874499 ps
T1224 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1554187851 Sep 09 11:45:45 AM UTC 24 Sep 09 11:45:58 AM UTC 24 189910829 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2457162235 Sep 09 11:45:47 AM UTC 24 Sep 09 11:45:58 AM UTC 24 2590994067 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1271880725 Sep 09 11:45:41 AM UTC 24 Sep 09 11:46:00 AM UTC 24 2475342040 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3321982535 Sep 09 11:45:48 AM UTC 24 Sep 09 11:46:00 AM UTC 24 1728355886 ps
T1225 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1579269940 Sep 09 11:45:58 AM UTC 24 Sep 09 11:46:00 AM UTC 24 78125336 ps
T1226 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.4206923246 Sep 09 11:45:54 AM UTC 24 Sep 09 11:46:00 AM UTC 24 73419764 ps
T1227 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2082832637 Sep 09 11:45:54 AM UTC 24 Sep 09 11:46:00 AM UTC 24 107305710 ps
T1228 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1138871154 Sep 09 11:46:11 AM UTC 24 Sep 09 11:46:14 AM UTC 24 82383403 ps
T1229 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.3582104565 Sep 09 11:45:56 AM UTC 24 Sep 09 11:46:00 AM UTC 24 571784363 ps
T1230 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.337415431 Sep 09 11:45:56 AM UTC 24 Sep 09 11:46:00 AM UTC 24 38293960 ps
T1231 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1980057043 Sep 09 11:45:54 AM UTC 24 Sep 09 11:46:00 AM UTC 24 42108461 ps
T1232 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.897233626 Sep 09 11:45:56 AM UTC 24 Sep 09 11:46:00 AM UTC 24 167029223 ps
T1233 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2415311215 Sep 09 11:45:56 AM UTC 24 Sep 09 11:46:01 AM UTC 24 695142234 ps
T1234 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.133144769 Sep 09 11:45:55 AM UTC 24 Sep 09 11:46:01 AM UTC 24 39894711 ps
T1235 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1271689067 Sep 09 11:45:57 AM UTC 24 Sep 09 11:46:01 AM UTC 24 66261269 ps
T1236 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3845992403 Sep 09 11:45:59 AM UTC 24 Sep 09 11:46:01 AM UTC 24 47312151 ps
T1237 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1539080851 Sep 09 11:45:54 AM UTC 24 Sep 09 11:46:01 AM UTC 24 101984522 ps
T1238 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1526260572 Sep 09 11:45:56 AM UTC 24 Sep 09 11:46:02 AM UTC 24 240597053 ps
T1239 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3515777582 Sep 09 11:45:57 AM UTC 24 Sep 09 11:46:02 AM UTC 24 223086889 ps
T1240 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.96416080 Sep 09 11:45:57 AM UTC 24 Sep 09 11:46:04 AM UTC 24 692967236 ps
T1241 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3428402413 Sep 09 11:45:56 AM UTC 24 Sep 09 11:46:04 AM UTC 24 1289728255 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2351421908 Sep 09 11:45:44 AM UTC 24 Sep 09 11:46:05 AM UTC 24 1438527619 ps
T1242 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.902327969 Sep 09 11:46:01 AM UTC 24 Sep 09 11:46:05 AM UTC 24 75374143 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3237257226 Sep 09 11:45:45 AM UTC 24 Sep 09 11:46:05 AM UTC 24 2558625538 ps
T1243 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1512723626 Sep 09 11:46:01 AM UTC 24 Sep 09 11:46:05 AM UTC 24 639746108 ps
T1244 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.54861056 Sep 09 11:46:02 AM UTC 24 Sep 09 11:46:05 AM UTC 24 81745965 ps
T1245 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.760454285 Sep 09 11:46:01 AM UTC 24 Sep 09 11:46:05 AM UTC 24 281861184 ps
T1246 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1602452148 Sep 09 11:46:01 AM UTC 24 Sep 09 11:46:05 AM UTC 24 564087914 ps
T1247 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3065915432 Sep 09 11:45:59 AM UTC 24 Sep 09 11:46:05 AM UTC 24 54692868 ps
T1248 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3741778284 Sep 09 11:45:46 AM UTC 24 Sep 09 11:46:05 AM UTC 24 126840778 ps
T1249 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3865918469 Sep 09 11:46:02 AM UTC 24 Sep 09 11:46:05 AM UTC 24 77624625 ps
T1250 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3613597418 Sep 09 11:45:59 AM UTC 24 Sep 09 11:46:05 AM UTC 24 72342237 ps
T1251 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2728985509 Sep 09 11:46:02 AM UTC 24 Sep 09 11:46:06 AM UTC 24 587343844 ps
T1252 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.3005331215 Sep 09 11:46:11 AM UTC 24 Sep 09 11:46:14 AM UTC 24 39375053 ps
T1253 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3177311593 Sep 09 11:46:11 AM UTC 24 Sep 09 11:46:14 AM UTC 24 56234856 ps
T1254 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.630049627 Sep 09 11:46:01 AM UTC 24 Sep 09 11:46:06 AM UTC 24 352453139 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2356720391 Sep 09 11:46:02 AM UTC 24 Sep 09 11:46:06 AM UTC 24 46575134 ps
T1255 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3440620391 Sep 09 11:45:53 AM UTC 24 Sep 09 11:46:06 AM UTC 24 80855022 ps
T1256 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3245863287 Sep 09 11:45:53 AM UTC 24 Sep 09 11:46:06 AM UTC 24 141614736 ps
T1257 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1019354649 Sep 09 11:46:03 AM UTC 24 Sep 09 11:46:07 AM UTC 24 65451655 ps
T1258 /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3530863891 Sep 09 11:46:01 AM UTC 24 Sep 09 11:46:07 AM UTC 24 633522945 ps
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