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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A	0	0	77900107	227921	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A	0	0	77900107	116659	0	0
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A	0	0	77900107	240027	0	0
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A	0	0	1116	1116	0	0
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_rsp_fifo.DataKnown_A	0	0	77900107	13729975	0	0
tb.dut.u_otp_rsp_fifo.DepthKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_rsp_fifo.RvalidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_rsp_fifo.WreadyKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	77900107	13729975	0	0
tb.dut.u_part_sel_idx.CheckHotOne_A	0	0	77900107	77088315	0	0
tb.dut.u_part_sel_idx.CheckNGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_part_sel_idx.GrantKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_part_sel_idx.IdxKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_part_sel_idx.Priority_A	0	0	77900107	77088315	0	0
tb.dut.u_part_sel_idx.ReqImpliesValid_A	0	0	77900107	77088315	0	0
tb.dut.u_part_sel_idx.ValidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A	0	0	77900107	29728092	0	0
tb.dut.u_prim_edn_req.DataOutputValid_A	0	0	77900107	196667	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	77900107	393811	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	77900107	393711	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	187953296	394055	0	0
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	77900107	196459	0	0
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_reg_core.en2addrHit	0	0	80837848	6189638	0	0
tb.dut.u_reg_core.reAfterRv	0	0	80837848	6189638	0	0
tb.dut.u_reg_core.rePulse	0	0	80837848	5336118	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	80837848	8712685	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	80837848	12483061	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	80837848	1177494	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	80837848	971837	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	80837848	7027895	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	80837848	11511224	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	80837848	79974703	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1291	1291	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1291	1291	0	0
tb.dut.u_reg_core.wePulse	0	0	80837848	853520	0	0
tb.dut.u_scrmbl_mtx.CheckHotOne_A	0	0	77900107	77088315	0	0
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_scrmbl_mtx.GrantKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_scrmbl_mtx.IdxKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A	0	0	77900107	43603975	0	0
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A	0	0	77900107	33484340	0	0
tb.dut.u_scrmbl_mtx.ValidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.WeOutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty	0	0	77900107	75911	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull	0	0	77900107	75911	0	0
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A	0	0	77900107	1369674	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	77900107	1369674	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A	0	0	77900107	178204	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	77900107	178204	0	0
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg	0	0	1116	1116	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A	0	0	77900107	503486	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	77900107	503486	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1116	1116	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A	0	0	1116	1116	0	0
tb.dut.u_tlul_lc_gate.u_state_regs_A	0	0	77900107	77088315	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1116	1116	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1116	1116	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_arb.RoundRobin_A	0	0	77900107	0	0	1105
tb.dut.u_otp_arb.RoundRobin_A	0	0	77900107	0	0	1105
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	77900107	0	0	1105
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	77900107	0	0	1105
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	77900107	77050712	0	3315
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	77900107	0	0	1105

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	80838747	923	923	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	80838747	202	202	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	80838747	204	204	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	80838747	130	130	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	80838747	27	27	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	80838747	106	106	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	80838747	29	29	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	80838747	2915	2915	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	80838747	6339	6339	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	80838747	3030912	3030912	1212
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	80838747	332	332	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	80838747	60	60	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	80838747	63	63	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	80838747	41	41	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	80838747	2	2	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	80838747	34	34	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	80838747	13	13	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	80838747	735	735	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	80838747	2190	2190	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	80838747	52946	52946	55

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	80838747	923	923	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	80838747	202	202	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	80838747	204	204	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	80838747	130	130	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	80838747	27	27	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	80838747	106	106	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	80838747	29	29	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	80838747	2915	2915	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	80838747	6339	6339	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	80838747	3030912	3030912	1212
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	80838747	332	332	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	80838747	60	60	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	80838747	63	63	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	80838747	41	41	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	80838747	2	2	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	80838747	34	34	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	80838747	13	13	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	80838747	735	735	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	80838747	2190	2190	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	80838747	52946	52946	55